llvm.org GIT mirror llvm / b26ede0
[NVPTX] Flag surface/texture query instructions with IsTexSurfQuery Also, add some tests to make sure we can handle surface/texture queries on both Fermi and Kepler+. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213268 91177308-0d34-0410-b5e6-96231b3b80d8 Justin Holewinski 6 years ago
2 changed file(s) with 109 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
42404240 //-----------------------------------
42414241 // Texture Query Intrinsics
42424242 //-----------------------------------
4243
4244 let IsSurfTexQuery = 1 in {
42434245 def TXQ_CHANNEL_ORDER
42444246 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
42454247 "txq.channel_order.b32 \t$d, [$a];",
42724274 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
42734275 "txq.num_mipmap_levels.b32 \t$d, [$a];",
42744276 []>;
4277 }
42754278
42764279 def : Pat<(int_nvvm_txq_channel_order Int64Regs:$a),
42774280 (TXQ_CHANNEL_ORDER Int64Regs:$a)>;
42944297 //-----------------------------------
42954298 // Surface Query Intrinsics
42964299 //-----------------------------------
4300
4301 let IsSurfTexQuery = 1 in {
42974302 def SUQ_CHANNEL_ORDER
42984303 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
42994304 "suq.channel_order.b32 \t$d, [$a];",
43184323 : NVPTXInst<(outs Int32Regs:$d), (ins Int64Regs:$a),
43194324 "suq.array_size.b32 \t$d, [$a];",
43204325 []>;
4326 }
43214327
43224328 def : Pat<(int_nvvm_suq_channel_order Int64Regs:$a),
43234329 (SUQ_CHANNEL_ORDER Int64Regs:$a)>;
0 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20
1 ; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30
2
3 target triple = "nvptx-unknown-cuda"
4
5 @tex0 = internal addrspace(1) global i64 0, align 8
6 @surf0 = internal addrspace(1) global i64 0, align 8
7
8 declare i32 @llvm.nvvm.txq.width(i64)
9 declare i32 @llvm.nvvm.txq.height(i64)
10 declare i32 @llvm.nvvm.suq.width(i64)
11 declare i32 @llvm.nvvm.suq.height(i64)
12 declare i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)*)
13
14
15 ; SM20-LABEL: @t0
16 ; SM30-LABEL: @t0
17 define i32 @t0(i64 %texHandle) {
18 ; SM20: txq.width.b32
19 ; SM30: txq.width.b32
20 %width = tail call i32 @llvm.nvvm.txq.width(i64 %texHandle)
21 ret i32 %width
22 }
23
24 ; SM20-LABEL: @t1
25 ; SM30-LABEL: @t1
26 define i32 @t1() {
27 ; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], tex0
28 %texHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @tex0)
29 ; SM20: txq.width.b32 %r{{[0-9]+}}, [tex0]
30 ; SM30: txq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
31 %width = tail call i32 @llvm.nvvm.txq.width(i64 %texHandle)
32 ret i32 %width
33 }
34
35
36 ; SM20-LABEL: @t2
37 ; SM30-LABEL: @t2
38 define i32 @t2(i64 %texHandle) {
39 ; SM20: txq.height.b32
40 ; SM30: txq.height.b32
41 %height = tail call i32 @llvm.nvvm.txq.height(i64 %texHandle)
42 ret i32 %height
43 }
44
45 ; SM20-LABEL: @t3
46 ; SM30-LABEL: @t3
47 define i32 @t3() {
48 ; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], tex0
49 %texHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @tex0)
50 ; SM20: txq.height.b32 %r{{[0-9]+}}, [tex0]
51 ; SM30: txq.height.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
52 %height = tail call i32 @llvm.nvvm.txq.height(i64 %texHandle)
53 ret i32 %height
54 }
55
56
57 ; SM20-LABEL: @s0
58 ; SM30-LABEL: @s0
59 define i32 @s0(i64 %surfHandle) {
60 ; SM20: suq.width.b32
61 ; SM30: suq.width.b32
62 %width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle)
63 ret i32 %width
64 }
65
66 ; SM20-LABEL: @s1
67 ; SM30-LABEL: @s1
68 define i32 @s1() {
69 ; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], surf0
70 %surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf0)
71 ; SM20: suq.width.b32 %r{{[0-9]+}}, [surf0]
72 ; SM30: suq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
73 %width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle)
74 ret i32 %width
75 }
76
77
78 ; SM20-LABEL: @s2
79 ; SM30-LABEL: @s2
80 define i32 @s2(i64 %surfHandle) {
81 ; SM20: suq.height.b32
82 ; SM30: suq.height.b32
83 %height = tail call i32 @llvm.nvvm.suq.height(i64 %surfHandle)
84 ret i32 %height
85 }
86
87 ; SM20-LABEL: @s3
88 ; SM30-LABEL: @s3
89 define i32 @s3() {
90 ; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], surf0
91 %surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf0)
92 ; SM20: suq.height.b32 %r{{[0-9]+}}, [surf0]
93 ; SM30: suq.height.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
94 %height = tail call i32 @llvm.nvvm.suq.height(i64 %surfHandle)
95 ret i32 %height
96 }
97
98
99
100 !nvvm.annotations = !{!1, !2}
101 !1 = metadata !{i64 addrspace(1)* @tex0, metadata !"texture", i32 1}
102 !2 = metadata !{i64 addrspace(1)* @surf0, metadata !"surface", i32 1}