llvm.org GIT mirror llvm / b26e6ec
Whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196203 91177308-0d34-0410-b5e6-96231b3b80d8 NAKAMURA Takumi 5 years ago
1 changed file(s) with 177 addition(s) and 178 deletion(s). Raw diff Collapse all Expand all
226226 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
227227 // two operands constraints.
228228 class NeonI_3VSame_Constraint_impl
229 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
229 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
230230 bits<5> opcode, SDPatternOperator opnode>
231231 : NeonI_3VSame
232232 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
14441444 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
14451445 }
14461446
1447 // Vector Shift (Immediate)
1447 // Vector Shift (Immediate)
14481448 // Immediate in [0, 63]
14491449 def imm0_63 : Operand {
14501450 let ParserMatchClass = uimm6_asmoperand;
14721472 class shr_imm : Operand {
14731473 let EncoderMethod = "getShiftRightImm" # OFFSET;
14741474 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1475 let ParserMatchClass =
1475 let ParserMatchClass =
14761476 !cast("shr_imm" # OFFSET # "_asmoperand");
14771477 }
14781478
14951495 class shl_imm : Operand {
14961496 let EncoderMethod = "getShiftLeftImm" # OFFSET;
14971497 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1498 let ParserMatchClass =
1498 let ParserMatchClass =
14991499 !cast("shl_imm" # OFFSET # "_asmoperand");
15001500 }
15011501
27782778
27792779 // For pattern that need two operators being chained.
27802780 class NeonI_3VDL_Aba size, bits<4> opcode,
2781 string asmop, string ResS, string OpS,
2781 string asmop, string ResS, string OpS,
27822782 SDPatternOperator opnode, SDPatternOperator subop,
27832783 RegisterOperand OpVPR,
27842784 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
27852785 : NeonI_3VDiff
27862786 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2787 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2787 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
27882788 [(set (ResTy VPR128:$Rd),
27892789 (ResTy (opnode
2790 (ResTy VPR128:$src),
2790 (ResTy VPR128:$src),
27912791 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
27922792 (OpTy OpVPR:$Rm))))))))],
27932793 NoItinerary> {
28122812 multiclass NeonI_3VDL2_Aba_v1 opcode, string asmop,
28132813 SDPatternOperator opnode, string subop> {
28142814 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2815 opnode, !cast(subop # "_16B"),
2815 opnode, !cast(subop # "_16B"),
28162816 VPR128, v8i16, v16i8, v8i8>;
28172817 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2818 opnode, !cast(subop # "_8H"),
2818 opnode, !cast(subop # "_8H"),
28192819 VPR128, v4i32, v8i16, v4i16>;
28202820 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2821 opnode, !cast(subop # "_4S"),
2821 opnode, !cast(subop # "_4S"),
28222822 VPR128, v2i64, v4i32, v2i32>;
28232823 }
28242824
29382938 let Constraints = "$src = $Rd";
29392939 }
29402940
2941 multiclass NeonI_3VDL2_3Op_mlas_v1 opcode, string asmop,
2941 multiclass NeonI_3VDL2_3Op_mlas_v1 opcode, string asmop,
29422942 SDPatternOperator subop, string opnode> {
29432943 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
29442944 subop, !cast(opnode # "_16B"),
29452945 VPR128, v8i16, v16i8>;
29462946 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2947 subop, !cast(opnode # "_8H"),
2947 subop, !cast(opnode # "_8H"),
29482948 VPR128, v4i32, v8i16>;
29492949 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
29502950 subop, !cast(opnode # "_4S"),
29892989 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
29902990 int_arm_neon_vqdmull, 1>;
29912991
2992 multiclass NeonI_3VDL2_2Op_mull_v2 opcode, string asmop,
2992 multiclass NeonI_3VDL2_2Op_mull_v2 opcode, string asmop,
29932993 string opnode, bit Commutable = 0> {
29942994 let isCommutable = Commutable in {
29952995 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
30013001 }
30023002 }
30033003
3004 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3004 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
30053005 "NI_qdmull_hi", 1>;
30063006
3007 multiclass NeonI_3VDL2_3Op_qdmlal_v2 opcode, string asmop,
3007 multiclass NeonI_3VDL2_3Op_qdmlal_v2 opcode, string asmop,
30083008 SDPatternOperator opnode> {
30093009 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
30103010 opnode, NI_qdmull_hi_8H,
30243024 let isCommutable = Commutable in {
30253025 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
30263026 opnode, VPR128, VPR64, v8i16, v8i8>;
3027
3027
30283028 def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
30293029 (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
30303030 asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
30343034
30353035 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
30363036
3037 multiclass NeonI_3VDL2_2Op_mull_v3 opcode, string asmop,
3037 multiclass NeonI_3VDL2_2Op_mull_v3 opcode, string asmop,
30383038 string opnode, bit Commutable = 0> {
30393039 let isCommutable = Commutable in {
30403040 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
30413041 !cast(opnode # "_16B"),
30423042 v8i16, v16i8>;
3043
3043
30443044 def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
30453045 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
30463046 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
30613061 // The structure consists of a sequence of sets of N values.
30623062 // The first element of the structure is placed in the first lane
30633063 // of the first first vector, the second element in the first lane
3064 // of the second vector, and so on.
3064 // of the second vector, and so on.
30653065 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
30663066 // the three 64-bit vectors list {BA, DC, FE}.
30673067 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
31263126 class NeonI_STVList opcode, bits<2> size,
31273127 RegisterOperand VecList, string asmop>
31283128 : NeonI_LdStMult
3129 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3129 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
31303130 asmop # "\t$Rt, [$Rn]",
3131 [],
3131 [],
31323132 NoItinerary> {
31333133 let mayStore = 1;
31343134 let neverHasSideEffects = 1;
33403340 multiclass NeonI_LDWB_VList opcode, bits<2> size,
33413341 RegisterOperand VecList, Operand ImmTy,
33423342 string asmop> {
3343 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3343 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
33443344 DecoderMethod = "DecodeVLDSTPostInstruction" in {
33453345 def _fixed : NeonI_LdStMult_Post
33463346 (outs VecList:$Rt, GPR64xsp:$wb),
3347 (ins GPR64xsp:$Rn, ImmTy:$amt),
3347 (ins GPR64xsp:$Rn, ImmTy:$amt),
33483348 asmop # "\t$Rt, [$Rn], $amt",
33493349 [],
33503350 NoItinerary> {
33533353
33543354 def _register : NeonI_LdStMult_Post
33553355 (outs VecList:$Rt, GPR64xsp:$wb),
3356 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3356 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
33573357 asmop # "\t$Rt, [$Rn], $Rm",
33583358 [],
33593359 NoItinerary>;
34363436
34373437 def _register : NeonI_LdStMult_Post
34383438 (outs GPR64xsp:$wb),
3439 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3439 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
34403440 asmop # "\t$Rt, [$Rn], $Rm",
34413441 [],
34423442 NoItinerary>;
35773577 // Load single 1-element structure to all lanes of 1 register
35783578 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
35793579
3580 // Load single N-element structure to all lanes of N consecutive
3580 // Load single N-element structure to all lanes of N consecutive
35813581 // registers (N = 2,3,4)
35823582 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
35833583 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
36613661 let Inst{12-10} = {lane{0}, 0b0, 0b0};
36623662 let Inst{30} = lane{1};
36633663 }
3664
3664
36653665 def _D : NeonI_LDN_Lane
36663666 !cast(List # "D_operand"),
36673667 neon_uimm1_bare, asmop> {
36843684 Instruction INST> {
36853685 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
36863686 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3687 (VTy (EXTRACT_SUBREG
3688 (INST GPR64xsp:$Rn,
3687 (VTy (EXTRACT_SUBREG
3688 (INST GPR64xsp:$Rn,
36893689 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
36903690 ImmOp:$lane),
36913691 sub_64))>;
37453745 let Inst{12-10} = {lane{0}, 0b0, 0b0};
37463746 let Inst{30} = lane{1};
37473747 }
3748
3748
37493749 def _D : NeonI_STN_Lane
37503750 !cast(List # "D_operand"),
37513751 neon_uimm1_bare, asmop>{
38633863 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
38643864 uimm_exact2, uimm_exact4, uimm_exact8>;
38653865
3866 // Post-index load single N-element structure to all lanes of N consecutive
3866 // Post-index load single N-element structure to all lanes of N consecutive
38673867 // registers (N = 2,3,4)
38683868 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
38693869 uimm_exact4, uimm_exact8, uimm_exact16>;
38723872 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
38733873 uimm_exact8, uimm_exact16, uimm_exact32>;
38743874
3875 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3875 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
38763876 Constraints = "$Rn = $wb, $Rt = $src",
38773877 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
38783878 class LDN_WBFx_Lane op2_1, bit op0, RegisterOperand VList,
39143914 let Inst{12-10} = lane{2-0};
39153915 let Inst{30} = lane{3};
39163916 }
3917
3917
39183918 def _H_fixed : LDN_WBFx_Lane
39193919 !cast(List # "H_operand"),
39203920 uimm_h, neon_uimm3_bare, asmop> {
39213921 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
39223922 let Inst{30} = lane{2};
39233923 }
3924
3924
39253925 def _H_register : LDN_WBReg_Lane
39263926 !cast(List # "H_operand"),
39273927 uimm_h, neon_uimm3_bare, asmop> {
39423942 let Inst{12-10} = {lane{0}, 0b0, 0b0};
39433943 let Inst{30} = lane{1};
39443944 }
3945
3945
39463946 def _D_fixed : LDN_WBFx_Lane
39473947 !cast(List # "D_operand"),
39483948 uimm_d, neon_uimm1_bare, asmop> {
40144014 let Inst{12-10} = lane{2-0};
40154015 let Inst{30} = lane{3};
40164016 }
4017
4017
40184018 def _H_fixed : STN_WBFx_Lane
40194019 !cast(List # "H_operand"),
40204020 uimm_h, neon_uimm3_bare, asmop> {
40214021 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
40224022 let Inst{30} = lane{2};
40234023 }
4024
4024
40254025 def _H_register : STN_WBReg_Lane
40264026 !cast(List # "H_operand"),
40274027 uimm_h, neon_uimm3_bare, asmop> {
40424042 let Inst{12-10} = {lane{0}, 0b0, 0b0};
40434043 let Inst{30} = lane{1};
40444044 }
4045
4045
40464046 def _D_fixed : STN_WBFx_Lane
40474047 !cast(List # "D_operand"),
40484048 uimm_d, neon_uimm1_bare, asmop> {
41174117 multiclass Neon_Scalar3Same_D_size_patterns
41184118 Instruction INSTD> {
41194119 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4120 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4120 (INSTD FPR64:$Rn, FPR64:$Rm)>;
41214121 }
41224122
41234123 multiclass Neon_Scalar3Same_BHSD_size_patterns
52355235 defm : Neon_ScalarPair_SD_size_patterns
52365236 int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
52375237
5238 defm : Neon_ScalarPair_SD_size_patterns
5238 defm : Neon_ScalarPair_SD_size_patterns
52395239 int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
52405240
5241 defm : Neon_ScalarPair_SD_size_patterns
5241 defm : Neon_ScalarPair_SD_size_patterns
52425242 int_aarch64_neon_vaddv, FADDPvv_S_2S, FADDPvv_D_2D>;
52435243
52445244 def : Pat<(v1f32 (int_aarch64_neon_vaddv (v4f32 VPR128:$Rn))),
52475247 (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
52485248 sub_64)))>;
52495249
5250 defm : Neon_ScalarPair_SD_size_patterns
5250 defm : Neon_ScalarPair_SD_size_patterns
52515251 int_aarch64_neon_vmaxv, FMAXPvv_S_2S, FMAXPvv_D_2D>;
52525252
5253 defm : Neon_ScalarPair_SD_size_patterns
5253 defm : Neon_ScalarPair_SD_size_patterns
52545254 int_aarch64_neon_vminv, FMINPvv_S_2S, FMINPvv_D_2D>;
52555255
5256 defm : Neon_ScalarPair_SD_size_patterns
5256 defm : Neon_ScalarPair_SD_size_patterns
52575257 int_aarch64_neon_vmaxnmv, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
52585258
5259 defm : Neon_ScalarPair_SD_size_patterns
5259 defm : Neon_ScalarPair_SD_size_patterns
52605260 int_aarch64_neon_vminnmv, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
52615261
52625262 // Scalar by element Arithmetic
60536053 string OpS, RegisterOperand OpVPR, Operand OpImm>
60546054 : NeonI_BitExtract
60556055 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6056 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6056 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
60576057 ", $Rm." # OpS # ", $Index",
60586058 [],
60596059 NoItinerary>{
60716071 }
60726072
60736073 class NI_Extract
6074 Operand OpImm>
6074 Operand OpImm>
60756075 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
60766076 (i64 OpImm:$Imm))),
60776077 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
61826182 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
61836183
61846184 class Neon_INS_main_pattern
6185 RegisterClass OpGPR, ValueType OpTy,
6186 Operand OpImm, Instruction INS>
6185 RegisterClass OpGPR, ValueType OpTy,
6186 Operand OpImm, Instruction INS>
61876187 : Pat<(ResTy (vector_insert
61886188 (ResTy VPR64:$src),
61896189 (OpTy OpGPR:$Rn),
61906190 (OpImm:$Imm))),
6191 (ResTy (EXTRACT_SUBREG
6191 (ResTy (EXTRACT_SUBREG
61926192 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
61936193 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
61946194
62036203
62046204 class NeonI_INS_element
62056205 : NeonI_insert<0b1, 0b1,
6206 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6206 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
62076207 ResImm:$Immd, ResImm:$Immn),
62086208 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
62096209 [],
63266326 (NaTy VPR64:$src),
63276327 (MidTy OpFPR:$Rn),
63286328 (ResImm:$Imm))),
6329 (NaTy (EXTRACT_SUBREG
6330 (ResTy (INS
6329 (NaTy (EXTRACT_SUBREG
6330 (ResTy (INS
63316331 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
63326332 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
63336333 ResImm:$Imm,
63866386 (StTy VPR128:$Rn), (StImm:$Imm))))),
63876387 eleTy)),
63886388 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6389
6389
63906390 def : Pat<(i64 (sext
63916391 (i32 (vector_extract
63926392 (StTy VPR128:$Rn), (StImm:$Imm))))),
63936393 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6394
6394
63956395 def : Pat<(i64 (sext_inreg
63966396 (i64 (vector_extract
63976397 (NaTy VPR64:$Rn), (NaImm:$Imm))),
63986398 eleTy)),
63996399 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
64006400 NaImm:$Imm)>;
6401
6401
64026402 def : Pat<(i64 (sext_inreg
64036403 (i64 (anyext
64046404 (i32 (vector_extract
64066406 eleTy)),
64076407 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
64086408 NaImm:$Imm)>;
6409
6409
64106410 def : Pat<(i64 (sext
64116411 (i32 (vector_extract
64126412 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
64136413 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6414 NaImm:$Imm)>;
6414 NaImm:$Imm)>;
64156415 }
64166416
64176417 defm : Neon_SMOVx_pattern
64836483 def : Neon_UMOV_pattern
64846484 neon_uimm3_bare, UMOVwb>;
64856485 def : Neon_UMOV_pattern
6486 neon_uimm2_bare, UMOVwh>;
6486 neon_uimm2_bare, UMOVwh>;
64876487 def : Neon_UMOV_pattern
64886488 neon_uimm1_bare, UMOVws>;
64896489
65386538
65396539 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
65406540 (FMOVxd FPR64:$Rn)>;
6541
6541
65426542 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
65436543 (f64 FPR64:$Rn)>;
65446544
66526652 neon_uimm1_bare, neon_uimm0_bare>;
66536653
66546654 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6655 (v2f32 (DUPELT2s
6655 (v2f32 (DUPELT2s
66566656 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
66576657 (i64 0)))>;
66586658 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6659 (v4f32 (DUPELT4s
6659 (v4f32 (DUPELT4s
66606660 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
66616661 (i64 0)))>;
66626662 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6663 (v2f64 (DUPELT2d
6663 (v2f64 (DUPELT2d
66646664 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
66656665 (i64 0)))>;
66666666
66696669 RegisterClass OpGPR, ValueType OpTy>
66706670 : NeonI_copy
66716671 asmop # "\t$Rd" # rdlane # ", $Rn",
6672 [(set (ResTy ResVPR:$Rd),
6672 [(set (ResTy ResVPR:$Rd),
66736673 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
66746674 NoItinerary>;
66756675
67136713 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
67146714 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
67156715 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6716 (INSELd
6716 (INSELd
67176717 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
67186718 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
67196719 (i64 1),
67206720 (i64 0))>;
67216721 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6722 (DUPELT2d
6722 (DUPELT2d
67236723 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
67246724 (i64 0))> ;
67256725 }
67536753 string asmop, string ResS, string OpS, string EleOpS,
67546754 Operand OpImm, RegisterOperand ResVPR,
67556755 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6756 : NeonI_2VElem
6756 : NeonI_2VElem
67576757 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
67586758 EleOpVPR:$Re, OpImm:$Index),
67596759 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
68196819 ValueType EleOpTy>
68206820 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
68216821 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6822 (INST ResVPR:$src, OpVPR:$Rn,
6822 (INST ResVPR:$src, OpVPR:$Rn,
68236823 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
68246824
68256825 multiclass NI_2VE_v1_pat
68526852 string asmop, string ResS, string OpS, string EleOpS,
68536853 Operand OpImm, RegisterOperand ResVPR,
68546854 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6855 : NeonI_2VElem
6855 : NeonI_2VElem
68566856 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
68576857 EleOpVPR:$Re, OpImm:$Index),
68586858 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
69156915 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
69166916 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
69176917 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6918 (INST OpVPR:$Rn,
6918 (INST OpVPR:$Rn,
69196919 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
69206920
69216921 multiclass NI_2VE_mul_v1_pat {
69816981 SDPatternOperator coreop>
69826982 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
69836983 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
6984 (INST OpVPR:$Rn,
6984 (INST OpVPR:$Rn,
69856985 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
69866986
69876987 multiclass NI_2VE_mul_v2_pat {
70397039 }
70407040
70417041 // _1d2d doesn't exist!
7042
7042
70437043 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
70447044 neon_uimm1_bare, VPR128, VPR128, VPR128> {
70457045 let Inst{11} = {Index{0}};
70637063 // Pattern for lane 0
70647064 class NI_2VEfma_lane0
70657065 RegisterOperand ResVPR, ValueType ResTy>
7066 : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7066 : Pat<(ResTy (op (ResTy ResVPR:$Rn),
70677067 (ResTy (Neon_vdup (f32 FPR32:$Re))),
70687068 (ResTy ResVPR:$src))),
70697069 (INST ResVPR:$src, ResVPR:$Rn,
70767076 SDPatternOperator coreop>
70777077 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
70787078 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7079 (INST ResVPR:$src, ResVPR:$Rn,
7079 (INST ResVPR:$src, ResVPR:$Rn,
70807080 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
70817081
70827082 // Pattern for lane in 64-bit vector
70877087 SDPatternOperator coreop>
70887088 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
70897089 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7090 (INST ResVPR:$src, ResVPR:$Rn,
7090 (INST ResVPR:$src, ResVPR:$Rn,
70917091 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
70927092
70937093
71267126 // Pattern for lane 0
71277127 class NI_2VEfms_lane0
71287128 RegisterOperand ResVPR, ValueType ResTy>
7129 : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7129 : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
71307130 (ResTy (Neon_vdup (f32 FPR32:$Re))),
71317131 (ResTy ResVPR:$src))),
71327132 (INST ResVPR:$src, ResVPR:$Rn,
72147214 let Inst{21} = {Index{0}};
72157215 let Inst{20-16} = Re;
72167216 }
7217
7217
72187218 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
72197219 neon_uimm2_bare, VPR128, VPR128, VPR128> {
72207220 let Inst{11} = {Index{1}};
72307230 let Inst{20} = {Index{0}};
72317231 let Inst{19-16} = Re{3-0};
72327232 }
7233
7233
72347234 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
72357235 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
72367236 let Inst{11} = {Index{2}};
72557255 let Inst{21} = {Index{0}};
72567256 let Inst{20-16} = Re;
72577257 }
7258
7258
72597259 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
72607260 neon_uimm2_bare, VPR128, VPR128, VPR128> {
72617261 let Inst{11} = {Index{1}};
72717271 let Inst{20} = {Index{0}};
72727272 let Inst{19-16} = Re{3-0};
72737273 }
7274
7274
72757275 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
72767276 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
72777277 let Inst{11} = {Index{2}};
73107310 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
73117311 (HalfOpTy (Neon_vduplane
73127312 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7313 (INST VPR128:$src, VPR128:$Rn,
7313 (INST VPR128:$src, VPR128:$Rn,
73147314 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
73157315
73167316 class NI_2VEL2_lane0
73247324 multiclass NI_2VEL_v3_pat {
73257325 def : NI_2VE_laneq(subop # "_4s4h"), neon_uimm3_bare,
73267326 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7327
7327
73287328 def : NI_2VE_laneq(subop # "_2d2s"), neon_uimm2_bare,
73297329 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7330
7330
73317331 def : NI_2VEL2_laneq(subop # "_4s8h"), neon_uimm3_bare,
73327332 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7333
7333
73347334 def : NI_2VEL2_laneq(subop # "_2d4s"), neon_uimm2_bare,
73357335 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7336
7337 def : NI_2VEL2_lane0(subop # "_4s8h"),
7336
7337 def : NI_2VEL2_lane0(subop # "_4s8h"),
73387338 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7339
7339
73407340 def : NI_2VEL2_lane0(subop # "_2d4s"),
73417341 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
73427342
73447344
73457345 def : NI_2VE_lane(subop # "_4s4h"), neon_uimm2_bare,
73467346 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7347
7347
73487348 def : NI_2VE_lane(subop # "_2d2s"), neon_uimm1_bare,
73497349 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
73507350
73517351 def : NI_2VEL2_lane(subop # "_4s8h"), neon_uimm2_bare,
73527352 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7353
7353
73547354 def : NI_2VEL2_lane(subop # "_2d4s"), neon_uimm1_bare,
73557355 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
73567356 }
73657365 RegisterOperand EleOpVPR, ValueType ResTy,
73667366 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
73677367 SDPatternOperator hiop>
7368 : Pat<(ResTy (op
7368 : Pat<(ResTy (op
73697369 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
73707370 (HalfOpTy (Neon_vduplane
73717371 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
73807380 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
73817381 (HalfOpTy (Neon_vduplane
73827382 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7383 (INST VPR128:$Rn,
7383 (INST VPR128:$Rn,
73847384 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
73857385
73867386 // Pattern for fixed lane 0
73877387 class NI_2VEL2_mul_lane0
73887388 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
73897389 SDPatternOperator hiop, Instruction DupInst>
7390 : Pat<(ResTy (op
7390 : Pat<(ResTy (op
73917391 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
73927392 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
73937393 (INST VPR128:$Rn, (DupInst $Re), 0)>;
74017401
74027402 def : NI_2VEL2_mul_laneq(subop # "_4s8h"), neon_uimm3_bare,
74037403 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7404
7404
74057405 def : NI_2VEL2_mul_laneq(subop # "_2d4s"), neon_uimm2_bare,
74067406 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
74077407
74087408 def : NI_2VEL2_mul_lane0(subop # "_4s8h"),
74097409 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7410
7410
74117411 def : NI_2VEL2_mul_lane0(subop # "_2d4s"),
74127412 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
74137413
74217421
74227422 def : NI_2VEL2_mul_lane(subop # "_4s8h"), neon_uimm2_bare,
74237423 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7424
7424
74257425 def : NI_2VEL2_mul_lane(subop # "_2d4s"), neon_uimm1_bare,
74267426 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
74277427 }
74477447 def : NI_2VE_laneq(subop # "_4s4h"), neon_uimm3_bare,
74487448 !cast(op # "_4s"), VPR128, VPR64, VPR128Lo,
74497449 v4i32, v4i16, v8i16>;
7450
7450
74517451 def : NI_2VE_laneq(subop # "_2d2s"), neon_uimm2_bare,
74527452 !cast(op # "_2d"), VPR128, VPR64, VPR128,
74537453 v2i64, v2i32, v4i32>;
7454
7454
74557455 def : NI_2VEL2_laneq(subop # "_4s8h"), neon_uimm3_bare,
74567456 !cast(op # "_4s"), VPR128Lo,
74577457 v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7458
7458
74597459 def : NI_2VEL2_laneq(subop # "_2d4s"), neon_uimm2_bare,
74607460 !cast(op # "_2d"), VPR128,
74617461 v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
74627462
74637463 def : NI_2VEL2_lane0(subop # "_4s8h"),
7464 !cast(op # "_4s"),
7464 !cast(op # "_4s"),
74657465 v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7466
7466
74677467 def : NI_2VEL2_lane0(subop # "_2d4s"),
7468 !cast(op # "_2d"),
7468 !cast(op # "_2d"),
74697469 v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7470
7470
74717471 // Index can only be half of the max value for lane in 64-bit vector
74727472
74737473 def : NI_2VE_lane(subop # "_4s4h"), neon_uimm2_bare,
74747474 !cast(op # "_4s"), VPR128, VPR64, VPR64Lo,
74757475 v4i32, v4i16, v4i16>;
7476
7476
74777477 def : NI_2VE_lane(subop # "_2d2s"), neon_uimm1_bare,
74787478 !cast(op # "_2d"), VPR128, VPR64, VPR64,
74797479 v2i64, v2i32, v2i32>;
74817481 def : NI_2VEL2_lane(subop # "_4s8h"), neon_uimm2_bare,
74827482 !cast(op # "_4s"), VPR64Lo,
74837483 v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7484
7484
74857485 def : NI_2VEL2_lane(subop # "_2d4s"), neon_uimm1_bare,
74867486 !cast(op # "_2d"), VPR64,
74877487 v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
75407540 [(set (v8i16 VPR128:$Rd),
75417541 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
75427542 NoItinerary>;
7543
7543
75447544 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
75457545 (outs VPR64:$Rd), (ins VPR64:$Rn),
75467546 asmop # "\t$Rd.4h, $Rn.8b",
75477547 [(set (v4i16 VPR64:$Rd),
75487548 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
75497549 NoItinerary>;
7550
7550
75517551 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
75527552 (outs VPR128:$Rd), (ins VPR128:$Rn),
75537553 asmop # "\t$Rd.4s, $Rn.8h",
75547554 [(set (v4i32 VPR128:$Rd),
75557555 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
75567556 NoItinerary>;
7557
7557
75587558 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
75597559 (outs VPR64:$Rd), (ins VPR64:$Rn),
75607560 asmop # "\t$Rd.2s, $Rn.4h",
75617561 [(set (v2i32 VPR64:$Rd),
75627562 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
75637563 NoItinerary>;
7564
7564
75657565 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
75667566 (outs VPR128:$Rd), (ins VPR128:$Rn),
75677567 asmop # "\t$Rd.2d, $Rn.4s",
75687568 [(set (v2i64 VPR128:$Rd),
75697569 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
75707570 NoItinerary>;
7571
7571
75727572 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
75737573 (outs VPR64:$Rd), (ins VPR64:$Rn),
75747574 asmop # "\t$Rd.1d, $Rn.2s",
75897589 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
75907590 asmop # "\t$Rd.8h, $Rn.16b",
75917591 [(set (v8i16 VPR128:$Rd),
7592 (v8i16 (Neon_Padd
7592 (v8i16 (Neon_Padd
75937593 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
75947594 NoItinerary>;
7595
7595
75967596 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
75977597 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
75987598 asmop # "\t$Rd.4h, $Rn.8b",
75997599 [(set (v4i16 VPR64:$Rd),
7600 (v4i16 (Neon_Padd
7600 (v4i16 (Neon_Padd
76017601 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
76027602 NoItinerary>;
7603
7603
76047604 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
76057605 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
76067606 asmop # "\t$Rd.4s, $Rn.8h",
76087608 (v4i32 (Neon_Padd
76097609 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
76107610 NoItinerary>;
7611
7611
76127612 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
76137613 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
76147614 asmop # "\t$Rd.2s, $Rn.4h",
76167616 (v2i32 (Neon_Padd
76177617 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
76187618 NoItinerary>;
7619
7619
76207620 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
76217621 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
76227622 asmop # "\t$Rd.2d, $Rn.4s",
76247624 (v2i64 (Neon_Padd
76257625 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
76267626 NoItinerary>;
7627
7627
76287628 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
76297629 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
76307630 asmop # "\t$Rd.1d, $Rn.2s",
76457645 (outs VPR128:$Rd), (ins VPR128:$Rn),
76467646 asmop # "\t$Rd.16b, $Rn.16b",
76477647 [], NoItinerary>;
7648
7648
76497649 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
76507650 (outs VPR128:$Rd), (ins VPR128:$Rn),
76517651 asmop # "\t$Rd.8h, $Rn.8h",
76527652 [], NoItinerary>;
7653
7653
76547654 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
76557655 (outs VPR128:$Rd), (ins VPR128:$Rn),
76567656 asmop # "\t$Rd.4s, $Rn.4s",
76577657 [], NoItinerary>;
7658
7658
76597659 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
76607660 (outs VPR128:$Rd), (ins VPR128:$Rn),
76617661 asmop # "\t$Rd.2d, $Rn.2d",
76627662 [], NoItinerary>;
7663
7663
76647664 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
76657665 (outs VPR64:$Rd), (ins VPR64:$Rn),
76667666 asmop # "\t$Rd.8b, $Rn.8b",
76677667 [], NoItinerary>;
7668
7668
76697669 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
76707670 (outs VPR64:$Rd), (ins VPR64:$Rn),
76717671 asmop # "\t$Rd.4h, $Rn.4h",
76727672 [], NoItinerary>;
7673
7673
76747674 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
76757675 (outs VPR64:$Rd), (ins VPR64:$Rn),
76767676 asmop # "\t$Rd.2s, $Rn.2s",
77107710 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
77117711 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
77127712
7713 def : Pat<(v16i8 (sub
7713 def : Pat<(v16i8 (sub
77147714 (v16i8 Neon_AllZero),
77157715 (v16i8 VPR128:$Rn))),
77167716 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7717 def : Pat<(v8i8 (sub
7717 def : Pat<(v8i8 (sub
77187718 (v8i8 Neon_AllZero),
77197719 (v8i8 VPR64:$Rn))),
77207720 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7721 def : Pat<(v8i16 (sub
7721 def : Pat<(v8i16 (sub
77227722 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
77237723 (v8i16 VPR128:$Rn))),
77247724 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7725 def : Pat<(v4i16 (sub
7725 def : Pat<(v4i16 (sub
77267726 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
77277727 (v4i16 VPR64:$Rn))),
77287728 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7729 def : Pat<(v4i32 (sub
7729 def : Pat<(v4i32 (sub
77307730 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
77317731 (v4i32 VPR128:$Rn))),
77327732 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7733 def : Pat<(v2i32 (sub
7733 def : Pat<(v2i32 (sub
77347734 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
77357735 (v2i32 VPR64:$Rn))),
77367736 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7737 def : Pat<(v2i64 (sub
7737 def : Pat<(v2i64 (sub
77387738 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
77397739 (v2i64 VPR128:$Rn))),
77407740 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
77457745 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
77467746 asmop # "\t$Rd.16b, $Rn.16b",
77477747 [], NoItinerary>;
7748
7748
77497749 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
77507750 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
77517751 asmop # "\t$Rd.8h, $Rn.8h",
77527752 [], NoItinerary>;
7753
7753
77547754 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
77557755 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
77567756 asmop # "\t$Rd.4s, $Rn.4s",
77577757 [], NoItinerary>;
7758
7758
77597759 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
77607760 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
77617761 asmop # "\t$Rd.2d, $Rn.2d",
77627762 [], NoItinerary>;
7763
7763
77647764 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
77657765 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
77667766 asmop # "\t$Rd.8b, $Rn.8b",
77677767 [], NoItinerary>;
7768
7768
77697769 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
77707770 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
77717771 asmop # "\t$Rd.4h, $Rn.4h",
77727772 [], NoItinerary>;
7773
7773
77747774 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
77757775 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
77767776 asmop # "\t$Rd.2s, $Rn.2s",
78237823 [(set (v16i8 VPR128:$Rd),
78247824 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
78257825 NoItinerary>;
7826
7826
78277827 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
78287828 (outs VPR128:$Rd), (ins VPR128:$Rn),
78297829 asmop # "\t$Rd.8h, $Rn.8h",
78307830 [(set (v8i16 VPR128:$Rd),
78317831 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
78327832 NoItinerary>;
7833
7833
78347834 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
78357835 (outs VPR128:$Rd), (ins VPR128:$Rn),
78367836 asmop # "\t$Rd.4s, $Rn.4s",
78377837 [(set (v4i32 VPR128:$Rd),
78387838 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
78397839 NoItinerary>;
7840
7840
78417841 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
78427842 (outs VPR64:$Rd), (ins VPR64:$Rn),
78437843 asmop # "\t$Rd.8b, $Rn.8b",
78447844 [(set (v8i8 VPR64:$Rd),
78457845 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
78467846 NoItinerary>;
7847
7847
78487848 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
78497849 (outs VPR64:$Rd), (ins VPR64:$Rn),
78507850 asmop # "\t$Rd.4h, $Rn.4h",
78517851 [(set (v4i16 VPR64:$Rd),
78527852 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
78537853 NoItinerary>;
7854
7854
78557855 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
78567856 (outs VPR64:$Rd), (ins VPR64:$Rn),
78577857 asmop # "\t$Rd.2s, $Rn.2s",
78697869 (outs VPR128:$Rd), (ins VPR128:$Rn),
78707870 asmop # "\t$Rd.16b, $Rn.16b",
78717871 [], NoItinerary>;
7872
7872
78737873 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
78747874 (outs VPR64:$Rd), (ins VPR64:$Rn),
78757875 asmop # "\t$Rd.8b, $Rn.8b",
78907890 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
78917891 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
78927892
7893 def : Pat<(v16i8 (xor
7893 def : Pat<(v16i8 (xor
78947894 (v16i8 VPR128:$Rn),
78957895 (v16i8 Neon_AllOne))),
78967896 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
7897 def : Pat<(v8i8 (xor
7897 def : Pat<(v8i8 (xor
78987898 (v8i8 VPR64:$Rn),
78997899 (v8i8 Neon_AllOne))),
79007900 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
7901 def : Pat<(v8i16 (xor
7901 def : Pat<(v8i16 (xor
79027902 (v8i16 VPR128:$Rn),
79037903 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
79047904 (NOT16b VPR128:$Rn)>;
7905 def : Pat<(v4i16 (xor
7905 def : Pat<(v4i16 (xor
79067906 (v4i16 VPR64:$Rn),
79077907 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
79087908 (NOT8b VPR64:$Rn)>;
7909 def : Pat<(v4i32 (xor
7909 def : Pat<(v4i32 (xor
79107910 (v4i32 VPR128:$Rn),
79117911 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
79127912 (NOT16b VPR128:$Rn)>;
7913 def : Pat<(v2i32 (xor
7913 def : Pat<(v2i32 (xor
79147914 (v2i32 VPR64:$Rn),
79157915 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
79167916 (NOT8b VPR64:$Rn)>;
7917 def : Pat<(v2i64 (xor
7917 def : Pat<(v2i64 (xor
79187918 (v2i64 VPR128:$Rn),
79197919 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
79207920 (NOT16b VPR128:$Rn)>;
79327932 [(set (v4f32 VPR128:$Rd),
79337933 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
79347934 NoItinerary>;
7935
7935
79367936 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
79377937 (outs VPR128:$Rd), (ins VPR128:$Rn),
79387938 asmop # "\t$Rd.2d, $Rn.2d",
79397939 [(set (v2f64 VPR128:$Rd),
79407940 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
79417941 NoItinerary>;
7942
7942
79437943 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
79447944 (outs VPR64:$Rd), (ins VPR64:$Rn),
79457945 asmop # "\t$Rd.2s, $Rn.2s",
79727972 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
79737973 asmop # "2\t$Rd.16b, $Rn.8h",
79747974 [], NoItinerary>;
7975
7975
79767976 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
79777977 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
79787978 asmop # "2\t$Rd.8h, $Rn.4s",
79797979 [], NoItinerary>;
7980
7980
79817981 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
79827982 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
79837983 asmop # "2\t$Rd.4s, $Rn.2d",
79907990 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
79917991 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
79927992
7993 multiclass NeonI_2VMisc_Narrow_Patterns
7993 multiclass NeonI_2VMisc_Narrow_Patterns
79947994 SDPatternOperator Neon_Op> {
79957995 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
79967996 (v8i8 (!cast(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
80008000
80018001 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
80028002 (v2i32 (!cast(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8003
8003
80048004 def : Pat<(v16i8 (concat_vectors
80058005 (v8i8 VPR64:$src),
80068006 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8007 (!cast(Prefix # 8h16b)
8007 (!cast(Prefix # 8h16b)
80088008 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
80098009 VPR128:$Rn)>;
80108010
80358035 (ins VPR64:$Rn, uimm_exact8:$Imm),
80368036 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
80378037 [], NoItinerary>;
8038
8038
80398039 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
80408040 (outs VPR128:$Rd),
80418041 (ins VPR64:$Rn, uimm_exact16:$Imm),
80428042 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
80438043 [], NoItinerary>;
8044
8044
80458045 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
80468046 (outs VPR128:$Rd),
80478047 (ins VPR64:$Rn, uimm_exact32:$Imm),
80488048 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
80498049 [], NoItinerary>;
8050
8050
80518051 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
80528052 (outs VPR128:$Rd),
80538053 (ins VPR128:$Rn, uimm_exact8:$Imm),
80548054 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
80558055 [], NoItinerary>;
8056
8056
80578057 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
80588058 (outs VPR128:$Rd),
80598059 (ins VPR128:$Rn, uimm_exact16:$Imm),
80608060 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
80618061 [], NoItinerary>;
8062
8062
80638063 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
80648064 (outs VPR128:$Rd),
80658065 (ins VPR128:$Rn, uimm_exact32:$Imm),
80728072
80738073 class NeonI_SHLL_Patterns
80748074 SDPatternOperator ExtOp, Operand Neon_Imm,
8075 string suffix>
8075 string suffix>
80768076 : Pat<(DesTy (shl
80778077 (DesTy (ExtOp (OpTy VPR64:$Rn))),
80788078 (DesTy (Neon_vdup
80798079 (i32 Neon_Imm:$Imm))))),
80808080 (!cast("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8081
8081
80828082 class NeonI_SHLL_High_Patterns
80838083 SDPatternOperator ExtOp, Operand Neon_Imm,
8084 string suffix, PatFrag GetHigh>
8084 string suffix, PatFrag GetHigh>
80858085 : Pat<(DesTy (shl
80868086 (DesTy (ExtOp
80878087 (OpTy (GetHigh VPR128:$Rn)))),
81188118 (outs VPR64:$Rd), (ins VPR128:$Rn),
81198119 asmop # "\t$Rd.2s, $Rn.2d",
81208120 [], NoItinerary>;
8121
8121
81228122 let Constraints = "$src = $Rd" in {
81238123 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
81248124 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
81258125 asmop # "2\t$Rd.8h, $Rn.4s",
81268126 [], NoItinerary>;
8127
8127
81288128 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
81298129 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
81308130 asmop # "2\t$Rd.4s, $Rn.2d",
81378137 multiclass NeonI_2VMisc_Narrow_Pattern
81388138 SDPatternOperator f32_to_f16_Op,
81398139 SDPatternOperator f64_to_f32_Op> {
8140
8140
81418141 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
81428142 (!cast(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8143
8143
81448144 def : Pat<(v8i16 (concat_vectors
81458145 (v4i16 VPR64:$src),
81468146 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
81478147 (!cast(prefix # "4s8h")
81488148 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8149 (v4f32 VPR128:$Rn))>;
8150
8149 (v4f32 VPR128:$Rn))>;
8150
81518151 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
81528152 (!cast(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8153
8153
81548154 def : Pat<(v4f32 (concat_vectors
81558155 (v2f32 VPR64:$src),
81568156 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
81748174 [], NoItinerary> {
81758175 let Constraints = "$src = $Rd";
81768176 }
8177
8177
81788178 def : Pat<(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))),
81798179 (!cast(prefix # "2d2s") VPR128:$Rn)>;
81808180
82188218 multiclass NeonI_2VMisc_Extend_Pattern {
82198219 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
82208220 (!cast(prefix # "4h4s") VPR64:$Rn)>;
8221
8221
82228222 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
82238223 (v4i16 (Neon_High8H
82248224 (v8i16 VPR128:$Rn))))),
82258225 (!cast(prefix # "8h4s") VPR128:$Rn)>;
8226
8226
82278227 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
82288228 (!cast(prefix # "2s2d") VPR64:$Rn)>;
8229
8229
82308230 def : Pat<(v2f64 (fextend
82318231 (v2f32 (Neon_High4Float
82328232 (v4f32 VPR128:$Rn))))),
82408240 ValueType ResTy2d, ValueType OpTy2d,
82418241 ValueType ResTy2s, ValueType OpTy2s,
82428242 SDPatternOperator Neon_Op> {
8243
8243
82448244 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
82458245 (outs VPR128:$Rd), (ins VPR128:$Rn),
82468246 asmop # "\t$Rd.4s, $Rn.4s",
82548254 [(set (ResTy2d VPR128:$Rd),
82558255 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
82568256 NoItinerary>;
8257
8257
82588258 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
82598259 (outs VPR64:$Rd), (ins VPR64:$Rn),
82608260 asmop # "\t$Rd.2s, $Rn.2s",
83268326 [(set (v4i32 VPR128:$Rd),
83278327 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
83288328 NoItinerary>;
8329
8329
83308330 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
83318331 (outs VPR64:$Rd), (ins VPR64:$Rn),
83328332 asmop # "\t$Rd.2s, $Rn.2s",
84588458 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
84598459 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
84608460 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8461