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[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions Differential Revision: http://reviews.llvm.org/D16625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273850 91177308-0d34-0410-b5e6-96231b3b80d8 Hrvoje Varga 3 years ago
26 changed file(s) with 237 addition(s) and 77 deletion(s). Raw diff Collapse all Expand all
8080 case Mips::DSLL_MM64R6:
8181 Inst.setOpcode(Mips::DSLL32_MM64R6);
8282 return;
83 case Mips::DSRL_MM64R6:
84 Inst.setOpcode(Mips::DSRL32_MM64R6);
85 return;
8386 case Mips::DSRA_MM64R6:
8487 Inst.setOpcode(Mips::DSRA32_MM64R6);
8588 return;
194197 case Mips::DSRA:
195198 case Mips::DROTR:
196199 case Mips::DSLL_MM64R6:
200 case Mips::DSRL_MM64R6:
197201 case Mips::DSRA_MM64R6:
198202 case Mips::DROTR_MM64R6:
199203 LowerLargeShift(TmpInst);
172172 let Inst{8-0} = funct;
173173 }
174174
175 class LD_SD_32_2R_OFFSET16_FM_MMR6 op>
176 : MMR6Arch, MipsR6Inst {
177 bits<5> rt;
178 bits<21> addr;
179 bits<5> base = addr{20-16};
180 bits<16> offset = addr{15-0};
181
182 bits<32> Inst;
183
184 let Inst{31-26} = op;
185 let Inst{25-21} = rt;
186 let Inst{20-16} = base;
187 let Inst{15-0} = offset;
188 }
189
190 class POOL32C_2R_OFFSET12_FM_MMR6 funct>
191 : MMR6Arch, MipsR6Inst {
192 bits<5> rt;
193 bits<21> addr;
194 bits<5> base = addr{20-16};
195 bits<12> offset = addr{11-0};
196
197 bits<32> Inst;
198
199 let Inst{31-26} = 0b011000;
200 let Inst{25-21} = rt;
201 let Inst{20-16} = base;
202 let Inst{15-12} = funct;
203 let Inst{11-0} = offset;
204 }
205
175206 class POOL32S_3R_FM_MMR6 funct>
176207 : MMR6Arch, MipsR6Inst {
177208 bits<5> rt;
184215 let Inst{25-21} = rt;
185216 let Inst{20-16} = rs;
186217 let Inst{15-11} = rd;
187 let Inst{10-9} = 0b00;
188 let Inst{8-0} = funct;
189 }
218 let Inst{10-9} = 0b00;
219 let Inst{8-0} = funct;
220 }
5959 class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>;
6060 class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
6161 class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
62 class LD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"ld", 0b110111>;
63 class LLD_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lld", 0b0111>;
64 class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
65 class SD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"sd", 0b110110>;
66 class DSRL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl", 0b001000000>;
67 class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>;
68 class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
6269
6370 //===----------------------------------------------------------------------===//
6471 //
220227 dag OutOperandList = (outs GPR64Opnd:$rt);
221228 dag InOperandList = (ins GPR64Opnd:$rs, ImmOpnd:$sa);
222229 string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
230 list Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
223231 InstrItinClass Itinerary = itin;
224 list Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
232 Format Form = FrmR;
225233 string TwoOperandAliasConstraint = "$rs = $rt";
226234 string BaseOpcode = instr_asm;
227235 }
251259 class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
252260 II_DROTR32>;
253261 class DROTRV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"drotrv", II_DROTRV, rotr>;
262 class DSRL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl", uimm6, II_DSRL, srl,
263 immZExt6>;
264 class DSRL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl32", uimm5, II_DSRL32>;
265 class DSRLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrlv", II_DSRLV, srl>;
266
267 class Load_MM64R6
268 SDPatternOperator OpNode = null_frag> {
269 dag OutOperandList = (outs GPR64Opnd:$rt);
270 dag InOperandList = (ins MemOpnd:$addr);
271 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
272 list Pattern = [(set GPR64Opnd:$rt, (OpNode addr:$addr))];
273 InstrItinClass Itinerary = itin;
274 Format Form = FrmI;
275 bit mayLoad = 1;
276 bit canFoldAsLoad = 1;
277 string BaseOpcode = instr_asm;
278 }
279
280 class LD_MM64R6_DESC : Load_MM64R6<"ld", mem_simm16, II_LD, load> {
281 string DecoderMethod = "DecodeMemMMImm16";
282 }
283 class LWU_MM64R6_DESC : Load_MM64R6<"lwu", mem_simm12, II_LWU, zextloadi32>{
284 string DecoderMethod = "DecodeMemMMImm12";
285 }
286
287 class LLD_MM64R6_DESC {
288 dag OutOperandList = (outs GPR64Opnd:$rt);
289 dag InOperandList = (ins mem_simm12:$addr);
290 string AsmString = "lld\t$rt, $addr";
291 list Pattern = [];
292 bit mayLoad = 1;
293 InstrItinClass Itinerary = II_LLD;
294 string BaseOpcode = "lld";
295 string DecoderMethod = "DecodeMemMMImm12";
296 }
297
298 class SD_MM64R6_DESC {
299 dag OutOperandList = (outs);
300 dag InOperandList = (ins GPR64Opnd:$rt, mem_simm16:$addr);
301 string AsmString = "sd\t$rt, $addr";
302 list Pattern = [(store GPR64Opnd:$rt, addr:$addr)];
303 InstrItinClass Itinerary = II_SD;
304 Format Form = FrmI;
305 bit mayStore = 1;
306 string BaseOpcode = "sd";
307 string DecoderMethod = "DecodeMemMMImm16";
308 }
254309
255310 //===----------------------------------------------------------------------===//
256311 //
342397 ISA_MICROMIPS64R6;
343398 def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_ENC, DROTRV_MM64R6_DESC,
344399 ISA_MICROMIPS64R6;
400 def LD_MM64R6 : StdMMR6Rel, LD_MM64R6_ENC, LD_MM64R6_DESC,
401 ISA_MICROMIPS64R6;
402 def LLD_MM64R6 : StdMMR6Rel, R6MMR6Rel, LLD_MM64R6_ENC, LLD_MM64R6_DESC,
403 ISA_MICROMIPS64R6;
404 def LWU_MM64R6 : StdMMR6Rel, LWU_MM64R6_ENC, LWU_MM64R6_DESC,
405 ISA_MICROMIPS64R6;
406 def SD_MM64R6 : StdMMR6Rel, SD_MM64R6_ENC, SD_MM64R6_DESC,
407 ISA_MICROMIPS64R6;
408 def DSRL_MM64R6 : StdMMR6Rel, DSRL_MM64R6_ENC, DSRL_MM64R6_DESC,
409 ISA_MICROMIPS64R6;
410 def DSRL32_MM64R6 : StdMMR6Rel, DSRL32_MM64R6_ENC, DSRL32_MM64R6_DESC,
411 ISA_MICROMIPS64R6;
412 def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC,
413 ISA_MICROMIPS64R6;
345414 }
346415
347416 //===----------------------------------------------------------------------===//
395464 // Carry pattern
396465 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
397466 (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
467
468 def : MipsPat<(atomic_load_64 addr:$a), (LD_MM64R6 addr:$a)>, ISA_MICROMIPS64R6;
398469
399470 //===----------------------------------------------------------------------===//
400471 //
674674 let Inst{15-0} = imm16;
675675 }
676676
677 class LL_FM_MM funct> {
677 class LL_FM_MM funct> : MMArch {
678678 bits<5> rt;
679679 bits<21> addr;
680680
0 def addrimm12 : ComplexPattern;
11 def addrimm4lsl2 : ComplexPattern;
2
3 def simm12 : Operand {
4 let DecoderMethod = "DecodeSimm12";
5 }
62
73 def simm9_addiusp : Operand {
84 let EncoderMethod = "getSImm9AddiuspValue";
139135 let EncoderMethod = "getMemEncodingMMImm4sp";
140136 let ParserMatchClass = MipsMemUimm4AsmOperand;
141137 let OperandType = "OPERAND_MEMORY";
142 }
143
144 def MipsMemSimm12AsmOperand : AsmOperandClass {
145 let Name = "MemOffsetSimm12";
146 let SuperClasses = [MipsMemAsmOperand];
147 let RenderMethod = "addMemOperands";
148 let ParserMethod = "parseMemOperand";
149 let PredicateMethod = "isMemWithSimmOffset<12>";
150 let DiagnosticType = "MemSImm12";
151 }
152
153 def mem_simm12 : mem_generic {
154 let MIOperandInfo = (ops ptr_rc, simm12);
155 let EncoderMethod = "getMemEncoding";
156 let ParserMatchClass = MipsMemSimm12AsmOperand;
157138 }
158139
159140 def jmptarget_mm : Operand {
303284 }
304285
305286 class LoadMM
306 InstrItinClass Itin = NoItinerary> :
307 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
287 InstrItinClass Itin = NoItinerary, DAGOperand MO = mem_mm_12> :
288 InstSE<(outs RO:$rt), (ins MO:$addr),
308289 !strconcat(opstr, "\t$rt, $addr"),
309 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> {
290 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
310291 let DecoderMethod = "DecodeMemMMImm12";
311292 let canFoldAsLoad = 1;
312293 let mayLoad = 1;
789770
790771 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>;
791772
792 def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>;
793
794773 /// Load and Store Instructions - unaligned
795774 def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
796775 LWL_FM_MM<0x0>;
982961 let DecoderNamespace = "MicroMips" in {
983962 def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware,
984963 RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
964 def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
965 mem_simm12>, LL_FM_MM<0xe>,
966 ISA_MICROMIPS32_NOT_MIPS32R6;
985967 }
986968
987969 //===----------------------------------------------------------------------===//
676676 class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
677677
678678 class LL_R6_DESC_BASE
679 InstrItinClass itin> {
679 Operand MemOpnd, InstrItinClass itin>
680 : MipsR6Arch {
680681 dag OutOperandList = (outs GPROpnd:$rt);
681 dag InOperandList = (ins mem_simm9:$addr);
682 dag InOperandList = (ins MemOpnd:$addr);
682683 string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
683684 list Pattern = [];
684685 bit mayLoad = 1;
685686 InstrItinClass Itinerary = itin;
686687 }
687688
688 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, II_LL>;
689 class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
689690
690691 class SC_R6_DESC_BASE
691692 InstrItinClass itin> {
139139 def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL,
140140 shl, immZExt6>,
141141 SRA_FM<0x38, 0>, ISA_MIPS3;
142 }
143 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
142 def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL,
143 srl, immZExt6>,
144144 SRA_FM<0x3a, 0>, ISA_MIPS3;
145 let AdditionalPredicates = [NotInMicroMips] in {
146145 def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA,
147146 sra, immZExt6>,
148147 SRA_FM<0x3b, 0>, ISA_MIPS3;
149148 def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
150149 SRLV_FM<0x14, 0>, ISA_MIPS3;
151 }
152 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
153 SRLV_FM<0x16, 0>, ISA_MIPS3;
154 let AdditionalPredicates = [NotInMicroMips] in {
155150 def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
156151 SRLV_FM<0x17, 0>, ISA_MIPS3;
157 }
158 let AdditionalPredicates = [NotInMicroMips] in {
152 def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
153 SRLV_FM<0x16, 0>, ISA_MIPS3;
159154 def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd,
160155 II_DSLL32>,
161156 SRA_FM<0x3c, 0>, ISA_MIPS3;
162 }
163 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
164 SRA_FM<0x3e, 0>, ISA_MIPS3;
165 let AdditionalPredicates = [NotInMicroMips] in {
157 def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd,
158 II_DSRL32>,
159 SRA_FM<0x3e, 0>, ISA_MIPS3;
166160 def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd,
167161 II_DSRA32>,
168162 SRA_FM<0x3f, 0>, ISA_MIPS3;
192186 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
193187 }
194188
195 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
196 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
197 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
189 let AdditionalPredicates = [NotInMicroMips] in {
190 def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
191 LW_FM<0x27>, ISA_MIPS3;
192 def LD : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>,
193 LW_FM<0x37>, ISA_MIPS3;
194 def SD : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>,
195 LW_FM<0x3f>, ISA_MIPS3;
196 }
197
198
198199
199200 /// load/store left/right
200201 let isCodeGenOnly = 1 in {
214215 ISA_MIPS3_NOT_32R6_64R6;
215216
216217 /// Load-linked, Store-conditional
217 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
218 let AdditionalPredicates = [NotInMicroMips] in {
219 def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>,
220 ISA_MIPS3_NOT_32R6_64R6;
221 }
218222 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
219223
220224 let AdditionalPredicates = [NotInMicroMips],
686690 def : MipsInstAlias<"dsra $rd, $rt, $rs",
687691 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
688692 ISA_MIPS3;
689 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
690 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
691 ISA_MIPS3;
693 let AdditionalPredicates = [NotInMicroMips] in {
694 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
695 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
696 ISA_MIPS3;
692697
693698 // Two operand (implicit 0 selector) versions:
694 let AdditionalPredicates = [NotInMicroMips] in {
695699 def : MipsInstAlias<"dmtc0 $rt, $rd",
696700 (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
697701 def : MipsInstAlias<"dmfc0 $rt, $rd",
7070 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
7171 class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
7272 class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
73 class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, II_LLD>;
73 class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm16, II_LLD>;
7474 class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
7575 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
7676 class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
8787 list Defs = [AT];
8888 }
8989
90 class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, II_LL>;
90 class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
9191 class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
9292 //===----------------------------------------------------------------------===//
9393 //
116116 def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6;
117117 def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6;
118118 def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6;
119 def LLD_R6 : R6MMR6Rel, LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
119120 }
120121 def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
121 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS32R6;
122122 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
123123 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
124124 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
879879 let DiagnosticType = "MemSImm10";
880880 }
881881
882 def MipsMemSimm12AsmOperand : AsmOperandClass {
883 let Name = "MemOffsetSimm12";
884 let SuperClasses = [MipsMemAsmOperand];
885 let RenderMethod = "addMemOperands";
886 let ParserMethod = "parseMemOperand";
887 let PredicateMethod = "isMemWithSimmOffset<12>";
888 let DiagnosticType = "MemSImm12";
889 }
890
882891 foreach I = {1, 2, 3} in
883892 def MipsMemSimm10Lsl # I # AsmOperand : AsmOperandClass {
884893 let Name = "MemOffsetSimm10_" # I;
938947 let EncoderMethod = "getMSAMemEncoding";
939948 }
940949
950 def simm12 : Operand {
951 let DecoderMethod = "DecodeSimm12";
952 }
953
941954 def mem_simm9 : mem_generic {
942955 let MIOperandInfo = (ops ptr_rc, simm9);
943956 let EncoderMethod = "getMemEncoding";
962975 let MIOperandInfo = (ops ptr_rc, simm11);
963976 let EncoderMethod = "getMemEncoding";
964977 let ParserMatchClass = MipsMemSimm11AsmOperand;
978 }
979
980 def mem_simm12 : mem_generic {
981 let MIOperandInfo = (ops ptr_rc, simm12);
982 let EncoderMethod = "getMemEncoding";
983 let ParserMatchClass = MipsMemSimm12AsmOperand;
965984 }
966985
967986 def mem_simm16 : mem_generic {
11661185 }
11671186
11681187 class Store
1169 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
1170 StoreMemory;
1188 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr,
1189 DAGOperand MO = mem> :
1190 StoreMemory;
11711191
11721192 // Load/Store Left/Right
11731193 let canFoldAsLoad = 1 in
15391559 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
15401560 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
15411561
1542 class LLBase :
1543 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1544 [], II_LL, FrmI> {
1562 class LLBase :
1563 InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
1564 [], II_LL, FrmI, opstr> {
15451565 let DecoderMethod = "DecodeMem";
15461566 let mayLoad = 1;
15471567 }
0 ; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
11 ; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
2 ; RUN: llc %s -march=mips64 -mcpu=mips64r3 -mattr=micromips -filetype=asm \
2 ; RUN: llc %s -march=mips64 -mcpu=mips64r6 -mattr=micromips -filetype=asm \
33 ; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
44
55 ; The purpose of this test is to check whether the CodeGen selects
288288 0x58 0xaa 0x40 0xc0 # CHECK: drotr $5, $10, 8
289289 0x58 0x22 0x20 0xc8 # CHECK: drotr32 $1, $2, 4
290290 0x58 0xc4 0x18 0xd0 # CHECK: drotrv $3, $6, $4
291 0xdc 0x82 0x00 0x05 # CHECK: ld $4, 5($2)
292 0x60 0x48 0x70 0x03 # CHECK: lld $2, 3($8)
293 0x60 0x22 0xe0 0x0a # CHECK: lwu $1, 10($2)
294 0xd8 0x83 0x00 0x05 # CHECK: sd $4, 5($3)
295 0x58 0x22 0x10 0x40 # CHECK: dsrl $1, $2, 2
296 0x58 0x64 0x28 0x48 # CHECK: dsrl32 $3, $4, 5
297 0x58 0x63 0x08 0x50 # CHECK: dsrlv $1, $3, $3
8787 jraddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
8888 jraddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
8989 jraddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
90 lwu $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
22 # RUN: FileCheck %s < %t1
33
44
5 # The LLD instruction with invalid memory operand should emit "expected memory with 12-bit signed offset".
6 lld $31, 4096($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
7 lld $31, 2048($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
8 lld $31, -2049($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
9 # The LWU instruction with invalid memory operand should emit "expected memory with 12-bit signed offset".
10 lwu $31, 4096($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
11 lwu $31, 2048($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
12 lwu $31, -2049($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
513 # The 10-bit immediate supported by the standard encodings cause us to emit
614 # the diagnostic for the 10-bit form. This isn't exactly wrong but it is
715 # misleading. Ideally, we'd emit every way to achieve a valid match instead
290290 drotr $5, $10, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
291291 drotr32 $1, $2, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
292292 drotr32 $1, $2, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
293 ld $31, 65536($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
294 ld $31, 32768($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
295 ld $31, -32769($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
296 sd $31, 65536($31) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
297 sd $31, 32768($31) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
298 sd $31, -32769($31) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
299299 drotr $5, $10, 8 # CHECK: drotr $5, $10, 8 # encoding: [0x58,0xaa,0x40,0xc0]
300300 drotr32 $1, $2, 4 # CHECK: drotr32 $1, $2, 4 # encoding: [0x58,0x22,0x20,0xc8]
301301 drotrv $3, $6, $4 # CHECK: drotrv $3, $6, $4 # encoding: [0x58,0xc4,0x18,0xd0]
302 ld $4, 5($2) # CHECK: ld $4, 5($2) # encoding: [0xdc,0x82,0x00,0x05]
303 lld $2, 3($8) # CHECK: lld $2, 3($8) # encoding: [0x60,0x48,0x70,0x03]
304 lwu $1, 10($2) # CHECK: lwu $1, 10($2) # encoding: [0x60,0x22,0xe0,0x0a]
305 sd $4, 5($3) # CHECK: sd $4, 5($3) # encoding: [0xd8,0x83,0x00,0x05]
306 dsrl $1, $2, 2 # CHECK: dsrl $1, $2, 2 # encoding: [0x58,0x22,0x10,0x40]
307 dsrl32 $3, $4, 5 # CHECK: dsrl32 $3, $4, 5 # encoding: [0x58,0x64,0x28,0x48]
308 dsrlv $1, $3, $3 # CHECK: dsrlv $1, $3, $3 # encoding: [0x58,0x63,0x08,0x50]
302309
303310 1:
55 # RUN: FileCheck %s < %t1
66
77 .set noat
8 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
98 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
109 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1110 ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1211 ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1312 ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1413 ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
15 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
16 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1714 sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
1815 scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
19 sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2016 sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2117 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
2218 sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
5353 floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5454 floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5555 floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
56 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
57 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
58 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
5659 round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5760 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5861 round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5962 round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 sd $12,5835($10) # CHECK: :[[@LINE]]:23: error: expected memory with 16-bit signed offset
6064 sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6165 sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6266 teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
77 .set noat
88 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
99 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1110 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1211 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1312 ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
1413 ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1514 ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1615 ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
17 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
18 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1916 sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
2017 scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
21 sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2218 sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
2319 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
2420 sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
6868 movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6969 movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7070 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
71 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
72 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
73 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
7174 round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7275 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7376 round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7477 round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
78 sd $12,5835($10) # CHECK: :[[@LINE]]:23: error: expected memory with 16-bit signed offset
7579 sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7680 sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7781 sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
66
77 .set noat
88 dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
109 ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1110 ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
13 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1411 scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
15 sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1612 sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1713 sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
4949 eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5050 floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5151 floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
52 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
53 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
54 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed offset
5255 round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5356 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
57 sd $t0,5835($a6) # CHECK: :[[@LINE]]:24: error: expected memory with 16-bit signed offset
5458 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5559 trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
77 .set noat
88 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
99 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1210 scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
13 sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1411 sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1512 sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
4747 floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
4848 ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
4949 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
50 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
5051 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
5152 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
5253 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6465 movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6566 movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6667 movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
68 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
6769 round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
6870 round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
71 sd $12,5835($10) # CHECK: :[[@LINE]]:23: error: expected memory with 16-bit signed offset
6972 sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7073 trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
7174 trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
1313 jalr.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
1414 pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
1515 pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
16 sd $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
1717 dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
1818 dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
1919 dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
20 sd $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
7676 dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
7777 dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
7878 dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:24: error: expected 3-bit unsigned immediate
79 ld $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
80 ld $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
81 ld $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
82 lld $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
83 lld $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
84 sd $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
85 lld $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
86 sd $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
87 sd $32, 65536($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
88 dsrl $2, $4, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
89 dsrl $2, $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
90 dsrl $32, $32, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
91 dsrl32 $2, $4, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
92 dsrl32 $32, $32, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
93 dsrlv $2, $4, 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
94 dsrlv $32, $32, $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction