llvm.org GIT mirror llvm / b216a1b
More stuff for CellSPU -- this should be enough to get an error-free compilation (no files missing). Test cases remain to be checked in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44598 91177308-0d34-0410-b5e6-96231b3b80d8 Scott Michel 11 years ago
4 changed file(s) with 243 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
362362 [Build specific host targets: all,host-only,{target-name} (default=all)]),,
363363 enableval=all)
364364 case "$enableval" in
365 # Note: Add "CellSPU" to all when fully functional.
365366 all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha IA64 ARM Mips" ;;
366367 host-only)
367368 case "$llvm_cv_target_arch" in
373374 IA64) TARGETS_TO_BUILD="IA64" ;;
374375 ARM) TARGETS_TO_BUILD="ARM" ;;
375376 Mips) TARGETS_TO_BUILD="Mips" ;;
377 CellSPU|SPU) TARGETS_TO_BUILD="CellSPU" ;;
376378 *) AC_MSG_ERROR([Can not set target to build]) ;;
377379 esac
378380 ;;
386388 ia64) TARGETS_TO_BUILD="IA64 $TARGETS_TO_BUILD" ;;
387389 arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
388390 mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
391 spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
389392 *) AC_MSG_ERROR([Unrecognized target $a_target]) ;;
390393 esac
391394 done
273273 include "llvm/IntrinsicsPowerPC.td"
274274 include "llvm/IntrinsicsX86.td"
275275 include "llvm/IntrinsicsARM.td"
276 include "llvm/IntrinsicsCellSPU.td"
0 //==- IntrinsicsCellSPU.td - Cell SDK intrinsics -*- tablegen -*-==//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by The Aerospace Corporation.
5 //
6 //===----------------------------------------------------------------------===//
7 // Cell SPU Instructions:
8 //===----------------------------------------------------------------------===//
9 // TODO Items (not urgent today, but would be nice, low priority)
10 //
11 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
12 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
13 // in 16-bit and 32-bit constants and reduce instruction count.
14 //===----------------------------------------------------------------------===//
15
16 // 7-bit integer type, used as an immediate:
17 def cell_i7_ty: LLVMType; // Note: This was i8
18 def cell_i8_ty: LLVMType; // Note: This was i8
19
20 class v16i8_u7imm :
21 GCCBuiltin,
22 Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, cell_i7_ty],
23 [IntrNoMem]>;
24
25 class v16i8_u8imm :
26 GCCBuiltin,
27 Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
28 [IntrNoMem]>;
29
30 class v16i8_s10imm :
31 GCCBuiltin,
32 Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
33 [IntrNoMem]>;
34
35 class v16i8_u16imm :
36 GCCBuiltin,
37 Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i16_ty],
38 [IntrNoMem]>;
39
40 class v16i8_rr :
41 GCCBuiltin,
42 Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
43 [IntrNoMem]>;
44
45 class v8i16_s10imm :
46 GCCBuiltin,
47 Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i16_ty],
48 [IntrNoMem]>;
49
50 class v8i16_u16imm :
51 GCCBuiltin,
52 Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_i16_ty],
53 [IntrNoMem]>;
54
55 class v8i16_rr :
56 GCCBuiltin,
57 Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
58 [IntrNoMem]>;
59
60 class v4i32_rr :
61 GCCBuiltin,
62 Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
63 [IntrNoMem]>;
64
65 class v4i32_u7imm :
66 GCCBuiltin,
67 Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, cell_i7_ty],
68 [IntrNoMem]>;
69
70 class v4i32_s10imm :
71 GCCBuiltin,
72 Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_i16_ty],
73 [IntrNoMem]>;
74
75 class v4i32_u16imm :
76 GCCBuiltin,
77 Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_i16_ty],
78 [IntrNoMem]>;
79
80 class v4f32_rr :
81 GCCBuiltin,
82 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
83 [IntrNoMem]>;
84
85 class v4f32_rrr :
86 GCCBuiltin,
87 Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
88 [IntrNoMem]>;
89
90 class v2f64_rr :
91 GCCBuiltin,
92 Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
93 [IntrNoMem]>;
94
95 // All Cell SPU intrinsics start with "llvm.spu.".
96 let TargetPrefix = "spu" in {
97 def int_spu_si_fsmbi : v8i16_u16imm<"fsmbi">;
98 def int_spu_si_ah : v8i16_rr<"ah">;
99 def int_spu_si_ahi : v8i16_s10imm<"ahi">;
100 def int_spu_si_a : v4i32_rr<"a">;
101 def int_spu_si_ai : v4i32_s10imm<"ai">;
102 def int_spu_si_sfh : v8i16_rr<"sfh">;
103 def int_spu_si_sfhi : v8i16_s10imm<"sfhi">;
104 def int_spu_si_sf : v4i32_rr<"sf">;
105 def int_spu_si_sfi : v4i32_s10imm<"sfi">;
106 def int_spu_si_addx : v4i32_rr<"addx">;
107 def int_spu_si_cg : v4i32_rr<"cg">;
108 def int_spu_si_cgx : v4i32_rr<"cgx">;
109 def int_spu_si_sfx : v4i32_rr<"sfx">;
110 def int_spu_si_bg : v4i32_rr<"bg">;
111 def int_spu_si_bgx : v4i32_rr<"bgx">;
112 def int_spu_si_mpy : // This is special:
113 GCCBuiltin<"__builtin_si_mpy">,
114 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
115 [IntrNoMem]>;
116 def int_spu_si_mpyu : // This is special:
117 GCCBuiltin<"__builtin_si_mpyu">,
118 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
119 [IntrNoMem]>;
120 def int_spu_si_mpyi : // This is special:
121 GCCBuiltin<"__builtin_si_mpyi">,
122 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_i16_ty],
123 [IntrNoMem]>;
124 def int_spu_si_mpyui : // This is special:
125 GCCBuiltin<"__builtin_si_mpyui">,
126 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_i16_ty],
127 [IntrNoMem]>;
128 def int_spu_si_mpya : // This is special:
129 GCCBuiltin<"__builtin_si_mpya">,
130 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
131 [IntrNoMem]>;
132 def int_spu_si_mpyh : // This is special:
133 GCCBuiltin<"__builtin_si_mpyh">,
134 Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v8i16_ty],
135 [IntrNoMem]>;
136 def int_spu_si_mpys : // This is special:
137 GCCBuiltin<"__builtin_si_mpys">,
138 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
139 [IntrNoMem]>;
140 def int_spu_si_mpyhh : // This is special:
141 GCCBuiltin<"__builtin_si_mpyhh">,
142 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
143 [IntrNoMem]>;
144 def int_spu_si_mpyhha : // This is special:
145 GCCBuiltin<"__builtin_si_mpyhha">,
146 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
147 [IntrNoMem]>;
148 def int_spu_si_mpyhhu : // This is special:
149 GCCBuiltin<"__builtin_si_mpyhhu">,
150 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
151 [IntrNoMem]>;
152 def int_spu_si_mpyhhau : // This is special:
153 GCCBuiltin<"__builtin_si_mpyhhau">,
154 Intrinsic<[llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
155 [IntrNoMem]>;
156
157 def int_spu_si_shli: v4i32_u7imm<"shli">;
158 def int_spu_si_shlqbi: v16i8_rr<"shlqbi">;
159 def int_spu_si_shlqbii: v16i8_u7imm<"shlqbii">;
160 def int_spu_si_shlqby: v16i8_rr<"shlqby">;
161 def int_spu_si_shlqbyi: v16i8_u7imm<"shlqbyi">;
162
163 def int_spu_si_ceq: v4i32_rr<"ceq">;
164 def int_spu_si_ceqi: v4i32_s10imm<"ceqi">;
165 def int_spu_si_ceqb: v16i8_rr<"ceqb">;
166 def int_spu_si_ceqbi: v16i8_u8imm<"ceqbi">;
167 def int_spu_si_ceqh: v8i16_rr<"ceqh">;
168 def int_spu_si_ceqhi: v8i16_s10imm<"ceqhi">;
169 def int_spu_si_cgt: v4i32_rr<"cgt">;
170 def int_spu_si_cgti: v4i32_s10imm<"cgti">;
171 def int_spu_si_cgtb: v16i8_rr<"cgtb">;
172 def int_spu_si_cgtbi: v16i8_u8imm<"cgtbi">;
173 def int_spu_si_cgth: v8i16_rr<"cgth">;
174 def int_spu_si_cgthi: v8i16_s10imm<"cgthi">;
175 def int_spu_si_clgtb: v16i8_rr<"clgtb">;
176 def int_spu_si_clgtbi: v16i8_u8imm<"clgtbi">;
177 def int_spu_si_clgth: v8i16_rr<"clgth">;
178 def int_spu_si_clgthi: v8i16_s10imm<"clgthi">;
179 def int_spu_si_clgt: v4i32_rr<"clgt">;
180 def int_spu_si_clgti: v4i32_s10imm<"clgti">;
181
182 def int_spu_si_and: v4i32_rr<"and">;
183 def int_spu_si_andbi: v16i8_u8imm<"andbi">;
184 def int_spu_si_andc: v4i32_rr<"andc">;
185 def int_spu_si_andhi: v8i16_s10imm<"andhi">;
186 def int_spu_si_andi: v4i32_s10imm<"andi">;
187
188 def int_spu_si_or: v4i32_rr<"or">;
189 def int_spu_si_orbi: v16i8_u8imm<"orbi">;
190 def int_spu_si_orc: v4i32_rr<"orc">;
191 def int_spu_si_orhi: v8i16_s10imm<"orhi">;
192 def int_spu_si_ori: v4i32_s10imm<"ori">;
193
194 def int_spu_si_xor: v4i32_rr<"xor">;
195 def int_spu_si_xorbi: v16i8_u8imm<"xorbi">;
196 def int_spu_si_xorhi: v8i16_s10imm<"xorhi">;
197 def int_spu_si_xori: v4i32_s10imm<"xori">;
198
199 def int_spu_si_nor: v4i32_rr<"nor">;
200 def int_spu_si_nand: v4i32_rr<"nand">;
201
202 def int_spu_si_fa: v4f32_rr<"fa">;
203 def int_spu_si_fs: v4f32_rr<"fs">;
204 def int_spu_si_fm: v4f32_rr<"fm">;
205
206 def int_spu_si_fceq: v4f32_rr<"fceq">;
207 def int_spu_si_fcmeq: v4f32_rr<"fcmeq">;
208 def int_spu_si_fcgt: v4f32_rr<"fcgt">;
209 def int_spu_si_fcmgt: v4f32_rr<"fcmgt">;
210
211 def int_spu_si_fma: v4f32_rrr<"fma">;
212 def int_spu_si_fnms: v4f32_rrr<"fnms">;
213 def int_spu_si_fms: v4f32_rrr<"fms">;
214
215 def int_spu_si_dfa: v2f64_rr<"dfa">;
216 def int_spu_si_dfs: v2f64_rr<"dfs">;
217 def int_spu_si_dfm: v2f64_rr<"dfm">;
218
219 //def int_spu_si_dfceq: v2f64_rr<"dfceq">;
220 //def int_spu_si_dfcmeq: v2f64_rr<"dfcmeq">;
221 //def int_spu_si_dfcgt: v2f64_rr<"dfcgt">;
222 //def int_spu_si_dfcmgt: v2f64_rr<"dfcmgt">;
223
224 def int_spu_si_dfnma: v2f64_rr<"dfnma">;
225 def int_spu_si_dfma: v2f64_rr<"dfma">;
226 def int_spu_si_dfnms: v2f64_rr<"dfnms">;
227 def int_spu_si_dfms: v2f64_rr<"dfms">;
228
229 }
2020 SUCH DAMAGES ARE FORESEEABLE.
2121
2222 ---------------------------------------------------------------------------
23 --WARNING--:
2324 --WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
25 --WARNING--:
26
27 If you are brave enough to try this code or help to hack on it, be sure
28 to add 'spu' to configure's --enable-targets option, e.g.:
29
30 ./configure \
31 --enable-targets=x86,x86_64,powerpc,spu
32
2433 ---------------------------------------------------------------------------
2534
2635 TODO: