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[ARM] Use searchable-table for banked registers This is a continuation of https://reviews.llvm.org/D36219 This patch uses reverse mapping (encoding->name) in ARMInstPrinter::printBankedRegOperand to get rid of hard-coded values (as pointed out by @olista01). Reviewed by: @fhahn, @rovka, @olista01 Differential Revision: https://reviews.llvm.org/D36260 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310072 91177308-0d34-0410-b5e6-96231b3b80d8 Javed Absar 3 years ago
1 changed file(s) with 7 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
872872 const MCSubtargetInfo &STI,
873873 raw_ostream &O) {
874874 uint32_t Banked = MI->getOperand(OpNum).getImm();
875 uint32_t R = (Banked & 0x20) >> 5;
876 uint32_t SysM = Banked & 0x1f;
877
878 // Nothing much we can do about this, the encodings are specified in B9.2.3 of
879 // the ARM ARM v7C, and are all over the shop.
880 if (R) {
881 O << "SPSR_";
882
883 switch (SysM) {
884 case 0x0e:
885 O << "fiq";
886 return;
887 case 0x10:
888 O << "irq";
889 return;
890 case 0x12:
891 O << "svc";
892 return;
893 case 0x14:
894 O << "abt";
895 return;
896 case 0x16:
897 O << "und";
898 return;
899 case 0x1c:
900 O << "mon";
901 return;
902 case 0x1e:
903 O << "hyp";
904 return;
905 default:
906 llvm_unreachable("Invalid banked SPSR register");
907 }
908 }
909
910 assert(!R && "should have dealt with SPSR regs");
911 const char *RegNames[] = {
912 "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr",
913 "", "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq",
914 "lr_fiq", "", "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt",
915 "sp_abt", "lr_und", "sp_und", "", "", "", "",
916 "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"};
917 const char *Name = RegNames[SysM];
918 assert(Name[0] && "invalid banked register operand");
919
875 auto TheReg = ARMBankedReg::lookupBankedRegByEncoding(Banked);
876 assert(TheReg && "invalid banked register operand");
877 std::string Name = TheReg->Name;
878
879 uint32_t isSPSR = (Banked & 0x20) >> 5;
880 if (isSPSR)
881 Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_'
920882 O << Name;
921883 }
922884