llvm.org GIT mirror llvm / b1576f5
Change the x86 assembly output to use tab characters to separate the mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40648 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 13 years ago
35 changed file(s) with 1164 addition(s) and 1164 deletion(s). Raw diff Collapse all Expand all
164164 [(set RFP64:$dst,
165165 (OpNode RFP64:$src1, (extloadf32 addr:$src2)))]>;
166166 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
167 !strconcat("f", !strconcat(asmstring, "{s} $src"))>;
167 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
168168 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
169 !strconcat("f", !strconcat(asmstring, "{l} $src"))>;
169 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))>;
170170 // ST(0) = ST(0) + [memint]
171171 def _FpI16m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
172172 [(set RFP32:$dst, (OpNode RFP32:$src1,
181181 [(set RFP64:$dst, (OpNode RFP64:$src1,
182182 (X86fild addr:$src2, i32)))]>;
183183 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
184 !strconcat("fi", !strconcat(asmstring, "{s} $src"))>;
184 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))>;
185185 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
186 !strconcat("fi", !strconcat(asmstring, "{l} $src"))>;
186 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))>;
187187 }
188188
189189 defm ADD : FPBinary_rr;
207207 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
208208 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
209209 // we have to put some 'r's in and take them out of weird places.
210 def ADD_FST0r : FPST0rInst <0xC0, "fadd $op">;
211 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
212 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp $op">;
213 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr $op">;
214 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
215 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">;
216 def SUB_FST0r : FPST0rInst <0xE0, "fsub $op">;
217 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
218 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
219 def MUL_FST0r : FPST0rInst <0xC8, "fmul $op">;
220 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
221 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp $op">;
222 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr $op">;
223 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
224 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">;
225 def DIV_FST0r : FPST0rInst <0xF0, "fdiv $op">;
226 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
227 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
210 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
211 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
212 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
213 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
214 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
215 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
216 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
217 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
218 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
219 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
220 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
221 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
222 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
223 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
224 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
225 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
226 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
227 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
228228
229229 // Unary operations.
230230 multiclass FPUnary opcode, string asmstring> {
269269
270270 // These are not factored because there's no clean way to pass DA/DB.
271271 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
272 "fcmovb {$op, %st(0)|%ST(0), $op}">, DA;
272 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
273273 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
274 "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA;
274 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
275275 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
276 "fcmove {$op, %st(0)|%ST(0), $op}">, DA;
276 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
277277 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
278 "fcmovu {$op, %st(0)|%ST(0), $op}">, DA;
278 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
279279 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
280 "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB;
280 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
281281 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
282 "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB;
282 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
283283 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
284 "fcmovne {$op, %st(0)|%ST(0), $op}">, DB;
284 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
285285 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
286 "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB;
286 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
287287
288288 // Floating point loads & stores.
289289 def LD_Fp32m : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
320320 def IST_Fp32m64 : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
321321 def IST_Fp64m64 : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
322322
323 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s} $src">;
324 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l} $src">;
325 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s} $src">;
326 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l} $src">;
327 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll} $src">;
328 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s} $dst">;
329 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l} $dst">;
330 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s} $dst">;
331 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l} $dst">;
332 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s} $dst">;
333 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l} $dst">;
334 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s} $dst">;
335 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l} $dst">;
336 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll} $dst">;
323 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
324 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
325 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
326 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
327 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
328 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
329 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
330 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
331 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
332 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
333 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
334 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
335 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
336 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
337337
338338 // FISTTP requires SSE3 even though it's a FPStack op.
339339 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
355355 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
356356 Requires<[HasSSE3]>;
357357
358 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s} $dst">;
359 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l} $dst">;
360 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll} $dst">;
358 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
359 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
360 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
361361
362362 // FP Stack manipulation instructions.
363 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld $op">, D9;
364 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst $op">, DD;
365 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp $op">, DD;
366 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch $op">, D9;
363 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
364 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
365 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
366 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
367367
368368 // Floating point constant loads.
369369 let isReMaterializable = 1 in {
393393
394394 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
395395 (outs), (ins RST:$reg),
396 "fucom $reg">, DD, Imp<[ST0],[]>;
396 "fucom\t$reg">, DD, Imp<[ST0],[]>;
397397 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
398398 (outs), (ins RST:$reg),
399 "fucomp $reg">, DD, Imp<[ST0],[]>;
399 "fucomp\t$reg">, DD, Imp<[ST0],[]>;
400400 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
401401 (outs), (ins),
402402 "fucompp">, DA, Imp<[ST0],[]>;
403403
404404 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
405405 (outs), (ins RST:$reg),
406 "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
406 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
407407 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
408408 (outs), (ins RST:$reg),
409 "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
409 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
410410
411411 // Floating point flag ops.
412412 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
413413 (outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>;
414414
415415 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
416 (outs), (ins i16mem:$dst), "fnstcw $dst", []>;
416 (outs), (ins i16mem:$dst), "fnstcw\t$dst", []>;
417417 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
418 (outs), (ins i16mem:$dst), "fldcw $dst", []>;
418 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
419419
420420 //===----------------------------------------------------------------------===//
421421 // Non-Instruction Patterns
274274 let isTerminator = 1, isReturn = 1, isBarrier = 1,
275275 hasCtrlDep = 1 in {
276276 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
277 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret $amt",
277 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
278278 [(X86retflag imm:$amt)]>;
279279 }
280280
285285
286286 // Indirect branches
287287 let isBranch = 1, isBarrier = 1 in
288 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
288 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
289289
290290 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
291 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l} {*}$dst",
291 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
292292 [(brind GR32:$dst)]>;
293 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l} {*}$dst",
293 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
294294 [(brind (loadi32 addr:$dst))]>;
295295 }
296296
297297 // Conditional branches
298 def JE : IBr<0x84, (ins brtarget:$dst), "je $dst",
298 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
299299 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
300 def JNE : IBr<0x85, (ins brtarget:$dst), "jne $dst",
300 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
301301 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
302 def JL : IBr<0x8C, (ins brtarget:$dst), "jl $dst",
302 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
303303 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
304 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle $dst",
304 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
305305 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
306 def JG : IBr<0x8F, (ins brtarget:$dst), "jg $dst",
306 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
307307 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
308 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge $dst",
308 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
309309 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
310310
311 def JB : IBr<0x82, (ins brtarget:$dst), "jb $dst",
311 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
312312 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
313 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe $dst",
313 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
314314 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
315 def JA : IBr<0x87, (ins brtarget:$dst), "ja $dst",
315 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
316316 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
317 def JAE : IBr<0x83, (ins brtarget:$dst), "jae $dst",
317 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
318318 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
319319
320 def JS : IBr<0x88, (ins brtarget:$dst), "js $dst",
320 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
321321 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
322 def JNS : IBr<0x89, (ins brtarget:$dst), "jns $dst",
322 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
323323 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
324 def JP : IBr<0x8A, (ins brtarget:$dst), "jp $dst",
324 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
325325 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
326 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp $dst",
326 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
327327 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
328 def JO : IBr<0x80, (ins brtarget:$dst), "jo $dst",
328 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
329329 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
330 def JNO : IBr<0x81, (ins brtarget:$dst), "jno $dst",
330 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
331331 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
332332
333333 //===----------------------------------------------------------------------===//
339339 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
340340 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
341341 def CALLpcrel32 : I<0xE8, RawFrm, (outs), (ins i32imm:$dst, variable_ops),
342 "call ${dst:call}", []>;
342 "call\t${dst:call}", []>;
343343 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
344 "call {*}$dst", [(X86call GR32:$dst)]>;
344 "call\t{*}$dst", [(X86call GR32:$dst)]>;
345345 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
346 "call {*}$dst", []>;
346 "call\t{*}$dst", []>;
347347 }
348348
349349 // Tail call stuff.
350350 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
351 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
351 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAIL CALL",
352352 []>;
353353 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
354 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp {*}$dst # TAIL CALL",
354 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp\t{*}$dst # TAIL CALL",
355355 []>;
356356 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
357357 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
358 "jmp {*}$dst # TAIL CALL", []>;
358 "jmp\t{*}$dst # TAIL CALL", []>;
359359
360360 //===----------------------------------------------------------------------===//
361361 // Miscellaneous Instructions...
363363 def LEAVE : I<0xC9, RawFrm,
364364 (outs), (ins), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
365365 def POP32r : I<0x58, AddRegFrm,
366 (outs GR32:$reg), (ins), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
366 (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, Imp<[ESP],[ESP]>;
367367
368368 def PUSH32r : I<0x50, AddRegFrm,
369 (outs), (ins GR32:$reg), "push{l} $reg", []>, Imp<[ESP],[ESP]>;
369 (outs), (ins GR32:$reg), "push{l}\t$reg", []>, Imp<[ESP],[ESP]>;
370370
371371 def MovePCtoStack : I<0, Pseudo, (outs), (ins piclabel:$label),
372 "call $label", []>;
372 "call\t$label", []>;
373373
374374 let isTwoAddress = 1 in // GR32 = bswap GR32
375375 def BSWAP32r : I<0xC8, AddRegFrm,
376376 (outs GR32:$dst), (ins GR32:$src),
377 "bswap{l} $dst",
377 "bswap{l}\t$dst",
378378 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
379379
380380 // FIXME: Model xchg* as two address instructions?
381381 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
382382 (outs), (ins GR8:$src1, GR8:$src2),
383 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
383 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
384384 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
385385 (outs), (ins GR16:$src1, GR16:$src2),
386 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
386 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
387387 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
388388 (outs), (ins GR32:$src1, GR32:$src2),
389 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
389 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
390390
391391 def XCHG8mr : I<0x86, MRMDestMem,
392392 (outs), (ins i8mem:$src1, GR8:$src2),
393 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
393 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
394394 def XCHG16mr : I<0x87, MRMDestMem,
395395 (outs), (ins i16mem:$src1, GR16:$src2),
396 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
396 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
397397 def XCHG32mr : I<0x87, MRMDestMem,
398398 (outs), (ins i32mem:$src1, GR32:$src2),
399 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
399 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
400400 def XCHG8rm : I<0x86, MRMSrcMem,
401401 (outs), (ins GR8:$src1, i8mem:$src2),
402 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
402 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
403403 def XCHG16rm : I<0x87, MRMSrcMem,
404404 (outs), (ins GR16:$src1, i16mem:$src2),
405 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
405 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
406406 def XCHG32rm : I<0x87, MRMSrcMem,
407407 (outs), (ins GR32:$src1, i32mem:$src2),
408 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
408 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
409409
410410 def LEA16r : I<0x8D, MRMSrcMem,
411411 (outs GR16:$dst), (ins i32mem:$src),
412 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
412 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
413413 def LEA32r : I<0x8D, MRMSrcMem,
414414 (outs GR32:$dst), (ins lea32mem:$src),
415 "lea{l} {$src|$dst}, {$dst|$src}",
415 "lea{l}\t{$src|$dst}, {$dst|$src}",
416416 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
417417
418418 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
442442 // Input/Output Instructions...
443443 //
444444 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
445 "in{b} {%dx, %al|%AL, %DX}",
445 "in{b}\t{%dx, %al|%AL, %DX}",
446446 []>, Imp<[DX], [AL]>;
447447 def IN16rr : I<0xED, RawFrm, (outs), (ins),
448 "in{w} {%dx, %ax|%AX, %DX}",
448 "in{w}\t{%dx, %ax|%AX, %DX}",
449449 []>, Imp<[DX], [AX]>, OpSize;
450450 def IN32rr : I<0xED, RawFrm, (outs), (ins),
451 "in{l} {%dx, %eax|%EAX, %DX}",
451 "in{l}\t{%dx, %eax|%EAX, %DX}",
452452 []>, Imp<[DX],[EAX]>;
453453
454454 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
455 "in{b} {$port, %al|%AL, $port}",
455 "in{b}\t{$port, %al|%AL, $port}",
456456 []>,
457457 Imp<[], [AL]>;
458458 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
459 "in{w} {$port, %ax|%AX, $port}",
459 "in{w}\t{$port, %ax|%AX, $port}",
460460 []>,
461461 Imp<[], [AX]>, OpSize;
462462 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
463 "in{l} {$port, %eax|%EAX, $port}",
463 "in{l}\t{$port, %eax|%EAX, $port}",
464464 []>,
465465 Imp<[],[EAX]>;
466466
467467 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
468 "out{b} {%al, %dx|%DX, %AL}",
468 "out{b}\t{%al, %dx|%DX, %AL}",
469469 []>, Imp<[DX, AL], []>;
470470 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
471 "out{w} {%ax, %dx|%DX, %AX}",
471 "out{w}\t{%ax, %dx|%DX, %AX}",
472472 []>, Imp<[DX, AX], []>, OpSize;
473473 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
474 "out{l} {%eax, %dx|%DX, %EAX}",
474 "out{l}\t{%eax, %dx|%DX, %EAX}",
475475 []>, Imp<[DX, EAX], []>;
476476
477477 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
478 "out{b} {%al, $port|$port, %AL}",
478 "out{b}\t{%al, $port|$port, %AL}",
479479 []>,
480480 Imp<[AL], []>;
481481 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
482 "out{w} {%ax, $port|$port, %AX}",
482 "out{w}\t{%ax, $port|$port, %AX}",
483483 []>,
484484 Imp<[AX], []>, OpSize;
485485 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
486 "out{l} {%eax, $port|$port, %EAX}",
486 "out{l}\t{%eax, $port|$port, %EAX}",
487487 []>,
488488 Imp<[EAX], []>;
489489
491491 // Move Instructions...
492492 //
493493 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
494 "mov{b} {$src, $dst|$dst, $src}", []>;
494 "mov{b}\t{$src, $dst|$dst, $src}", []>;
495495 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
496 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
496 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
497497 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
498 "mov{l} {$src, $dst|$dst, $src}", []>;
498 "mov{l}\t{$src, $dst|$dst, $src}", []>;
499499 let isReMaterializable = 1 in {
500500 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
501 "mov{b} {$src, $dst|$dst, $src}",
501 "mov{b}\t{$src, $dst|$dst, $src}",
502502 [(set GR8:$dst, imm:$src)]>;
503503 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
504 "mov{w} {$src, $dst|$dst, $src}",
504 "mov{w}\t{$src, $dst|$dst, $src}",
505505 [(set GR16:$dst, imm:$src)]>, OpSize;
506506 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
507 "mov{l} {$src, $dst|$dst, $src}",
507 "mov{l}\t{$src, $dst|$dst, $src}",
508508 [(set GR32:$dst, imm:$src)]>;
509509 }
510510 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
511 "mov{b} {$src, $dst|$dst, $src}",
511 "mov{b}\t{$src, $dst|$dst, $src}",
512512 [(store (i8 imm:$src), addr:$dst)]>;
513513 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
514 "mov{w} {$src, $dst|$dst, $src}",
514 "mov{w}\t{$src, $dst|$dst, $src}",
515515 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
516516 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
517 "mov{l} {$src, $dst|$dst, $src}",
517 "mov{l}\t{$src, $dst|$dst, $src}",
518518 [(store (i32 imm:$src), addr:$dst)]>;
519519
520520 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
521 "mov{b} {$src, $dst|$dst, $src}",
521 "mov{b}\t{$src, $dst|$dst, $src}",
522522 [(set GR8:$dst, (load addr:$src))]>;
523523 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
524 "mov{w} {$src, $dst|$dst, $src}",
524 "mov{w}\t{$src, $dst|$dst, $src}",
525525 [(set GR16:$dst, (load addr:$src))]>, OpSize;
526526 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
527 "mov{l} {$src, $dst|$dst, $src}",
527 "mov{l}\t{$src, $dst|$dst, $src}",
528528 [(set GR32:$dst, (load addr:$src))]>;
529529
530530 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
531 "mov{b} {$src, $dst|$dst, $src}",
531 "mov{b}\t{$src, $dst|$dst, $src}",
532532 [(store GR8:$src, addr:$dst)]>;
533533 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
534 "mov{w} {$src, $dst|$dst, $src}",
534 "mov{w}\t{$src, $dst|$dst, $src}",
535535 [(store GR16:$src, addr:$dst)]>, OpSize;
536536 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
537 "mov{l} {$src, $dst|$dst, $src}",
537 "mov{l}\t{$src, $dst|$dst, $src}",
538538 [(store GR32:$src, addr:$dst)]>;
539539
540540 //===----------------------------------------------------------------------===//
542542 //
543543
544544 // Extra precision multiplication
545 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b} $src",
545 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
546546 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
547547 // This probably ought to be moved to a def : Pat<> if the
548548 // syntax can be accepted.
549549 [(set AL, (mul AL, GR8:$src))]>,
550550 Imp<[AL],[AX]>; // AL,AH = AL*GR8
551 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w} $src", []>,
551 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
552552 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
553 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l} $src", []>,
553 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>,
554554 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
555555 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
556 "mul{b} $src",
556 "mul{b}\t$src",
557557 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
558558 // This probably ought to be moved to a def : Pat<> if the
559559 // syntax can be accepted.
560560 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
561561 Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
562562 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
563 "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
563 "mul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
564564 OpSize; // AX,DX = AX*[mem16]
565565 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
566 "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
567
568 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b} $src", []>,
566 "mul{l}\t$src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
567
568 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
569569 Imp<[AL],[AX]>; // AL,AH = AL*GR8
570 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w} $src", []>,
570 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
571571 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
572 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l} $src", []>,
572 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
573573 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
574574 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
575 "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
575 "imul{b}\t$src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
576576 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
577 "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
577 "imul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
578578 OpSize; // AX,DX = AX*[mem16]
579579 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
580 "imul{l} $src", []>,
580 "imul{l}\t$src", []>,
581581 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
582582
583583 // unsigned division/remainder
584584 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
585 "div{b} $src", []>, Imp<[AX],[AX]>;
585 "div{b}\t$src", []>, Imp<[AX],[AX]>;
586586 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
587 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
587 "div{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
588588 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
589 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
589 "div{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
590590 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
591 "div{b} $src", []>, Imp<[AX],[AX]>;
591 "div{b}\t$src", []>, Imp<[AX],[AX]>;
592592 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
593 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
593 "div{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
594594 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
595 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
595 "div{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
596596
597597 // Signed division/remainder.
598598 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
599 "idiv{b} $src", []>, Imp<[AX],[AX]>;
599 "idiv{b}\t$src", []>, Imp<[AX],[AX]>;
600600 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
601 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
601 "idiv{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
602602 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
603 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
603 "idiv{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
604604 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
605 "idiv{b} $src", []>, Imp<[AX],[AX]>;
605 "idiv{b}\t$src", []>, Imp<[AX],[AX]>;
606606 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
607 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
607 "idiv{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
608608 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
609 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
609 "idiv{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
610610
611611
612612 //===----------------------------------------------------------------------===//
617617 // Conditional moves
618618 def CMOVB16rr : I<0x42, MRMSrcReg, // if
619619 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
620 "cmovb {$src2, $dst|$dst, $src2}",
620 "cmovb\t{$src2, $dst|$dst, $src2}",
621621 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
622622 X86_COND_B))]>,
623623 TB, OpSize;
624624 def CMOVB16rm : I<0x42, MRMSrcMem, // if
625625 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
626 "cmovb {$src2, $dst|$dst, $src2}",
626 "cmovb\t{$src2, $dst|$dst, $src2}",
627627 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
628628 X86_COND_B))]>,
629629 TB, OpSize;
630630 def CMOVB32rr : I<0x42, MRMSrcReg, // if
631631 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
632 "cmovb {$src2, $dst|$dst, $src2}",
632 "cmovb\t{$src2, $dst|$dst, $src2}",
633633 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
634634 X86_COND_B))]>,
635635 TB;
636636 def CMOVB32rm : I<0x42, MRMSrcMem, // if
637637 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
638 "cmovb {$src2, $dst|$dst, $src2}",
638 "cmovb\t{$src2, $dst|$dst, $src2}",
639639 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
640640 X86_COND_B))]>,
641641 TB;
642642
643643 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
644644 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
645 "cmovae {$src2, $dst|$dst, $src2}",
645 "cmovae\t{$src2, $dst|$dst, $src2}",
646646 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
647647 X86_COND_AE))]>,
648648 TB, OpSize;
649649 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
650650 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
651 "cmovae {$src2, $dst|$dst, $src2}",
651 "cmovae\t{$src2, $dst|$dst, $src2}",
652652 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
653653 X86_COND_AE))]>,
654654 TB, OpSize;
655655 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
656656 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
657 "cmovae {$src2, $dst|$dst, $src2}",
657 "cmovae\t{$src2, $dst|$dst, $src2}",
658658 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
659659 X86_COND_AE))]>,
660660 TB;
661661 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
662662 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
663 "cmovae {$src2, $dst|$dst, $src2}",
663 "cmovae\t{$src2, $dst|$dst, $src2}",
664664 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
665665 X86_COND_AE))]>,
666666 TB;
667667
668668 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
669669 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
670 "cmove {$src2, $dst|$dst, $src2}",
670 "cmove\t{$src2, $dst|$dst, $src2}",
671671 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
672672 X86_COND_E))]>,
673673 TB, OpSize;
674674 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
675675 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
676 "cmove {$src2, $dst|$dst, $src2}",
676 "cmove\t{$src2, $dst|$dst, $src2}",
677677 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
678678 X86_COND_E))]>,
679679 TB, OpSize;
680680 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
681681 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
682 "cmove {$src2, $dst|$dst, $src2}",
682 "cmove\t{$src2, $dst|$dst, $src2}",
683683 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
684684 X86_COND_E))]>,
685685 TB;
686686 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
687687 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
688 "cmove {$src2, $dst|$dst, $src2}",
688 "cmove\t{$src2, $dst|$dst, $src2}",
689689 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
690690 X86_COND_E))]>,
691691 TB;
692692
693693 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
694694 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
695 "cmovne {$src2, $dst|$dst, $src2}",
695 "cmovne\t{$src2, $dst|$dst, $src2}",
696696 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
697697 X86_COND_NE))]>,
698698 TB, OpSize;
699699 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
700700 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
701 "cmovne {$src2, $dst|$dst, $src2}",
701 "cmovne\t{$src2, $dst|$dst, $src2}",
702702 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
703703 X86_COND_NE))]>,
704704 TB, OpSize;
705705 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
706706 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
707 "cmovne {$src2, $dst|$dst, $src2}",
707 "cmovne\t{$src2, $dst|$dst, $src2}",
708708 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
709709 X86_COND_NE))]>,
710710 TB;
711711 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
712712 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
713 "cmovne {$src2, $dst|$dst, $src2}",
713 "cmovne\t{$src2, $dst|$dst, $src2}",
714714 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
715715 X86_COND_NE))]>,
716716 TB;
717717
718718 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
719719 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
720 "cmovbe {$src2, $dst|$dst, $src2}",
720 "cmovbe\t{$src2, $dst|$dst, $src2}",
721721 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
722722 X86_COND_BE))]>,
723723 TB, OpSize;
724724 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
725725 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
726 "cmovbe {$src2, $dst|$dst, $src2}",
726 "cmovbe\t{$src2, $dst|$dst, $src2}",
727727 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
728728 X86_COND_BE))]>,
729729 TB, OpSize;
730730 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
731731 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
732 "cmovbe {$src2, $dst|$dst, $src2}",
732 "cmovbe\t{$src2, $dst|$dst, $src2}",
733733 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
734734 X86_COND_BE))]>,
735735 TB;
736736 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
737737 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
738 "cmovbe {$src2, $dst|$dst, $src2}",
738 "cmovbe\t{$src2, $dst|$dst, $src2}",
739739 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
740740 X86_COND_BE))]>,
741741 TB;
742742
743743 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
744744 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
745 "cmova {$src2, $dst|$dst, $src2}",
745 "cmova\t{$src2, $dst|$dst, $src2}",
746746 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
747747 X86_COND_A))]>,
748748 TB, OpSize;
749749 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
750750 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
751 "cmova {$src2, $dst|$dst, $src2}",
751 "cmova\t{$src2, $dst|$dst, $src2}",
752752 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
753753 X86_COND_A))]>,
754754 TB, OpSize;
755755 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
756756 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
757 "cmova {$src2, $dst|$dst, $src2}",
757 "cmova\t{$src2, $dst|$dst, $src2}",
758758 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
759759 X86_COND_A))]>,
760760 TB;
761761 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
762762 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
763 "cmova {$src2, $dst|$dst, $src2}",
763 "cmova\t{$src2, $dst|$dst, $src2}",
764764 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
765765 X86_COND_A))]>,
766766 TB;
767767
768768 def CMOVL16rr : I<0x4C, MRMSrcReg, // if
769769 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
770 "cmovl {$src2, $dst|$dst, $src2}",
770 "cmovl\t{$src2, $dst|$dst, $src2}",
771771 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
772772 X86_COND_L))]>,
773773 TB, OpSize;
774774 def CMOVL16rm : I<0x4C, MRMSrcMem, // if
775775 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
776 "cmovl {$src2, $dst|$dst, $src2}",
776 "cmovl\t{$src2, $dst|$dst, $src2}",
777777 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
778778 X86_COND_L))]>,
779779 TB, OpSize;
780780 def CMOVL32rr : I<0x4C, MRMSrcReg, // if
781781 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
782 "cmovl {$src2, $dst|$dst, $src2}",
782 "cmovl\t{$src2, $dst|$dst, $src2}",
783783 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
784784 X86_COND_L))]>,
785785 TB;
786786 def CMOVL32rm : I<0x4C, MRMSrcMem, // if
787787 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
788 "cmovl {$src2, $dst|$dst, $src2}",
788 "cmovl\t{$src2, $dst|$dst, $src2}",
789789 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
790790 X86_COND_L))]>,
791791 TB;
792792
793793 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
794794 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
795 "cmovge {$src2, $dst|$dst, $src2}",
795 "cmovge\t{$src2, $dst|$dst, $src2}",
796796 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
797797 X86_COND_GE))]>,
798798 TB, OpSize;
799799 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
800800 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
801 "cmovge {$src2, $dst|$dst, $src2}",
801 "cmovge\t{$src2, $dst|$dst, $src2}",
802802 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
803803 X86_COND_GE))]>,
804804 TB, OpSize;
805805 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
806806 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
807 "cmovge {$src2, $dst|$dst, $src2}",
807 "cmovge\t{$src2, $dst|$dst, $src2}",
808808 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
809809 X86_COND_GE))]>,
810810 TB;
811811 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
812812 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
813 "cmovge {$src2, $dst|$dst, $src2}",
813 "cmovge\t{$src2, $dst|$dst, $src2}",
814814 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
815815 X86_COND_GE))]>,
816816 TB;
817817
818818 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
819819 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
820 "cmovle {$src2, $dst|$dst, $src2}",
820 "cmovle\t{$src2, $dst|$dst, $src2}",
821821 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
822822 X86_COND_LE))]>,
823823 TB, OpSize;
824824 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
825825 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
826 "cmovle {$src2, $dst|$dst, $src2}",
826 "cmovle\t{$src2, $dst|$dst, $src2}",
827827 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
828828 X86_COND_LE))]>,
829829 TB, OpSize;
830830 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
831831 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
832 "cmovle {$src2, $dst|$dst, $src2}",
832 "cmovle\t{$src2, $dst|$dst, $src2}",
833833 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
834834 X86_COND_LE))]>,
835835 TB;
836836 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
837837 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
838 "cmovle {$src2, $dst|$dst, $src2}",
838 "cmovle\t{$src2, $dst|$dst, $src2}",
839839 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
840840 X86_COND_LE))]>,
841841 TB;
842842
843843 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
844844 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
845 "cmovg {$src2, $dst|$dst, $src2}",
845 "cmovg\t{$src2, $dst|$dst, $src2}",
846846 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
847847 X86_COND_G))]>,
848848 TB, OpSize;
849849 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
850850 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
851 "cmovg {$src2, $dst|$dst, $src2}",
851 "cmovg\t{$src2, $dst|$dst, $src2}",
852852 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
853853 X86_COND_G))]>,
854854 TB, OpSize;
855855 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
856856 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
857 "cmovg {$src2, $dst|$dst, $src2}",
857 "cmovg\t{$src2, $dst|$dst, $src2}",
858858 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
859859 X86_COND_G))]>,
860860 TB;
861861 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
862862 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
863 "cmovg {$src2, $dst|$dst, $src2}",
863 "cmovg\t{$src2, $dst|$dst, $src2}",
864864 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
865865 X86_COND_G))]>,
866866 TB;
867867
868868 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
869869 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
870 "cmovs {$src2, $dst|$dst, $src2}",
870 "cmovs\t{$src2, $dst|$dst, $src2}",
871871 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
872872 X86_COND_S))]>,
873873 TB, OpSize;
874874 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
875875 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
876 "cmovs {$src2, $dst|$dst, $src2}",
876 "cmovs\t{$src2, $dst|$dst, $src2}",
877877 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
878878 X86_COND_S))]>,
879879 TB, OpSize;
880880 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
881881 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
882 "cmovs {$src2, $dst|$dst, $src2}",
882 "cmovs\t{$src2, $dst|$dst, $src2}",
883883 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
884884 X86_COND_S))]>,
885885 TB;
886886 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
887887 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
888 "cmovs {$src2, $dst|$dst, $src2}",
888 "cmovs\t{$src2, $dst|$dst, $src2}",
889889 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
890890 X86_COND_S))]>,
891891 TB;
892892
893893 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
894894 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
895 "cmovns {$src2, $dst|$dst, $src2}",
895 "cmovns\t{$src2, $dst|$dst, $src2}",
896896 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
897897 X86_COND_NS))]>,
898898 TB, OpSize;
899899 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
900900 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
901 "cmovns {$src2, $dst|$dst, $src2}",
901 "cmovns\t{$src2, $dst|$dst, $src2}",
902902 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
903903 X86_COND_NS))]>,
904904 TB, OpSize;
905905 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
906906 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
907 "cmovns {$src2, $dst|$dst, $src2}",
907 "cmovns\t{$src2, $dst|$dst, $src2}",
908908 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
909909 X86_COND_NS))]>,
910910 TB;
911911 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
912912 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
913 "cmovns {$src2, $dst|$dst, $src2}",
913 "cmovns\t{$src2, $dst|$dst, $src2}",
914914 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
915915 X86_COND_NS))]>,
916916 TB;
917917
918918 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
919919 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
920 "cmovp {$src2, $dst|$dst, $src2}",
920 "cmovp\t{$src2, $dst|$dst, $src2}",
921921 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
922922 X86_COND_P))]>,
923923 TB, OpSize;
924924 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
925925 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
926 "cmovp {$src2, $dst|$dst, $src2}",
926 "cmovp\t{$src2, $dst|$dst, $src2}",
927927 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
928928 X86_COND_P))]>,
929929 TB, OpSize;
930930 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
931931 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
932 "cmovp {$src2, $dst|$dst, $src2}",
932 "cmovp\t{$src2, $dst|$dst, $src2}",
933933 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
934934 X86_COND_P))]>,
935935 TB;
936936 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
937937 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
938 "cmovp {$src2, $dst|$dst, $src2}",
938 "cmovp\t{$src2, $dst|$dst, $src2}",
939939 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
940940 X86_COND_P))]>,
941941 TB;
942942
943943 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
944944 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
945 "cmovnp {$src2, $dst|$dst, $src2}",
945 "cmovnp\t{$src2, $dst|$dst, $src2}",
946946 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
947947 X86_COND_NP))]>,
948948 TB, OpSize;
949949 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
950950 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
951 "cmovnp {$src2, $dst|$dst, $src2}",
951 "cmovnp\t{$src2, $dst|$dst, $src2}",
952952 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
953953 X86_COND_NP))]>,
954954 TB, OpSize;
955955 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
956956 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
957 "cmovnp {$src2, $dst|$dst, $src2}",
957 "cmovnp\t{$src2, $dst|$dst, $src2}",
958958 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
959959 X86_COND_NP))]>,
960960 TB;
961961 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
962962 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
963 "cmovnp {$src2, $dst|$dst, $src2}",
963 "cmovnp\t{$src2, $dst|$dst, $src2}",
964964 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
965965 X86_COND_NP))]>,
966966 TB;
968968
969969 // unary instructions
970970 let CodeSize = 2 in {
971 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b} $dst",
971 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
972972 [(set GR8:$dst, (ineg GR8:$src))]>;
973 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w} $dst",
973 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
974974 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
975 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l} $dst",
975 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
976976 [(set GR32:$dst, (ineg GR32:$src))]>;
977977 let isTwoAddress = 0 in {
978 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b} $dst",
978 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
979979 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
980 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w} $dst",
980 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
981981 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
982 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l} $dst",
982 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
983983 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
984984
985985 }
986986
987 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b} $dst",
987 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
988988 [(set GR8:$dst, (not GR8:$src))]>;
989 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w} $dst",
989 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
990990 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
991 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l} $dst",
991 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
992992 [(set GR32:$dst, (not GR32:$src))]>;
993993 let isTwoAddress = 0 in {
994 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b} $dst",
994 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
995995 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
996 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w} $dst",
996 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
997997 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
998 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l} $dst",
998 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
999999 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
10001000 }
10011001 } // CodeSize
10021002
10031003 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
10041004 let CodeSize = 2 in
1005 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b} $dst",
1005 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
10061006 [(set GR8:$dst, (add GR8:$src, 1))]>;
10071007 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1008 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w} $dst",
1008 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
10091009 [(set GR16:$dst, (add GR16:$src, 1))]>,
10101010 OpSize, Requires<[In32BitMode]>;
1011 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l} $dst",
1011 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
10121012 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
10131013 }
10141014 let isTwoAddress = 0, CodeSize = 2 in {
1015 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b} $dst",
1015 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
10161016 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1017 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w} $dst",
1017 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
10181018 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1019 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l} $dst",
1019 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
10201020 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
10211021 }
10221022
10231023 let CodeSize = 2 in
1024 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b} $dst",
1024 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
10251025 [(set GR8:$dst, (add GR8:$src, -1))]>;
10261026 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1027 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w} $dst",
1027 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
10281028 [(set GR16:$dst, (add GR16:$src, -1))]>,
10291029 OpSize, Requires<[In32BitMode]>;
1030 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l} $dst",
1030 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
10311031 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
10321032 }
10331033
10341034 let isTwoAddress = 0, CodeSize = 2 in {
1035 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b} $dst",
1035 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
10361036 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1037 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w} $dst",
1037 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
10381038 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1039 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l} $dst",
1039 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
10401040 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
10411041 }
10421042
10441044 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
10451045 def AND8rr : I<0x20, MRMDestReg,
10461046 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1047 "and{b} {$src2, $dst|$dst, $src2}",
1047 "and{b}\t{$src2, $dst|$dst, $src2}",
10481048 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
10491049 def AND16rr : I<0x21, MRMDestReg,
10501050 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1051 "and{w} {$src2, $dst|$dst, $src2}",
1051 "and{w}\t{$src2, $dst|$dst, $src2}",
10521052 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
10531053 def AND32rr : I<0x21, MRMDestReg,
10541054 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1055 "and{l} {$src2, $dst|$dst, $src2}",
1055 "and{l}\t{$src2, $dst|$dst, $src2}",
10561056 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
10571057 }
10581058
10591059 def AND8rm : I<0x22, MRMSrcMem,
10601060 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1061 "and{b} {$src2, $dst|$dst, $src2}",
1061 "and{b}\t{$src2, $dst|$dst, $src2}",
10621062 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
10631063 def AND16rm : I<0x23, MRMSrcMem,
10641064 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1065 "and{w} {$src2, $dst|$dst, $src2}",
1065 "and{w}\t{$src2, $dst|$dst, $src2}",
10661066 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
10671067 def AND32rm : I<0x23, MRMSrcMem,
10681068 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1069 "and{l} {$src2, $dst|$dst, $src2}",
1069 "and{l}\t{$src2, $dst|$dst, $src2}",
10701070 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
10711071
10721072 def AND8ri : Ii8<0x80, MRM4r,
10731073 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1074 "and{b} {$src2, $dst|$dst, $src2}",
1074 "and{b}\t{$src2, $dst|$dst, $src2}",
10751075 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
10761076 def AND16ri : Ii16<0x81, MRM4r,
10771077 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1078 "and{w} {$src2, $dst|$dst, $src2}",
1078 "and{w}\t{$src2, $dst|$dst, $src2}",
10791079 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
10801080 def AND32ri : Ii32<0x81, MRM4r,
10811081 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1082 "and{l} {$src2, $dst|$dst, $src2}",
1082 "and{l}\t{$src2, $dst|$dst, $src2}",
10831083 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
10841084 def AND16ri8 : Ii8<0x83, MRM4r,
10851085 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1086 "and{w} {$src2, $dst|$dst, $src2}",
1086 "and{w}\t{$src2, $dst|$dst, $src2}",
10871087 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
10881088 OpSize;
10891089 def AND32ri8 : Ii8<0x83, MRM4r,
10901090 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1091 "and{l} {$src2, $dst|$dst, $src2}",
1091 "and{l}\t{$src2, $dst|$dst, $src2}",
10921092 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
10931093
10941094 let isTwoAddress = 0 in {
10951095 def AND8mr : I<0x20, MRMDestMem,
10961096 (outs), (ins i8mem :$dst, GR8 :$src),
1097 "and{b} {$src, $dst|$dst, $src}",
1097 "and{b}\t{$src, $dst|$dst, $src}",
10981098 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
10991099 def AND16mr : I<0x21, MRMDestMem,
11001100 (outs), (ins i16mem:$dst, GR16:$src),
1101 "and{w} {$src, $dst|$dst, $src}",
1101 "and{w}\t{$src, $dst|$dst, $src}",
11021102 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
11031103 OpSize;
11041104 def AND32mr : I<0x21, MRMDestMem,
11051105 (outs), (ins i32mem:$dst, GR32:$src),
1106 "and{l} {$src, $dst|$dst, $src}",
1106 "and{l}\t{$src, $dst|$dst, $src}",
11071107 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
11081108 def AND8mi : Ii8<0x80, MRM4m,
11091109 (outs), (ins i8mem :$dst, i8imm :$src),
1110 "and{b} {$src, $dst|$dst, $src}",
1110 "and{b}\t{$src, $dst|$dst, $src}",
11111111 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
11121112 def AND16mi : Ii16<0x81, MRM4m,
11131113 (outs), (ins i16mem:$dst, i16imm:$src),
1114 "and{w} {$src, $dst|$dst, $src}",
1114 "and{w}\t{$src, $dst|$dst, $src}",
11151115 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
11161116 OpSize;
11171117 def AND32mi : Ii32<0x81, MRM4m,
11181118 (outs), (ins i32mem:$dst, i32imm:$src),
1119 "and{l} {$src, $dst|$dst, $src}",
1119 "and{l}\t{$src, $dst|$dst, $src}",
11201120 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
11211121 def AND16mi8 : Ii8<0x83, MRM4m,
11221122 (outs), (ins i16mem:$dst, i16i8imm :$src),
1123 "and{w} {$src, $dst|$dst, $src}",
1123 "and{w}\t{$src, $dst|$dst, $src}",
11241124 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
11251125 OpSize;
11261126 def AND32mi8 : Ii8<0x83, MRM4m,
11271127 (outs), (ins i32mem:$dst, i32i8imm :$src),
1128 "and{l} {$src, $dst|$dst, $src}",
1128 "and{l}\t{$src, $dst|$dst, $src}",
11291129 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
11301130 }
11311131
11321132
11331133 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
11341134 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1135 "or{b} {$src2, $dst|$dst, $src2}",
1135 "or{b}\t{$src2, $dst|$dst, $src2}",
11361136 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
11371137 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1138 "or{w} {$src2, $dst|$dst, $src2}",
1138 "or{w}\t{$src2, $dst|$dst, $src2}",
11391139 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
11401140 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1141 "or{l} {$src2, $dst|$dst, $src2}",
1141 "or{l}\t{$src2, $dst|$dst, $src2}",
11421142 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
11431143 }
11441144 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1145 "or{b} {$src2, $dst|$dst, $src2}",
1145 "or{b}\t{$src2, $dst|$dst, $src2}",
11461146 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
11471147 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1148 "or{w} {$src2, $dst|$dst, $src2}",
1148 "or{w}\t{$src2, $dst|$dst, $src2}",
11491149 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
11501150 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1151 "or{l} {$src2, $dst|$dst, $src2}",
1151 "or{l}\t{$src2, $dst|$dst, $src2}",
11521152 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
11531153
11541154 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1155 "or{b} {$src2, $dst|$dst, $src2}",
1155 "or{b}\t{$src2, $dst|$dst, $src2}",
11561156 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
11571157 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1158 "or{w} {$src2, $dst|$dst, $src2}",
1158 "or{w}\t{$src2, $dst|$dst, $src2}",
11591159 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
11601160 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1161 "or{l} {$src2, $dst|$dst, $src2}",
1161 "or{l}\t{$src2, $dst|$dst, $src2}",
11621162 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
11631163
11641164 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1165 "or{w} {$src2, $dst|$dst, $src2}",
1165 "or{w}\t{$src2, $dst|$dst, $src2}",
11661166 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
11671167 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1168 "or{l} {$src2, $dst|$dst, $src2}",
1168 "or{l}\t{$src2, $dst|$dst, $src2}",
11691169 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
11701170 let isTwoAddress = 0 in {
11711171 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1172 "or{b} {$src, $dst|$dst, $src}",
1172 "or{b}\t{$src, $dst|$dst, $src}",
11731173 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
11741174 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1175 "or{w} {$src, $dst|$dst, $src}",
1175 "or{w}\t{$src, $dst|$dst, $src}",
11761176 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
11771177 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1178 "or{l} {$src, $dst|$dst, $src}",
1178 "or{l}\t{$src, $dst|$dst, $src}",
11791179 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
11801180 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1181 "or{b} {$src, $dst|$dst, $src}",
1181 "or{b}\t{$src, $dst|$dst, $src}",
11821182 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
11831183 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1184 "or{w} {$src, $dst|$dst, $src}",
1184 "or{w}\t{$src, $dst|$dst, $src}",
11851185 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
11861186 OpSize;
11871187 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1188 "or{l} {$src, $dst|$dst, $src}",
1188 "or{l}\t{$src, $dst|$dst, $src}",
11891189 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
11901190 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1191 "or{w} {$src, $dst|$dst, $src}",
1191 "or{w}\t{$src, $dst|$dst, $src}",
11921192 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
11931193 OpSize;
11941194 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1195 "or{l} {$src, $dst|$dst, $src}",
1195 "or{l}\t{$src, $dst|$dst, $src}",
11961196 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
11971197 }
11981198
12001200 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
12011201 def XOR8rr : I<0x30, MRMDestReg,
12021202 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1203 "xor{b} {$src2, $dst|$dst, $src2}",
1203 "xor{b}\t{$src2, $dst|$dst, $src2}",
12041204 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
12051205 def XOR16rr : I<0x31, MRMDestReg,
12061206 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1207 "xor{w} {$src2, $dst|$dst, $src2}",
1207 "xor{w}\t{$src2, $dst|$dst, $src2}",
12081208 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
12091209 def XOR32rr : I<0x31, MRMDestReg,
12101210 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1211 "xor{l} {$src2, $dst|$dst, $src2}",
1211 "xor{l}\t{$src2, $dst|$dst, $src2}",
12121212 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
12131213 }
12141214
12151215 def XOR8rm : I<0x32, MRMSrcMem ,
12161216 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1217 "xor{b} {$src2, $dst|$dst, $src2}",
1217 "xor{b}\t{$src2, $dst|$dst, $src2}",
12181218 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
12191219 def XOR16rm : I<0x33, MRMSrcMem ,
12201220 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1221 "xor{w} {$src2, $dst|$dst, $src2}",
1221 "xor{w}\t{$src2, $dst|$dst, $src2}",
12221222 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
12231223 def XOR32rm : I<0x33, MRMSrcMem ,
12241224 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1225 "xor{l} {$src2, $dst|$dst, $src2}",
1225 "xor{l}\t{$src2, $dst|$dst, $src2}",
12261226 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
12271227
12281228 def XOR8ri : Ii8<0x80, MRM6r,
12291229 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1230 "xor{b} {$src2, $dst|$dst, $src2}",
1230 "xor{b}\t{$src2, $dst|$dst, $src2}",
12311231 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
12321232 def XOR16ri : Ii16<0x81, MRM6r,
12331233 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1234 "xor{w} {$src2, $dst|$dst, $src2}",
1234 "xor{w}\t{$src2, $dst|$dst, $src2}",
12351235 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
12361236 def XOR32ri : Ii32<0x81, MRM6r,
12371237 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1238 "xor{l} {$src2, $dst|$dst, $src2}",
1238 "xor{l}\t{$src2, $dst|$dst, $src2}",
12391239 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
12401240 def XOR16ri8 : Ii8<0x83, MRM6r,
12411241 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1242 "xor{w} {$src2, $dst|$dst, $src2}",
1242 "xor{w}\t{$src2, $dst|$dst, $src2}",
12431243 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
12441244 OpSize;
12451245 def XOR32ri8 : Ii8<0x83, MRM6r,
12461246 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1247 "xor{l} {$src2, $dst|$dst, $src2}",
1247 "xor{l}\t{$src2, $dst|$dst, $src2}",
12481248 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
12491249 let isTwoAddress = 0 in {
12501250 def XOR8mr : I<0x30, MRMDestMem,
12511251 (outs), (ins i8mem :$dst, GR8 :$src),
1252 "xor{b} {$src, $dst|$dst, $src}",
1252 "xor{b}\t{$src, $dst|$dst, $src}",
12531253 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
12541254 def XOR16mr : I<0x31, MRMDestMem,
12551255 (outs), (ins i16mem:$dst, GR16:$src),
1256 "xor{w} {$src, $dst|$dst, $src}",
1256 "xor{w}\t{$src, $dst|$dst, $src}",
12571257 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
12581258 OpSize;
12591259 def XOR32mr : I<0x31, MRMDestMem,
12601260 (outs), (ins i32mem:$dst, GR32:$src),
1261 "xor{l} {$src, $dst|$dst, $src}",
1261 "xor{l}\t{$src, $dst|$dst, $src}",
12621262 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
12631263 def XOR8mi : Ii8<0x80, MRM6m,
12641264 (outs), (ins i8mem :$dst, i8imm :$src),
1265 "xor{b} {$src, $dst|$dst, $src}",
1265 "xor{b}\t{$src, $dst|$dst, $src}",
12661266 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
12671267 def XOR16mi : Ii16<0x81, MRM6m,
12681268 (outs), (ins i16mem:$dst, i16imm:$src),
1269 "xor{w} {$src, $dst|$dst, $src}",
1269 "xor{w}\t{$src, $dst|$dst, $src}",
12701270 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
12711271 OpSize;
12721272 def XOR32mi : Ii32<0x81, MRM6m,
12731273 (outs), (ins i32mem:$dst, i32imm:$src),
1274 "xor{l} {$src, $dst|$dst, $src}",
1274 "xor{l}\t{$src, $dst|$dst, $src}",
12751275 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
12761276 def XOR16mi8 : Ii8<0x83, MRM6m,
12771277 (outs), (ins i16mem:$dst, i16i8imm :$src),
1278 "xor{w} {$src, $dst|$dst, $src}",
1278 "xor{w}\t{$src, $dst|$dst, $src}",
12791279 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
12801280 OpSize;
12811281 def XOR32mi8 : Ii8<0x83, MRM6m,
12821282 (outs), (ins i32mem:$dst, i32i8imm :$src),
1283 "xor{l} {$src, $dst|$dst, $src}",
1283 "xor{l}\t{$src, $dst|$dst, $src}",
12841284 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
12851285 }
12861286
12871287 // Shift instructions
12881288 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1289 "shl{b} {%cl, $dst|$dst, %CL}",
1289 "shl{b}\t{%cl, $dst|$dst, %CL}",
12901290 [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>;
12911291 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1292 "shl{w} {%cl, $dst|$dst, %CL}",
1292 "shl{w}\t{%cl, $dst|$dst, %CL}",
12931293 [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
12941294 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1295 "shl{l} {%cl, $dst|$dst, %CL}",
1295 "shl{l}\t{%cl, $dst|$dst, %CL}",
12961296 [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>;
12971297
12981298 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1299 "shl{b} {$src2, $dst|$dst, $src2}",
1299 "shl{b}\t{$src2, $dst|$dst, $src2}",
13001300 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
13011301 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
13021302 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1303 "shl{w} {$src2, $dst|$dst, $src2}",
1303 "shl{w}\t{$src2, $dst|$dst, $src2}",
13041304 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
13051305 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1306 "shl{l} {$src2, $dst|$dst, $src2}",
1306 "shl{l}\t{$src2, $dst|$dst, $src2}",
13071307 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
13081308 }
13091309
13101310 // Shift left by one. Not used because (add x, x) is slightly cheaper.
13111311 def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
1312 "shl{b} $dst", []>;
1312 "shl{b}\t$dst", []>;
13131313 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1314 "shl{w} $dst", []>, OpSize;
1314 "shl{w}\t$dst", []>, OpSize;
13151315 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1316 "shl{l} $dst", []>;
1316 "shl{l}\t$dst", []>;
13171317
13181318 let isTwoAddress = 0 in {
13191319 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1320 "shl{b} {%cl, $dst|$dst, %CL}",
1320 "shl{b}\t{%cl, $dst|$dst, %CL}",
13211321 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
13221322 Imp<[CL],[]>;
13231323 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1324 "shl{w} {%cl, $dst|$dst, %CL}",
1324 "shl{w}\t{%cl, $dst|$dst, %CL}",
13251325 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
13261326 Imp<[CL],[]>, OpSize;
13271327 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1328 "shl{l} {%cl, $dst|$dst, %CL}",
1328 "shl{l}\t{%cl, $dst|$dst, %CL}",
13291329 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
13301330 Imp<[CL],[]>;
13311331 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1332 "shl{b} {$src, $dst|$dst, $src}",
1332 "shl{b}\t{$src, $dst|$dst, $src}",
13331333 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
13341334 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1335 "shl{w} {$src, $dst|$dst, $src}",
1335 "shl{w}\t{$src, $dst|$dst, $src}",
13361336 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
13371337 OpSize;
13381338 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1339 "shl{l} {$src, $dst|$dst, $src}",
1339 "shl{l}\t{$src, $dst|$dst, $src}",
13401340 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
13411341
13421342 // Shift by 1
13431343 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1344 "shl{b} $dst",
1344 "shl{b}\t$dst",
13451345 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
13461346 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1347 "shl{w} $dst",
1347 "shl{w}\t$dst",
13481348 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
13491349 OpSize;
13501350 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1351 "shl{l} $dst",
1351 "shl{l}\t$dst",
13521352 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
13531353 }
13541354
13551355 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1356 "shr{b} {%cl, $dst|$dst, %CL}",
1356 "shr{b}\t{%cl, $dst|$dst, %CL}",
13571357 [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>;
13581358 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1359 "shr{w} {%cl, $dst|$dst, %CL}",
1359 "shr{w}\t{%cl, $dst|$dst, %CL}",
13601360 [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
13611361 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1362 "shr{l} {%cl, $dst|$dst, %CL}",
1362 "shr{l}\t{%cl, $dst|$dst, %CL}",
13631363 [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>;
13641364
13651365 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1366 "shr{b} {$src2, $dst|$dst, $src2}",
1366 "shr{b}\t{$src2, $dst|$dst, $src2}",
13671367 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
13681368 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1369 "shr{w} {$src2, $dst|$dst, $src2}",
1369 "shr{w}\t{$src2, $dst|$dst, $src2}",
13701370 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
13711371 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1372 "shr{l} {$src2, $dst|$dst, $src2}",
1372 "shr{l}\t{$src2, $dst|$dst, $src2}",
13731373 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
13741374
13751375 // Shift by 1
13761376 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1377 "shr{b} $dst",
1377 "shr{b}\t$dst",
13781378 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
13791379 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1380 "shr{w} $dst",
1380 "shr{w}\t$dst",
13811381 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
13821382 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1383 "shr{l} $dst",
1383 "shr{l}\t$dst",
13841384 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
13851385
13861386 let isTwoAddress = 0 in {
13871387 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1388 "shr{b} {%cl, $dst|$dst, %CL}",
1388 "shr{b}\t{%cl, $dst|$dst, %CL}",
13891389 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
13901390 Imp<[CL],[]>;
13911391 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1392 "shr{w} {%cl, $dst|$dst, %CL}",
1392 "shr{w}\t{%cl, $dst|$dst, %CL}",
13931393 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
13941394 Imp<[CL],[]>, OpSize;
13951395 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1396 "shr{l} {%cl, $dst|$dst, %CL}",
1396 "shr{l}\t{%cl, $dst|$dst, %CL}",
13971397 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
13981398 Imp<[CL],[]>;
13991399 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1400 "shr{b} {$src, $dst|$dst, $src}",
1400 "shr{b}\t{$src, $dst|$dst, $src}",
14011401 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
14021402 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1403 "shr{w} {$src, $dst|$dst, $src}",
1403 "shr{w}\t{$src, $dst|$dst, $src}",
14041404 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
14051405 OpSize;
14061406 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1407 "shr{l} {$src, $dst|$dst, $src}",
1407 "shr{l}\t{$src, $dst|$dst, $src}",
14081408 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
14091409
14101410 // Shift by 1
14111411 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1412 "shr{b} $dst",
1412 "shr{b}\t$dst",
14131413 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
14141414 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1415 "shr{w} $dst",
1415 "shr{w}\t$dst",
14161416 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
14171417 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1418 "shr{l} $dst",
1418 "shr{l}\t$dst",
14191419 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
14201420 }
14211421
14221422 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1423 "sar{b} {%cl, $dst|$dst, %CL}",
1423 "sar{b}\t{%cl, $dst|$dst, %CL}",
14241424 [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>;
14251425 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1426 "sar{w} {%cl, $dst|$dst, %CL}",
1426 "sar{w}\t{%cl, $dst|$dst, %CL}",
14271427 [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
14281428 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1429 "sar{l} {%cl, $dst|$dst, %CL}",
1429 "sar{l}\t{%cl, $dst|$dst, %CL}",
14301430 [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>;
14311431
14321432 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1433 "sar{b} {$src2, $dst|$dst, $src2}",
1433 "sar{b}\t{$src2, $dst|$dst, $src2}",
14341434 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
14351435 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1436 "sar{w} {$src2, $dst|$dst, $src2}",
1436 "sar{w}\t{$src2, $dst|$dst, $src2}",
14371437 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
14381438 OpSize;
14391439 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1440 "sar{l} {$src2, $dst|$dst, $src2}",
1440 "sar{l}\t{$src2, $dst|$dst, $src2}",
14411441 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
14421442
14431443 // Shift by 1
14441444 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1445 "sar{b} $dst",
1445 "sar{b}\t$dst",
14461446 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
14471447 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1448 "sar{w} $dst",
1448 "sar{w}\t$dst",
14491449 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
14501450 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1451 "sar{l} $dst",
1451 "sar{l}\t$dst",
14521452 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
14531453
14541454 let isTwoAddress = 0 in {
14551455 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1456 "sar{b} {%cl, $dst|$dst, %CL}",
1456 "sar{b}\t{%cl, $dst|$dst, %CL}",
14571457 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
14581458 Imp<[CL],[]>;
14591459 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1460 "sar{w} {%cl, $dst|$dst, %CL}",
1460 "sar{w}\t{%cl, $dst|$dst, %CL}",
14611461 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
14621462 Imp<[CL],[]>, OpSize;
14631463 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1464 "sar{l} {%cl, $dst|$dst, %CL}",
1464 "sar{l}\t{%cl, $dst|$dst, %CL}",
14651465 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
14661466 Imp<[CL],[]>;
14671467 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1468 "sar{b} {$src, $dst|$dst, $src}",
1468 "sar{b}\t{$src, $dst|$dst, $src}",
14691469 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
14701470 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1471 "sar{w} {$src, $dst|$dst, $src}",
1471 "sar{w}\t{$src, $dst|$dst, $src}",
14721472 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
14731473 OpSize;
14741474 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1475 "sar{l} {$src, $dst|$dst, $src}",
1475 "sar{l}\t{$src, $dst|$dst, $src}",
14761476 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
14771477
14781478 // Shift by 1
14791479 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1480 "sar{b} $dst",
1480 "sar{b}\t$dst",
14811481 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
14821482 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1483 "sar{w} $dst",
1483 "sar{w}\t$dst",
14841484 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
14851485 OpSize;
14861486 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1487 "sar{l} $dst",
1487 "sar{l}\t$dst",
14881488 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
14891489 }
14901490
14911491 // Rotate instructions
14921492 // FIXME: provide shorter instructions when imm8 == 1
14931493 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1494 "rol{b} {%cl, $dst|$dst, %CL}",
1494 "rol{b}\t{%cl, $dst|$dst, %CL}",
14951495 [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>;
14961496 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1497 "rol{w} {%cl, $dst|$dst, %CL}",
1497 "rol{w}\t{%cl, $dst|$dst, %CL}",
14981498 [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
14991499 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1500 "rol{l} {%cl, $dst|$dst, %CL}",
1500 "rol{l}\t{%cl, $dst|$dst, %CL}",
15011501 [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>;
15021502
15031503 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1504 "rol{b} {$src2, $dst|$dst, $src2}",
1504 "rol{b}\t{$src2, $dst|$dst, $src2}",
15051505 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
15061506 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1507 "rol{w} {$src2, $dst|$dst, $src2}",
1507 "rol{w}\t{$src2, $dst|$dst, $src2}",
15081508 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
15091509 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1510 "rol{l} {$src2, $dst|$dst, $src2}",
1510 "rol{l}\t{$src2, $dst|$dst, $src2}",
15111511 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
15121512
15131513 // Rotate by 1
15141514 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1515 "rol{b} $dst",
1515 "rol{b}\t$dst",
15161516 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
15171517 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1518 "rol{w} $dst",
1518 "rol{w}\t$dst",
15191519 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
15201520 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1521 "rol{l} $dst",
1521 "rol{l}\t$dst",
15221522 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
15231523
15241524 let isTwoAddress = 0 in {
15251525 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1526 "rol{b} {%cl, $dst|$dst, %CL}",
1526 "rol{b}\t{%cl, $dst|$dst, %CL}",
15271527 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
15281528 Imp<[CL],[]>;
15291529 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1530 "rol{w} {%cl, $dst|$dst, %CL}",
1530 "rol{w}\t{%cl, $dst|$dst, %CL}",
15311531 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
15321532 Imp<[CL],[]>, OpSize;
15331533 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1534 "rol{l} {%cl, $dst|$dst, %CL}",
1534 "rol{l}\t{%cl, $dst|$dst, %CL}",
15351535 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
15361536 Imp<[CL],[]>;
15371537 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1538 "rol{b} {$src, $dst|$dst, $src}",
1538 "rol{b}\t{$src, $dst|$dst, $src}",
15391539 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
15401540 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1541 "rol{w} {$src, $dst|$dst, $src}",
1541 "rol{w}\t{$src, $dst|$dst, $src}",
15421542 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
15431543 OpSize;
15441544 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1545 "rol{l} {$src, $dst|$dst, $src}",
1545 "rol{l}\t{$src, $dst|$dst, $src}",
15461546 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
15471547
15481548 // Rotate by 1
15491549 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1550 "rol{b} $dst",
1550 "rol{b}\t$dst",
15511551 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
15521552 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1553 "rol{w} $dst",
1553 "rol{w}\t$dst",
15541554 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
15551555 OpSize;
15561556 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1557 "rol{l} $dst",
1557 "rol{l}\t$dst",
15581558 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
15591559 }
15601560
15611561 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1562 "ror{b} {%cl, $dst|$dst, %CL}",
1562 "ror{b}\t{%cl, $dst|$dst, %CL}",
15631563 [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>;
15641564 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1565 "ror{w} {%cl, $dst|$dst, %CL}",
1565 "ror{w}\t{%cl, $dst|$dst, %CL}",
15661566 [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
15671567 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1568 "ror{l} {%cl, $dst|$dst, %CL}",
1568 "ror{l}\t{%cl, $dst|$dst, %CL}",
15691569 [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>;
15701570
15711571 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1572 "ror{b} {$src2, $dst|$dst, $src2}",
1572 "ror{b}\t{$src2, $dst|$dst, $src2}",
15731573 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
15741574 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1575 "ror{w} {$src2, $dst|$dst, $src2}",
1575 "ror{w}\t{$src2, $dst|$dst, $src2}",
15761576 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
15771577 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1578 "ror{l} {$src2, $dst|$dst, $src2}",
1578 "ror{l}\t{$src2, $dst|$dst, $src2}",
15791579 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
15801580
15811581 // Rotate by 1
15821582 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1583 "ror{b} $dst",
1583 "ror{b}\t$dst",
15841584 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
15851585 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1586 "ror{w} $dst",
1586 "ror{w}\t$dst",
15871587 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
15881588 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1589 "ror{l} $dst",
1589 "ror{l}\t$dst",
15901590 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
15911591
15921592 let isTwoAddress = 0 in {
15931593 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1594 "ror{b} {%cl, $dst|$dst, %CL}",
1594 "ror{b}\t{%cl, $dst|$dst, %CL}",
15951595 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
15961596 Imp<[CL],[]>;
15971597 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1598 "ror{w} {%cl, $dst|$dst, %CL}",
1598 "ror{w}\t{%cl, $dst|$dst, %CL}",
15991599 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
16001600 Imp<[CL],[]>, OpSize;
16011601 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1602 "ror{l} {%cl, $dst|$dst, %CL}",
1602 "ror{l}\t{%cl, $dst|$dst, %CL}",
16031603 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
16041604 Imp<[CL],[]>;
16051605 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1606 "ror{b} {$src, $dst|$dst, $src}",
1606 "ror{b}\t{$src, $dst|$dst, $src}",
16071607 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
16081608 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1609 "ror{w} {$src, $dst|$dst, $src}",
1609 "ror{w}\t{$src, $dst|$dst, $src}",
16101610 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
16111611 OpSize;
16121612 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1613 "ror{l} {$src, $dst|$dst, $src}",
1613 "ror{l}\t{$src, $dst|$dst, $src}",
16141614 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
16151615
16161616 // Rotate by 1
16171617 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1618 "ror{b} $dst",
1618 "ror{b}\t$dst",
16191619 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
16201620 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1621 "ror{w} $dst",
1621 "ror{w}\t$dst",
16221622 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
16231623 OpSize;
16241624 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1625 "ror{l} $dst",
1625 "ror{l}\t$dst",
16261626 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
16271627 }
16281628
16301630
16311631 // Double shift instructions (generalizations of rotate)
16321632 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1633 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1633 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16341634 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>,
16351635 Imp<[CL],[]>, TB;
16361636 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1637 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1637 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16381638 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>,
16391639 Imp<[CL],[]>, TB;
16401640 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1641 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1641 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16421642 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
16431643 Imp<[CL],[]>, TB, OpSize;
16441644 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1645 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1645 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16461646 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
16471647 Imp<[CL],[]>, TB, OpSize;
16481648
16491649 let isCommutable = 1 in { // These instructions commute to each other.
16501650 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
16511651 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1652 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1652 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
16531653 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
16541654 (i8 imm:$src3)))]>,
16551655 TB;
16561656 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
16571657 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1658 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1658 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
16591659 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
16601660 (i8 imm:$src3)))]>,
16611661 TB;
16621662 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
16631663 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1664 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1664 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
16651665 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
16661666 (i8 imm:$src3)))]>,
16671667 TB, OpSize;
16681668 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
16691669 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1670 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1670 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
16711671 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
16721672 (i8 imm:$src3)))]>,
16731673 TB, OpSize;
16751675
16761676 let isTwoAddress = 0 in {
16771677 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1678 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1678 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16791679 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
16801680 addr:$dst)]>,
16811681 Imp<[CL],[]>, TB;
16821682 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1683 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1683 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
16841684 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
16851685 addr:$dst)]>,
16861686 Imp<[CL],[]>, TB;
16871687 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
16881688 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1689 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1689 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
16901690 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
16911691 (i8 imm:$src3)), addr:$dst)]>,
16921692 TB;
16931693 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
16941694 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1695 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1695 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
16961696 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
16971697 (i8 imm:$src3)), addr:$dst)]>,
16981698 TB;
16991699
17001700 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1701 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1701 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
17021702 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
17031703 addr:$dst)]>,
17041704 Imp<[CL],[]>, TB, OpSize;
17051705 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1706 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1706 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
17071707 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
17081708 addr:$dst)]>,
17091709 Imp<[CL],[]>, TB, OpSize;
17101710 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
17111711 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1712 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1712 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
17131713 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
17141714 (i8 imm:$src3)), addr:$dst)]>,
17151715 TB, OpSize;
17161716 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
17171717 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1718 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1718 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
17191719 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
17201720 (i8 imm:$src3)), addr:$dst)]>,
17211721 TB, OpSize;
17251725 // Arithmetic.
17261726 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
17271727 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1728 "add{b} {$src2, $dst|$dst, $src2}",
1728 "add{b}\t{$src2, $dst|$dst, $src2}",
17291729 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
17301730 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
17311731 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1732 "add{w} {$src2, $dst|$dst, $src2}",
1732 "add{w}\t{$src2, $dst|$dst, $src2}",
17331733 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
17341734 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1735 "add{l} {$src2, $dst|$dst, $src2}",
1735 "add{l}\t{$src2, $dst|$dst, $src2}",
17361736 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
17371737 } // end isConvertibleToThreeAddress
17381738 } // end isCommutable
17391739 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1740 "add{b} {$src2, $dst|$dst, $src2}",
1740 "add{b}\t{$src2, $dst|$dst, $src2}",
17411741 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
17421742 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1743 "add{w} {$src2, $dst|$dst, $src2}",
1743 "add{w}\t{$src2, $dst|$dst, $src2}",
17441744 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize;
17451745 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1746 "add{l} {$src2, $dst|$dst, $src2}",
1746 "add{l}\t{$src2, $dst|$dst, $src2}",
17471747 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
17481748
17491749 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1750 "add{b} {$src2, $dst|$dst, $src2}",
1750 "add{b}\t{$src2, $dst|$dst, $src2}",
17511751 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
17521752
17531753 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
17541754 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1755 "add{w} {$src2, $dst|$dst, $src2}",
1755 "add{w}\t{$src2, $dst|$dst, $src2}",
17561756 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
17571757 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1758 "add{l} {$src2, $dst|$dst, $src2}",
1758 "add{l}\t{$src2, $dst|$dst, $src2}",
17591759 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
17601760 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1761 "add{w} {$src2, $dst|$dst, $src2}",
1761 "add{w}\t{$src2, $dst|$dst, $src2}",
17621762 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>,
17631763 OpSize;
17641764 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1765 "add{l} {$src2, $dst|$dst, $src2}",
1765 "add{l}\t{$src2, $dst|$dst, $src2}",
17661766 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
17671767 }
17681768
17691769 let isTwoAddress = 0 in {
17701770 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1771 "add{b} {$src2, $dst|$dst, $src2}",
1771 "add{b}\t{$src2, $dst|$dst, $src2}",
17721772 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
17731773 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1774 "add{w} {$src2, $dst|$dst, $src2}",
1774 "add{w}\t{$src2, $dst|$dst, $src2}",
17751775 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
17761776 OpSize;
17771777 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1778 "add{l} {$src2, $dst|$dst, $src2}",
1778 "add{l}\t{$src2, $dst|$dst, $src2}",
17791779 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
17801780 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1781 "add{b} {$src2, $dst|$dst, $src2}",
1781 "add{b}\t{$src2, $dst|$dst, $src2}",
17821782 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
17831783 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1784 "add{w} {$src2, $dst|$dst, $src2}",
1784 "add{w}\t{$src2, $dst|$dst, $src2}",
17851785 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
17861786 OpSize;
17871787 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1788 "add{l} {$src2, $dst|$dst, $src2}",
1788 "add{l}\t{$src2, $dst|$dst, $src2}",
17891789 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
17901790 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1791 "add{w} {$src2, $dst|$dst, $src2}",
1791 "add{w}\t{$src2, $dst|$dst, $src2}",
17921792 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
17931793 OpSize;
17941794 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1795 "add{l} {$src2, $dst|$dst, $src2}",
1795 "add{l}\t{$src2, $dst|$dst, $src2}",
17961796 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
17971797 }
17981798
17991799 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
18001800 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1801 "adc{l} {$src2, $dst|$dst, $src2}",
1801 "adc{l}\t{$src2, $dst|$dst, $src2}",
18021802 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
18031803 }
18041804 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1805 "adc{l} {$src2, $dst|$dst, $src2}",
1805 "adc{l}\t{$src2, $dst|$dst, $src2}",
18061806 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
18071807 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1808 "adc{l} {$src2, $dst|$dst, $src2}",
1808 "adc{l}\t{$src2, $dst|$dst, $src2}",
18091809 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
18101810 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1811 "adc{l} {$src2, $dst|$dst, $src2}",
1811 "adc{l}\t{$src2, $dst|$dst, $src2}",
18121812 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
18131813
18141814 let isTwoAddress = 0 in {
18151815 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1816 "adc{l} {$src2, $dst|$dst, $src2}",
1816 "adc{l}\t{$src2, $dst|$dst, $src2}",
18171817 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
18181818 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1819 "adc{l} {$src2, $dst|$dst, $src2}",
1819 "adc{l}\t{$src2, $dst|$dst, $src2}",
18201820 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
18211821 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1822 "adc{l} {$src2, $dst|$dst, $src2}",
1822 "adc{l}\t{$src2, $dst|$dst, $src2}",
18231823 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
18241824 }
18251825
18261826 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1827 "sub{b} {$src2, $dst|$dst, $src2}",
1827 "sub{b}\t{$src2, $dst|$dst, $src2}",
18281828 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
18291829 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1830 "sub{w} {$src2, $dst|$dst, $src2}",
1830 "sub{w}\t{$src2, $dst|$dst, $src2}",
18311831 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
18321832 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1833 "sub{l} {$src2, $dst|$dst, $src2}",
1833 "sub{l}\t{$src2, $dst|$dst, $src2}",
18341834 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
18351835 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1836 "sub{b} {$src2, $dst|$dst, $src2}",
1836 "sub{b}\t{$src2, $dst|$dst, $src2}",
18371837 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
18381838 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1839 "sub{w} {$src2, $dst|$dst, $src2}",
1839 "sub{w}\t{$src2, $dst|$dst, $src2}",
18401840 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
18411841 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1842 "sub{l} {$src2, $dst|$dst, $src2}",
1842 "sub{l}\t{$src2, $dst|$dst, $src2}",
18431843 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
18441844
18451845 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1846 "sub{b} {$src2, $dst|$dst, $src2}",
1846 "sub{b}\t{$src2, $dst|$dst, $src2}",
18471847 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
18481848 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1849 "sub{w} {$src2, $dst|$dst, $src2}",
1849 "sub{w}\t{$src2, $dst|$dst, $src2}",
18501850 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
18511851 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1852 "sub{l} {$src2, $dst|$dst, $src2}",
1852 "sub{l}\t{$src2, $dst|$dst, $src2}",
18531853 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
18541854 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1855 "sub{w} {$src2, $dst|$dst, $src2}",
1855 "sub{w}\t{$src2, $dst|$dst, $src2}",
18561856 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
18571857 OpSize;
18581858 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1859 "sub{l} {$src2, $dst|$dst, $src2}",
1859 "sub{l}\t{$src2, $dst|$dst, $src2}",
18601860 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
18611861 let isTwoAddress = 0 in {
18621862 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1863 "sub{b} {$src2, $dst|$dst, $src2}",
1863 "sub{b}\t{$src2, $dst|$dst, $src2}",
18641864 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
18651865 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1866 "sub{w} {$src2, $dst|$dst, $src2}",
1866 "sub{w}\t{$src2, $dst|$dst, $src2}",
18671867 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
18681868 OpSize;
18691869 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1870 "sub{l} {$src2, $dst|$dst, $src2}",
1870 "sub{l}\t{$src2, $dst|$dst, $src2}",
18711871 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
18721872 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1873 "sub{b} {$src2, $dst|$dst, $src2}",
1873 "sub{b}\t{$src2, $dst|$dst, $src2}",
18741874 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
18751875 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1876 "sub{w} {$src2, $dst|$dst, $src2}",
1876 "sub{w}\t{$src2, $dst|$dst, $src2}",
18771877 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
18781878 OpSize;
18791879 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1880 "sub{l} {$src2, $dst|$dst, $src2}",
1880 "sub{l}\t{$src2, $dst|$dst, $src2}",
18811881 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
18821882 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1883 "sub{w} {$src2, $dst|$dst, $src2}",
1883 "sub{w}\t{$src2, $dst|$dst, $src2}",
18841884 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
18851885 OpSize;
18861886 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1887 "sub{l} {$src2, $dst|$dst, $src2}",
1887 "sub{l}\t{$src2, $dst|$dst, $src2}",
18881888 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
18891889 }
18901890
18911891 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1892 "sbb{l} {$src2, $dst|$dst, $src2}",
1892 "sbb{l}\t{$src2, $dst|$dst, $src2}",
18931893 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
18941894
18951895 let isTwoAddress = 0 in {
18961896 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1897 "sbb{l} {$src2, $dst|$dst, $src2}",
1897 "sbb{l}\t{$src2, $dst|$dst, $src2}",
18981898 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
18991899 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1900 "sbb{b} {$src2, $dst|$dst, $src2}",
1900 "sbb{b}\t{$src2, $dst|$dst, $src2}",
19011901 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
19021902 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1903 "sbb{l} {$src2, $dst|$dst, $src2}",
1903 "sbb{l}\t{$src2, $dst|$dst, $src2}",
19041904 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
19051905 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1906 "sbb{l} {$src2, $dst|$dst, $src2}",
1906 "sbb{l}\t{$src2, $dst|$dst, $src2}",
19071907 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
19081908 }
19091909 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1910 "sbb{l} {$src2, $dst|$dst, $src2}",
1910 "sbb{l}\t{$src2, $dst|$dst, $src2}",
19111911 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
19121912 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1913 "sbb{l} {$src2, $dst|$dst, $src2}",
1913 "sbb{l}\t{$src2, $dst|$dst, $src2}",
19141914 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
19151915 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1916 "sbb{l} {$src2, $dst|$dst, $src2}",
1916 "sbb{l}\t{$src2, $dst|$dst, $src2}",
19171917 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
19181918
19191919 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
19201920 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1921 "imul{w} {$src2, $dst|$dst, $src2}",
1921 "imul{w}\t{$src2, $dst|$dst, $src2}",
19221922 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
19231923 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1924 "imul{l} {$src2, $dst|$dst, $src2}",
1924 "imul{l}\t{$src2, $dst|$dst, $src2}",
19251925 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
19261926 }
19271927 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1928 "imul{w} {$src2, $dst|$dst, $src2}",
1928 "imul{w}\t{$src2, $dst|$dst, $src2}",
19291929 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
19301930 TB, OpSize;
19311931 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1932 "imul{l} {$src2, $dst|$dst, $src2}",
1932 "imul{l}\t{$src2, $dst|$dst, $src2}",
19331933 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
19341934
19351935 } // end Two Address instructions
19371937 // Suprisingly enough, these are not two address instructions!
19381938 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
19391939 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1940 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
1940 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19411941 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
19421942 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
19431943 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1944 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
1944 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19451945 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
19461946 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
19471947 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1948 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
1948 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19491949 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
19501950 OpSize;
19511951 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
19521952 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1953 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
1953 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19541954 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
19551955
19561956 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
19571957 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
1958 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
1958 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19591959 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
19601960 OpSize;
19611961 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
19621962 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
1963 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
1963 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19641964 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
19651965 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
19661966 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
1967 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
1967 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19681968 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
19691969 OpSize;
19701970 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
19711971 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
1972 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
1972 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19731973 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
19741974
19751975 //===----------------------------------------------------------------------===//
19771977 //
19781978 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
19791979 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
1980 "test{b} {$src2, $src1|$src1, $src2}",
1980 "test{b}\t{$src2, $src1|$src1, $src2}",
19811981 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
19821982 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1983 "test{w} {$src2, $src1|$src1, $src2}",
1983 "test{w}\t{$src2, $src1|$src1, $src2}",
19841984 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
19851985 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1986 "test{l} {$src2, $src1|$src1, $src2}",
1986 "test{l}\t{$src2, $src1|$src1, $src2}",
19871987 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
19881988 }
19891989
19901990 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
1991 "test{b} {$src2, $src1|$src1, $src2}",
1991 "test{b}\t{$src2, $src1|$src1, $src2}",
19921992 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
19931993 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
1994 "test{w} {$src2, $src1|$src1, $src2}",
1994 "test{w}\t{$src2, $src1|$src1, $src2}",
19951995 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
19961996 OpSize;
19971997 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
1998 "test{l} {$src2, $src1|$src1, $src2}",
1998 "test{l}\t{$src2, $src1|$src1, $src2}",
19991999 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
20002000
20012001 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
20022002 (outs), (ins GR8:$src1, i8imm:$src2),
2003 "test{b} {$src2, $src1|$src1, $src2}",
2003 "test{b}\t{$src2, $src1|$src1, $src2}",
20042004 [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
20052005 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
20062006 (outs), (ins GR16:$src1, i16imm:$src2),
2007 "test{w} {$src2, $src1|$src1, $src2}",
2007 "test{w}\t{$src2, $src1|$src1, $src2}",
20082008 [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
20092009 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
20102010 (outs), (ins GR32:$src1, i32imm:$src2),
2011 "test{l} {$src2, $src1|$src1, $src2}",
2011 "test{l}\t{$src2, $src1|$src1, $src2}",
20122012 [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
20132013
20142014 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
20152015 (outs), (ins i8mem:$src1, i8imm:$src2),
2016 "test{b} {$src2, $src1|$src1, $src2}",
2016 "test{b}\t{$src2, $src1|$src1, $src2}",
20172017 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
20182018 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
20192019 (outs), (ins i16mem:$src1, i16imm:$src2),
2020 "test{w} {$src2, $src1|$src1, $src2}",
2020 "test{w}\t{$src2, $src1|$src1, $src2}",
20212021 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
20222022 OpSize;
20232023 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
20242024 (outs), (ins i32mem:$src1, i32imm:$src2),
2025 "test{l} {$src2, $src1|$src1, $src2}",
2025 "test{l}\t{$src2, $src1|$src1, $src2}",
20262026 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
20272027
20282028
20322032
20332033 def SETEr : I<0x94, MRM0r,
20342034 (outs GR8 :$dst), (ins),
2035 "sete $dst",
2035 "sete\t$dst",
20362036 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
20372037 TB; // GR8 = ==
20382038 def SETEm : I<0x94, MRM0m,
20392039 (outs), (ins i8mem:$dst),
2040 "sete $dst",
2040 "sete\t$dst",
20412041 [(store (X86setcc X86_COND_E), addr:$dst)]>,
20422042 TB; // [mem8] = ==
20432043 def SETNEr : I<0x95, MRM0r,
20442044 (outs GR8 :$dst), (ins),
2045 "setne $dst",
2045 "setne\t$dst",
20462046 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
20472047 TB; // GR8 = !=
20482048 def SETNEm : I<0x95, MRM0m,
20492049 (outs), (ins i8mem:$dst),
2050 "setne $dst",
2050 "setne\t$dst",
20512051 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
20522052 TB; // [mem8] = !=
20532053 def SETLr : I<0x9C, MRM0r,
20542054 (outs GR8 :$dst), (ins),
2055 "setl $dst",
2055 "setl\t$dst",
20562056 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
20572057 TB; // GR8 = < signed
20582058 def SETLm : I<0x9C, MRM0m,
20592059 (outs), (ins i8mem:$dst),
2060 "setl $dst",
2060 "setl\t$dst",
20612061 [(store (X86setcc X86_COND_L), addr:$dst)]>,
20622062 TB; // [mem8] = < signed
20632063 def SETGEr : I<0x9D, MRM0r,
20642064 (outs GR8 :$dst), (ins),
2065 "setge $dst",
2065 "setge\t$dst",
20662066 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
20672067 TB; // GR8 = >= signed
20682068 def SETGEm : I<0x9D, MRM0m,
20692069 (outs), (ins i8mem:$dst),
2070 "setge $dst",
2070 "setge\t$dst",
20712071 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
20722072 TB; // [mem8] = >= signed
20732073 def SETLEr : I<0x9E, MRM0r,
20742074 (outs GR8 :$dst), (ins),
2075 "setle $dst",
2075 "setle\t$dst",
20762076 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
20772077 TB; // GR8 = <= signed
20782078 def SETLEm : I<0x9E, MRM0m,
20792079 (outs), (ins i8mem:$dst),
2080 "setle $dst",
2080 "setle\t$dst",
20812081 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
20822082 TB; // [mem8] = <= signed
20832083 def SETGr : I<0x9F, MRM0r,
20842084 (outs GR8 :$dst), (ins),
2085 "setg $dst",
2085 "setg\t$dst",
20862086 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
20872087 TB; // GR8 = > signed
20882088 def SETGm : I<0x9F, MRM0m,
20892089 (outs), (ins i8mem:$dst),
2090 "setg $dst",
2090 "setg\t$dst",
20912091 [(store (X86setcc X86_COND_G), addr:$dst)]>,
20922092 TB; // [mem8] = > signed
20932093
20942094 def SETBr : I<0x92, MRM0r,
20952095 (outs GR8 :$dst), (ins),
2096 "setb $dst",
2096 "setb\t$dst",
20972097 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
20982098 TB; // GR8 = < unsign
20992099 def SETBm : I<0x92, MRM0m,
21002100 (outs), (ins i8mem:$dst),
2101 "setb $dst",
2101 "setb\t$dst",
21022102 [(store (X86setcc X86_COND_B), addr:$dst)]>,
21032103 TB; // [mem8] = < unsign
21042104 def SETAEr : I<0x93, MRM0r,
21052105 (outs GR8 :$dst), (ins),
2106 "setae $dst",
2106 "setae\t$dst",
21072107 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
21082108 TB; // GR8 = >= unsign
21092109 def SETAEm : I<0x93, MRM0m,
21102110 (outs), (ins i8mem:$dst),
2111 "setae $dst",
2111 "setae\t$dst",
21122112 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
21132113 TB; // [mem8] = >= unsign
21142114 def SETBEr : I<0x96, MRM0r,
21152115 (outs GR8 :$dst), (ins),
2116 "setbe $dst",
2116 "setbe\t$dst",
21172117 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
21182118 TB; // GR8 = <= unsign
21192119 def SETBEm : I<0x96, MRM0m,
21202120 (outs), (ins i8mem:$dst),
2121 "setbe $dst",
2121 "setbe\t$dst",
21222122 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
21232123 TB; // [mem8] = <= unsign
21242124 def SETAr : I<0x97, MRM0r,
21252125 (outs GR8 :$dst), (ins),
2126 "seta $dst",
2126 "seta\t$dst",
21272127 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
21282128 TB; // GR8 = > signed
21292129 def SETAm : I<0x97, MRM0m,
21302130 (outs), (ins i8mem:$dst),
2131 "seta $dst",
2131 "seta\t$dst",
21322132 [(store (X86setcc X86_COND_A), addr:$dst)]>,
21332133 TB; // [mem8] = > signed
21342134
21352135 def SETSr : I<0x98, MRM0r,
21362136 (outs GR8 :$dst), (ins),
2137 "sets $dst",
2137 "sets\t$dst",
21382138 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
21392139 TB; // GR8 =
21402140 def SETSm : I<0x98, MRM0m,
21412141 (outs), (ins i8mem:$dst),
2142 "sets $dst",
2142 "sets\t$dst",
21432143 [(store (X86setcc X86_COND_S), addr:$dst)]>,
21442144 TB; // [mem8] =
21452145 def SETNSr : I<0x99, MRM0r,
21462146 (outs GR8 :$dst), (ins),
2147 "setns $dst",
2147 "setns\t$dst",
21482148 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
21492149 TB; // GR8 = !
21502150 def SETNSm : I<0x99, MRM0m,
21512151 (outs), (ins i8mem:$dst),
2152 "setns $dst",
2152 "setns\t$dst",
21532153 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
21542154 TB; // [mem8] = !
21552155 def SETPr : I<0x9A, MRM0r,
21562156 (outs GR8 :$dst), (ins),
2157 "setp $dst",
2157 "setp\t$dst",
21582158 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
21592159 TB; // GR8 = parity
21602160 def SETPm : I<0x9A, MRM0m,
21612161 (outs), (ins i8mem:$dst),
2162 "setp $dst",
2162 "setp\t$dst",
21632163 [(store (X86setcc X86_COND_P), addr:$dst)]>,
21642164 TB; // [mem8] = parity
21652165 def SETNPr : I<0x9B, MRM0r,
21662166 (outs GR8 :$dst), (ins),
2167 "setnp $dst",
2167 "setnp\t$dst",
21682168 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
21692169 TB; // GR8 = not parity
21702170 def SETNPm : I<0x9B, MRM0m,
21712171 (outs), (ins i8mem:$dst),
2172 "setnp $dst",
2172 "setnp\t$dst",
21732173 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
21742174 TB; // [mem8] = not parity
21752175
21762176 // Integer comparisons
21772177 def CMP8rr : I<0x38, MRMDestReg,
21782178 (outs), (ins GR8 :$src1, GR8 :$src2),
2179 "cmp{b} {$src2, $src1|$src1, $src2}",
2179 "cmp{b}\t{$src2, $src1|$src1, $src2}",
21802180 [(X86cmp GR8:$src1, GR8:$src2)]>;
21812181 def CMP16rr : I<0x39, MRMDestReg,
21822182 (outs), (ins GR16:$src1, GR16:$src2),
2183 "cmp{w} {$src2, $src1|$src1, $src2}",
2183 "cmp{w}\t{$src2, $src1|$src1, $src2}",
21842184 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
21852185 def CMP32rr : I<0x39, MRMDestReg,
21862186 (outs), (ins GR32:$src1, GR32:$src2),
2187 "cmp{l} {$src2, $src1|$src1, $src2}",
2187 "cmp{l}\t{$src2, $src1|$src1, $src2}",
21882188 [(X86cmp GR32:$src1, GR32:$src2)]>;
21892189 def CMP8mr : I<0x38, MRMDestMem,
21902190 (outs), (ins i8mem :$src1, GR8 :$src2),
2191 "cmp{b} {$src2, $src1|$src1, $src2}",
2191 "cmp{b}\t{$src2, $src1|$src1, $src2}",
21922192 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
21932193 def CMP16mr : I<0x39, MRMDestMem,
21942194 (outs), (ins i16mem:$src1, GR16:$src2),
2195 "cmp{w} {$src2, $src1|$src1, $src2}",
2195 "cmp{w}\t{$src2, $src1|$src1, $src2}",
21962196 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
21972197 def CMP32mr : I<0x39, MRMDestMem,
21982198 (outs), (ins i32mem:$src1, GR32:$src2),
2199 "cmp{l} {$src2, $src1|$src1, $src2}",
2199 "cmp{l}\t{$src2, $src1|$src1, $src2}",
22002200 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
22012201 def CMP8rm : I<0x3A, MRMSrcMem,
22022202 (outs), (ins GR8 :$src1, i8mem :$src2),
2203 "cmp{b} {$src2, $src1|$src1, $src2}",
2203 "cmp{b}\t{$src2, $src1|$src1, $src2}",
22042204 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
22052205 def CMP16rm : I<0x3B, MRMSrcMem,
22062206 (outs), (ins GR16:$src1, i16mem:$src2),
2207 "cmp{w} {$src2, $src1|$src1, $src2}",
2207 "cmp{w}\t{$src2, $src1|$src1, $src2}",
22082208 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
22092209 def CMP32rm : I<0x3B, MRMSrcMem,
22102210 (outs), (ins GR32:$src1, i32mem:$src2),
2211 "cmp{l} {$src2, $src1|$src1, $src2}",
2211 "cmp{l}\t{$src2, $src1|$src1, $src2}",
22122212 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
22132213 def CMP8ri : Ii8<0x80, MRM7r,
22142214 (outs), (ins GR8:$src1, i8imm:$src2),
2215 "cmp{b} {$src2, $src1|$src1, $src2}",
2215 "cmp{b}\t{$src2, $src1|$src1, $src2}",
22162216 [(X86cmp GR8:$src1, imm:$src2)]>;
22172217 def CMP16ri : Ii16<0x81, MRM7r,
22182218 (outs), (ins GR16:$src1, i16imm:$src2),
2219 "cmp{w} {$src2, $src1|$src1, $src2}",
2219 "cmp{w}\t{$src2, $src1|$src1, $src2}",
22202220 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
22212221 def CMP32ri : Ii32<0x81, MRM7r,
22222222 (outs), (ins GR32:$src1, i32imm:$src2),
2223 "cmp{l} {$src2, $src1|$src1, $src2}",
2223 "cmp{l}\t{$src2, $src1|$src1, $src2}",
22242224 [(X86cmp GR32:$src1, imm:$src2)]>;
22252225 def CMP8mi : Ii8 <0x80, MRM7m,
22262226 (outs), (ins i8mem :$src1, i8imm :$src2),
2227 "cmp{b} {$src2, $src1|$src1, $src2}",
2227 "cmp{b}\t{$src2, $src1|$src1, $src2}",
22282228 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
22292229 def CMP16mi : Ii16<0x81, MRM7m,
22302230 (outs), (ins i16mem:$src1, i16imm:$src2),
2231 "cmp{w} {$src2, $src1|$src1, $src2}",
2231 "cmp{w}\t{$src2, $src1|$src1, $src2}",
22322232 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
22332233 def CMP32mi : Ii32<0x81, MRM7m,
22342234 (outs), (ins i32mem:$src1, i32imm:$src2),
2235 "cmp{l} {$src2, $src1|$src1, $src2}",
2235 "cmp{l}\t{$src2, $src1|$src1, $src2}",
22362236 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
22372237 def CMP16ri8 : Ii8<0x83, MRM7r,
22382238 (outs), (ins GR16:$src1, i16i8imm:$src2),
2239 "cmp{w} {$src2, $src1|$src1, $src2}",
2239 "cmp{w}\t{$src2, $src1|$src1, $src2}",
22402240 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
22412241 def CMP16mi8 : Ii8<0x83, MRM7m,
22422242 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2243 "cmp{w} {$src2, $src1|$src1, $src2}",
2243 "cmp{w}\t{$src2, $src1|$src1, $src2}",
22442244 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
22452245 def CMP32mi8 : Ii8<0x83, MRM7m,
22462246 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2247 "cmp{l} {$src2, $src1|$src1, $src2}",
2247 "cmp{l}\t{$src2, $src1|$src1, $src2}",
22482248 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
22492249 def CMP32ri8 : Ii8<0x83, MRM7r,
22502250 (outs), (ins GR32:$src1, i32i8imm:$src2),
2251 "cmp{l} {$src2, $src1|$src1, $src2}",
2251 "cmp{l}\t{$src2, $src1|$src1, $src2}",
22522252 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
22532253
22542254 // Sign/Zero extenders
22552255 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2256 "movs{bw|x} {$src, $dst|$dst, $src}",
2256 "movs{bw|x}\t{$src, $dst|$dst, $src}",
22572257 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
22582258 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2259 "movs{bw|x} {$src, $dst|$dst, $src}",
2259 "movs{bw|x}\t{$src, $dst|$dst, $src}",
22602260 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
22612261 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2262 "movs{bl|x} {$src, $dst|$dst, $src}",
2262 "movs{bl|x}\t{$src, $dst|$dst, $src}",
22632263 [(set GR32:$dst, (sext GR8:$src))]>, TB;
22642264 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2265 "movs{bl|x} {$src, $dst|$dst, $src}",
2265 "movs{bl|x}\t{$src, $dst|$dst, $src}",
22662266 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
22672267 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2268 "movs{wl|x} {$src, $dst|$dst, $src}",
2268 "movs{wl|x}\t{$src, $dst|$dst, $src}",
22692269 [(set GR32:$dst, (sext GR16:$src))]>, TB;
22702270 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2271 "movs{wl|x} {$src, $dst|$dst, $src}",
2271 "movs{wl|x}\t{$src, $dst|$dst, $src}",
22722272 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
22732273
22742274 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2275 "movz{bw|x} {$src, $dst|$dst, $src}",
2275 "movz{bw|x}\t{$src, $dst|$dst, $src}",
22762276 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
22772277 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2278 "movz{bw|x} {$src, $dst|$dst, $src}",
2278 "movz{bw|x}\t{$src, $dst|$dst, $src}",
22792279 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
22802280 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2281 "movz{bl|x} {$src, $dst|$dst, $src}",
2281 "movz{bl|x}\t{$src, $dst|$dst, $src}",
22822282 [(set GR32:$dst, (zext GR8:$src))]>, TB;
22832283 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2284 "movz{bl|x} {$src, $dst|$dst, $src}",
2284 "movz{bl|x}\t{$src, $dst|$dst, $src}",
22852285 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
22862286 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2287 "movz{wl|x} {$src, $dst|$dst, $src}",
2287 "movz{wl|x}\t{$src, $dst|$dst, $src}",
22882288 [(set GR32:$dst, (zext GR16:$src))]>, TB;
22892289 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2290 "movz{wl|x} {$src, $dst|$dst, $src}",
2290 "movz{wl|x}\t{$src, $dst|$dst, $src}",
22912291 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
22922292
22932293 def CBW : I<0x98, RawFrm, (outs), (ins),
23082308 // Alias instructions that map movr0 to xor.
23092309 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
23102310 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2311 "xor{b} $dst, $dst",
2311 "xor{b}\t$dst, $dst",
23122312 [(set GR8:$dst, 0)]>;
23132313 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2314 "xor{w} $dst, $dst",
2314 "xor{w}\t$dst, $dst",
23152315 [(set GR16:$dst, 0)]>, OpSize;
23162316 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2317 "xor{l} $dst, $dst",
2317 "xor{l}\t$dst, $dst",
23182318 [(set GR32:$dst, 0)]>;
23192319
23202320 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
23212321 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
23222322 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2323 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2323 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
23242324 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2325 "mov{l} {$src, $dst|$dst, $src}", []>;
2325 "mov{l}\t{$src, $dst|$dst, $src}", []>;
23262326
23272327 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2328 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2328 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
23292329 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2330 "mov{l} {$src, $dst|$dst, $src}", []>;
2330 "mov{l}\t{$src, $dst|$dst, $src}", []>;
23312331 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2332 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2332 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
23332333 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2334 "mov{l} {$src, $dst|$dst, $src}", []>;
2334 "mov{l}\t{$src, $dst|$dst, $src}", []>;
23352335 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2336 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2336 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
23372337 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2338 "mov{l} {$src, $dst|$dst, $src}", []>;
2338 "mov{l}\t{$src, $dst|$dst, $src}", []>;
23392339
23402340 //===----------------------------------------------------------------------===//
23412341 // Thread Local Storage Instructions
23422342 //
23432343
23442344 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2345 "leal ${sym:mem}(,%ebx,1), $dst",
2345 "leal\t${sym:mem}(,%ebx,1), $dst",
23462346 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>,
23472347 Imp<[EBX],[]>;
23482348
23492349 let AddedComplexity = 10 in
23502350 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2351 "movl %gs:($src), $dst",
2351 "movl\t%gs:($src), $dst",
23522352 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
23532353
23542354 let AddedComplexity = 15 in
23552355 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2356 "movl %gs:${src:mem}, $dst",
2356 "movl\t%gs:${src:mem}, $dst",
23572357 [(set GR32:$dst,
23582358 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
23592359
23602360 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2361 "movl %gs:0, $dst",
2361 "movl\t%gs:0, $dst",
23622362 [(set GR32:$dst, X86TLStp)]>;
23632363
23642364 //===----------------------------------------------------------------------===//
23772377 let isTerminator = 1, isReturn = 1, isBarrier = 1,
23782378 hasCtrlDep = 1 in {
23792379 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2380 "ret #eh_return, addr: $addr",
2380 "ret\t#eh_return, addr: $addr",
23812381 [(X86ehret GR32:$addr)]>;
23822382
23832383 }
8484 multiclass MMXI_binop_rm opc, string OpcodeStr, SDNode OpNode,
8585 ValueType OpVT, bit Commutable = 0> {
8686 def rr : MMXI
87 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
8888 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
8989 let isCommutable = Commutable;
9090 }
9191 def rm : MMXI
92 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
9393 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
9494 (bitconvert
9595 (load_mmx addr:$src2)))))]>;
9898 multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId,
9999 bit Commutable = 0> {
100100 def rr : MMXI
101 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
101 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
102102 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
103103 let isCommutable = Commutable;
104104 }
105105 def rm : MMXI
106 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
106 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
107107 [(set VR64:$dst, (IntId VR64:$src1,
108108 (bitconvert (load_mmx addr:$src2))))]>;
109109 }
116116 multiclass MMXI_binop_rm_v1i64 opc, string OpcodeStr, SDNode OpNode,
117117 bit Commutable = 0> {
118118 def rr : MMXI
119 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
119 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
120120 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
121121 let isCommutable = Commutable;
122122 }
123123 def rm : MMXI
124 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
124 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
125125 [(set VR64:$dst,
126126 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
127127 }
129129 multiclass MMXI_binop_rmi_int opc, bits<8> opc2, Format ImmForm,
130130 string OpcodeStr, Intrinsic IntId> {
131131 def rr : MMXI
132 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
132 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
133133 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
134134 def rm : MMXI
135 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
135 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
136136 [(set VR64:$dst, (IntId VR64:$src1,
137137 (bitconvert (load_mmx addr:$src2))))]>;
138138 def ri : MMXIi8
139 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
139 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
140140 [(set VR64:$dst, (IntId VR64:$src1,
141141 (scalar_to_vector (i32 imm:$src2))))]>;
142142 }
155155
156156 // Data Transfer Instructions
157157 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
158 "movd {$src, $dst|$dst, $src}", []>;
158 "movd\t{$src, $dst|$dst, $src}", []>;
159159 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
160 "movd {$src, $dst|$dst, $src}", []>;
160 "movd\t{$src, $dst|$dst, $src}", []>;
161161 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
162 "movd {$src, $dst|$dst, $src}", []>;
162 "movd\t{$src, $dst|$dst, $src}", []>;
163163
164164 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
165 "movd {$src, $dst|$dst, $src}", []>;
165 "movd\t{$src, $dst|$dst, $src}", []>;
166166
167167 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
168 "movq {$src, $dst|$dst, $src}", []>;
168 "movq\t{$src, $dst|$dst, $src}", []>;
169169 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
170 "movq {$src, $dst|$dst, $src}",
170 "movq\t{$src, $dst|$dst, $src}",
171171 [(set VR64:$dst, (load_mmx addr:$src))]>;
172172 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
173 "movq {$src, $dst|$dst, $src}",
173 "movq\t{$src, $dst|$dst, $src}",
174174 [(store (v1i64 VR64:$src), addr:$dst)]>;
175175
176176 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
177 "movdq2q {$src, $dst|$dst, $src}",
177 "movdq2q\t{$src, $dst|$dst, $src}",
178178 [(set VR64:$dst,
179179 (v1i64 (vector_extract (v2i64 VR128:$src),
180180 (iPTR 0))))]>;
181181
182182 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
183 "movq2dq {$src, $dst|$dst, $src}",
183 "movq2dq\t{$src, $dst|$dst, $src}",
184184 [(set VR128:$dst,
185185 (bitconvert (v1i64 VR64:$src)))]>;
186186
187187 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
188 "movntq {$src, $dst|$dst, $src}",
188 "movntq\t{$src, $dst|$dst, $src}",
189189 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
190190
191191 let AddedComplexity = 15 in
192192 // movd to MMX register zero-extends
193193 def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
194 "movd {$src, $dst|$dst, $src}",
194 "movd\t{$src, $dst|$dst, $src}",
195195 [(set VR64:$dst,
196196 (v2i32 (vector_shuffle immAllZerosV,
197197 (v2i32 (scalar_to_vector GR32:$src)),
198198 MMX_MOVL_shuffle_mask)))]>;
199199 let AddedComplexity = 20 in
200200 def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
201 "movd {$src, $dst|$dst, $src}",
201 "movd\t{$src, $dst|$dst, $src}",
202202 [(set VR64:$dst,
203203 (v2i32 (vector_shuffle immAllZerosV,
204204 (v2i32 (scalar_to_vector
260260 let isTwoAddress = 1 in {
261261 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
262262 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
263 "pandn {$src2, $dst|$dst, $src2}",
263 "pandn\t{$src2, $dst|$dst, $src2}",
264264 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
265265 VR64:$src2)))]>;
266266 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
267267 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
268 "pandn {$src2, $dst|$dst, $src2}",
268 "pandn\t{$src2, $dst|$dst, $src2}",
269269 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
270270 (load addr:$src2))))]>;
271271 }
306306 // Unpack High Packed Data Instructions
307307 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
308308 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
309 "punpckhbw {$src2, $dst|$dst, $src2}",
309 "punpckhbw\t{$src2, $dst|$dst, $src2}",
310310 [(set VR64:$dst,
311311 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
312312 MMX_UNPCKH_shuffle_mask)))]>;
313313 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
314314 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
315 "punpckhbw {$src2, $dst|$dst, $src2}",
315 "punpckhbw\t{$src2, $dst|$dst, $src2}",
316316 [(set VR64:$dst,
317317 (v8i8 (vector_shuffle VR64:$src1,
318318 (bc_v8i8 (load_mmx addr:$src2)),
320320
321321 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
322322 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
323 "punpckhwd {$src2, $dst|$dst, $src2}",
323 "punpckhwd\t{$src2, $dst|$dst, $src2}",
324324 [(set VR64:$dst,
325325 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
326326 MMX_UNPCKH_shuffle_mask)))]>;
327327 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
328328 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
329 "punpckhwd {$src2, $dst|$dst, $src2}",
329 "punpckhwd\t{$src2, $dst|$dst, $src2}",
330330 [(set VR64:$dst,
331331 (v4i16 (vector_shuffle VR64:$src1,
332332 (bc_v4i16 (load_mmx addr:$src2)),
334334
335335 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
336336 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
337 "punpckhdq {$src2, $dst|$dst, $src2}",
337 "punpckhdq\t{$src2, $dst|$dst, $src2}",
338338 [(set VR64:$dst,
339339 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
340340 MMX_UNPCKH_shuffle_mask)))]>;
341341 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
342342 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
343 "punpckhdq {$src2, $dst|$dst, $src2}",
343 "punpckhdq\t{$src2, $dst|$dst, $src2}",
344344 [(set VR64:$dst,
345345 (v2i32 (vector_shuffle VR64:$src1,
346346 (bc_v2i32 (load_mmx addr:$src2)),
349349 // Unpack Low Packed Data Instructions
350350 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
351351 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
352 "punpcklbw {$src2, $dst|$dst, $src2}",
352 "punpcklbw\t{$src2, $dst|$dst, $src2}",
353353 [(set VR64:$dst,
354354 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
355355 MMX_UNPCKL_shuffle_mask)))]>;
356356 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
357357 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
358 "punpcklbw {$src2, $dst|$dst, $src2}",
358 "punpcklbw\t{$src2, $dst|$dst, $src2}",
359359 [(set VR64:$dst,
360360 (v8i8 (vector_shuffle VR64:$src1,
361361<