llvm.org GIT mirror llvm / b140713
[X86] Rename matchBitOpReduction to matchScalarReduction. NFCI. This doesn't need to be just for bitops, but the ops do need to be fully associative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375445 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 1 month ago
1 changed file(s) with 4 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
1989019890
1989119891 /// Helper for matching OR(EXTRACTELT(X,0),OR(EXTRACTELT(X,1),...))
1989219892 /// style scalarized (associative) reduction patterns.
19893 static bool matchBitOpReduction(SDValue Op, ISD::NodeType BinOp,
19894 SmallVectorImpl &SrcOps) {
19893 static bool matchScalarReduction(SDValue Op, ISD::NodeType BinOp,
19894 SmallVectorImpl &SrcOps) {
1989519895 SmallVector Opnds;
1989619896 DenseMap SrcOpMap;
1989719897 EVT VT = MVT::Other;
1996419964 return SDValue();
1996519965
1996619966 SmallVector VecIns;
19967 if (!matchBitOpReduction(Op, ISD::OR, VecIns))
19967 if (!matchScalarReduction(Op, ISD::OR, VecIns))
1996819968 return SDValue();
1996919969
1997019970 // Quit if not 128/256-bit vector.
3912839128 // TODO: Support multiple SrcOps.
3912939129 if (VT == MVT::i1) {
3913039130 SmallVector SrcOps;
39131 if (matchBitOpReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
39131 if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps) &&
3913239132 SrcOps.size() == 1) {
3913339133 SDLoc dl(N);
3913439134 unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();