llvm.org GIT mirror llvm / b13ddb1
Don't pass Reloc::Model to places that already have it. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274022 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 4 years ago
8 changed file(s) with 31 addition(s) and 36 deletion(s). Raw diff Collapse all Expand all
12751275
12761276 bool
12771277 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1278 MachineFunction &MF = *MI->getParent()->getParent();
1279 Reloc::Model RM = MF.getTarget().getRelocationModel();
1280
12811278 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
12821279 assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
12831280 "LOAD_STACK_GUARD currently supported only for MachO.");
1284 expandLoadStackGuard(MI, RM);
1281 expandLoadStackGuard(MI);
12851282 MI->getParent()->erase(MI);
12861283 return true;
12871284 }
41094106 // sequence is needed for other targets.
41104107 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
41114108 unsigned LoadImmOpc,
4112 unsigned LoadOpc,
4113 Reloc::Model RM) const {
4109 unsigned LoadOpc) const {
41144110 MachineBasicBlock &MBB = *MI->getParent();
4111 const TargetMachine &TM = MBB.getParent()->getTarget();
4112 Reloc::Model RM = TM.getRelocationModel();
41154113 DebugLoc DL = MI->getDebugLoc();
41164114 unsigned Reg = MI->getOperand(0).getReg();
41174115 const GlobalValue *GV =
3535 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
3636
3737 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
38 unsigned LoadImmOpc, unsigned LoadOpc,
39 Reloc::Model RM) const;
38 unsigned LoadImmOpc, unsigned LoadOpc) const;
4039
4140 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
4241 /// and \p DefIdx.
348347 bool verifyInstruction(const MachineInstr *MI,
349348 StringRef &ErrInfo) const override;
350349
351 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI,
352 Reloc::Model RM) const = 0;
350 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
353351
354352 void expandMEMCPY(MachineBasicBlock::iterator) const;
355353
8989 return 0;
9090 }
9191
92 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
93 Reloc::Model RM) const {
92 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI) const {
9493 MachineFunction &MF = *MI->getParent()->getParent();
9594 const ARMSubtarget &Subtarget = MF.getSubtarget();
95 const TargetMachine &TM = MF.getTarget();
96 Reloc::Model RM = TM.getRelocationModel();
9697
9798 if (!Subtarget.useMovt(MF)) {
98 if (RM == Reloc::PIC_)
99 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12, RM);
99 if (TM.isPositionIndependent())
100 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12);
100101 else
101 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12, RM);
102 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12);
102103 return;
103104 }
104105
105 if (RM != Reloc::PIC_) {
106 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12, RM);
106 if (!TM.isPositionIndependent()) {
107 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12);
107108 return;
108109 }
109110
111112 cast((*MI->memoperands_begin())->getValue());
112113
113114 if (!Subtarget.GVIsIndirectSymbol(GV, RM)) {
114 expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12, RM);
115 expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12);
115116 return;
116117 }
117118
3838 const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
3939
4040 private:
41 void expandLoadStackGuard(MachineBasicBlock::iterator MI,
42 Reloc::Model RM) const override;
41 void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
4342 };
4443
4544 }
117117 }
118118 }
119119
120 void
121 Thumb1InstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
122 Reloc::Model RM) const {
123 if (RM == Reloc::PIC_)
124 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi, RM);
120 void Thumb1InstrInfo::expandLoadStackGuard(
121 MachineBasicBlock::iterator MI) const {
122 MachineFunction &MF = *MI->getParent()->getParent();
123 const TargetMachine &TM = MF.getTarget();
124 if (TM.isPositionIndependent())
125 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi);
125126 else
126 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi, RM);
127 expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);
127128 }
5353 const TargetRegisterInfo *TRI) const override;
5454
5555 private:
56 void expandLoadStackGuard(MachineBasicBlock::iterator MI,
57 Reloc::Model RM) const override;
56 void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
5857 };
5958 }
6059
208208 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
209209 }
210210
211 void
212 Thumb2InstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
213 Reloc::Model RM) const {
214 if (RM == Reloc::PIC_)
215 expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12, RM);
211 void Thumb2InstrInfo::expandLoadStackGuard(
212 MachineBasicBlock::iterator MI) const {
213 MachineFunction &MF = *MI->getParent()->getParent();
214 if (MF.getTarget().isPositionIndependent())
215 expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
216216 else
217 expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12, RM);
217 expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
218218 }
219219
220220 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
6161 const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
6262
6363 private:
64 void expandLoadStackGuard(MachineBasicBlock::iterator MI,
65 Reloc::Model RM) const override;
64 void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
6665 };
6766
6867 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical