llvm.org GIT mirror llvm / b123fd0
[X86][Haswell] Updating HSW instruction scheduling information This patch completely replaces the instruction scheduling information for the Haswell architecture target by modifying the file X86SchedHaswell.td located under the X86 Target. We used the scheduling information retrieved from the Haswell architects in order to replace and modify the existing scheduling. The patch continues the scheduling replacement effort started with the SNB target in r307529 and r310792. Information includes latency, number of micro-Ops and used ports by each HSW instruction. Please expect some performance fluctuations due to code alignment effects. Reviewers: RKSimon, zvi, aymanmus, craig.topper, m_zuckerman, igorb, dim, chandlerc, aaboud Differential Revision: https://reviews.llvm.org/D36663 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311879 91177308-0d34-0410-b5e6-96231b3b80d8 Gadi Haber 2 years ago
40 changed file(s) with 34777 addition(s) and 33749 deletion(s). Raw diff Collapse all Expand all
2222 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
2323 let LoopMicroOpBufferSize = 50;
2424
25 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
26 // the scheduler to assign a default model to unrecognized opcodes.
25 // This flag is set to allow the scheduler to assign a default model to
26 // unrecognized opcodes.
2727 let CompleteModel = 0;
2828 }
2929
435435 // r,m.
436436 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
437437
438 // CMOVcc.
439 // r,r.
440 def : InstRW<[Write2P0156_Lat2],
441 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
442 // r,m.
443 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd],
444 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
445
446 // XCHG.
447 // r,r.
448 def WriteXCHG : SchedWriteRes<[HWPort0156]> {
449 let Latency = 2;
450 let ResourceCycles = [3];
451 }
452
453 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
454
455 // r,m.
456 def WriteXCHGrm : SchedWriteRes<[]> {
457 let Latency = 21;
458 let NumMicroOps = 8;
459 }
460 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
461
462438 // XLAT.
463439 def WriteXLAT : SchedWriteRes<[]> {
464440 let Latency = 7;
470446 // m.
471447 def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
472448
473 // PUSHF.
474 def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> {
475 let NumMicroOps = 4;
476 }
477 def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>;
478
479449 // PUSHA.
480450 def WritePushA : SchedWriteRes<[]> {
481451 let NumMicroOps = 19;
486456 // m.
487457 def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
488458
489 // POPF.
490 def WritePopF : SchedWriteRes<[]> {
491 let NumMicroOps = 9;
492 }
493 def : InstRW<[WritePopF], (instregex "POPF(16|32)")>;
494
495459 // POPA.
496460 def WritePopA : SchedWriteRes<[]> {
497461 let NumMicroOps = 18;
498462 }
499463 def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
500464
501 // LAHF SAHF.
502 def : InstRW<[WriteP06], (instregex "(S|L)AHF")>;
503
504 // BSWAP.
505 // r32.
506 def WriteBSwap32 : SchedWriteRes<[HWPort15]>;
507 def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>;
508
509 // r64.
510 def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> {
511 let NumMicroOps = 2;
512 }
513 def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>;
514
515 // MOVBE.
516 // r16,m16 / r64,m64.
517 def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>;
518
519 // r32, m32.
520 def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> {
521 let NumMicroOps = 2;
522 }
523 def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>;
524
525 // m16,r16.
526 def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
527 let NumMicroOps = 3;
528 }
529 def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>;
530
531 // m32,r32.
532 def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> {
533 let NumMicroOps = 3;
534 }
535 def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>;
536
537 // m64,r64.
538 def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
539 let NumMicroOps = 4;
540 }
541 def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;
542
543465 //-- Arithmetic instructions --//
544
545 // ADD SUB.
546 // m,r/i.
547 def : InstRW<[Write2P0156_2P237_P4],
548 (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
549 "(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>;
550
551 // ADC SBB.
552 // r,r/i.
553 def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
554 "(ADC|SBB)(16|32|64)ri8",
555 "(ADC|SBB)64ri32",
556 "(ADC|SBB)(8|16|32|64)rr_REV")>;
557
558 // r,m.
559 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
560
561 // m,r/i.
562 def : InstRW<[Write3P0156_2P237_P4],
563 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
564 "(ADC|SBB)(16|32|64)mi8",
565 "(ADC|SBB)64mi32")>;
566
567 // INC DEC NOT NEG.
568 // m.
569 def : InstRW<[WriteP0156_2P237_P4],
570 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
571 "(INC|DEC)64(16|32)m")>;
572
573 // MUL IMUL.
574 // r16.
575 def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> {
576 let Latency = 4;
577 let NumMicroOps = 4;
578 }
579 def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
580
581 // m16.
582 def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
583 let Latency = 8;
584 let NumMicroOps = 5;
585 }
586 def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>;
587
588 // r32.
589 def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> {
590 let Latency = 4;
591 let NumMicroOps = 3;
592 }
593 def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
594
595 // m32.
596 def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
597 let Latency = 8;
598 let NumMicroOps = 4;
599 }
600 def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>;
601
602 // r64.
603 def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> {
604 let Latency = 3;
605 let NumMicroOps = 2;
606 }
607 def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
608
609 // m64.
610 def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
611 let Latency = 7;
612 let NumMicroOps = 3;
613 }
614 def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>;
615
616 // r16,r16.
617 def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> {
618 let Latency = 4;
619 let NumMicroOps = 2;
620 }
621 def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
622
623 // r16,m16.
624 def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
625 let Latency = 8;
626 let NumMicroOps = 3;
627 }
628 def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>;
629
630 // MULX.
631 // r32,r32,r32.
632 def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> {
633 let Latency = 4;
634 let NumMicroOps = 3;
635 let ResourceCycles = [1, 2];
636 }
637 def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
638
639 // r32,r32,m32.
640 def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> {
641 let Latency = 8;
642 let NumMicroOps = 4;
643 let ResourceCycles = [1, 2, 1];
644 }
645 def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>;
646
647 // r64,r64,r64.
648 def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> {
649 let Latency = 4;
650 let NumMicroOps = 2;
651 }
652 def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
653
654 // r64,r64,m64.
655 def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
656 let Latency = 8;
657 let NumMicroOps = 3;
658 }
659 def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>;
660466
661467 // DIV.
662468 // r8.
666472 }
667473 def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
668474
669 // r16.
670 def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
671 let Latency = 23;
672 let NumMicroOps = 10;
673 }
674 def : InstRW<[WriteDiv16], (instregex "DIV16r")>;
675
676 // r32.
677 def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
678 let Latency = 22;
679 let NumMicroOps = 10;
680 }
681 def : InstRW<[WriteDiv32], (instregex "DIV32r")>;
682
683 // r64.
684 def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
685 let Latency = 32;
686 let NumMicroOps = 36;
687 }
688 def : InstRW<[WriteDiv64], (instregex "DIV64r")>;
689
690475 // IDIV.
691476 // r8.
692477 def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
695480 }
696481 def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
697482
698 // r16.
699 def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
700 let Latency = 23;
701 let NumMicroOps = 10;
702 }
703 def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>;
704
705 // r32.
706 def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
707 let Latency = 22;
708 let NumMicroOps = 9;
709 }
710 def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>;
711
712 // r64.
713 def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
714 let Latency = 39;
715 let NumMicroOps = 59;
716 }
717 def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>;
718
719 //-- Logic instructions --//
720
721 // AND OR XOR.
722 // m,r/i.
723 def : InstRW<[Write2P0156_2P237_P4],
724 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
725 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
726
727 // SHR SHL SAR.
728 // m,i.
729 def WriteShiftRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
730 let NumMicroOps = 4;
731 let ResourceCycles = [2, 1, 1];
732 }
733 def : InstRW<[WriteShiftRMW], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
734
735 // r,cl.
736 def : InstRW<[Write3P06_Lat2], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>;
737
738 // m,cl.
739 def WriteShiftClLdRMW : SchedWriteRes<[HWPort06, HWPort23, HWPort4]> {
740 let NumMicroOps = 6;
741 let ResourceCycles = [3, 2, 1];
742 }
743 def : InstRW<[WriteShiftClLdRMW], (instregex "S(A|H)(R|L)(8|16|32|64)mCL")>;
744
745 // ROR ROL.
746 // r,1.
747 def : InstRW<[Write2P06], (instregex "RO(R|L)(8|16|32|64)r1")>;
748
749 // m,i.
750 def WriteRotateRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
751 let NumMicroOps = 5;
752 let ResourceCycles = [2, 2, 1];
753 }
754 def : InstRW<[WriteRotateRMW], (instregex "RO(R|L)(8|16|32|64)mi")>;
755
756 // r,cl.
757 def : InstRW<[Write3P06_Lat2], (instregex "RO(R|L)(8|16|32|64)rCL")>;
758
759 // m,cl.
760 def WriteRotateRMWCL : SchedWriteRes<[]> {
761 let NumMicroOps = 6;
762 }
763 def : InstRW<[WriteRotateRMWCL], (instregex "RO(R|L)(8|16|32|64)mCL")>;
764
765 // RCR RCL.
766 // r,1.
767 def WriteRCr1 : SchedWriteRes<[HWPort06, HWPort0156]> {
768 let Latency = 2;
769 let NumMicroOps = 3;
770 let ResourceCycles = [2, 1];
771 }
772 def : InstRW<[WriteRCr1], (instregex "RC(R|L)(8|16|32|64)r1")>;
773
774 // m,1.
775 def WriteRCm1 : SchedWriteRes<[]> {
776 let NumMicroOps = 6;
777 }
778 def : InstRW<[WriteRCm1], (instregex "RC(R|L)(8|16|32|64)m1")>;
779
780 // r,i.
781 def WriteRCri : SchedWriteRes<[HWPort0156]> {
782 let Latency = 6;
783 let NumMicroOps = 8;
784 }
785 def : InstRW<[WriteRCri], (instregex "RC(R|L)(8|16|32|64)r(i|CL)")>;
786
787 // m,i.
788 def WriteRCmi : SchedWriteRes<[]> {
789 let NumMicroOps = 11;
790 }
791 def : InstRW<[WriteRCmi], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>;
792
793 // SHRD SHLD.
794 // r,r,i.
795 def WriteShDrr : SchedWriteRes<[HWPort1]> {
796 let Latency = 3;
797 }
798 def : InstRW<[WriteShDrr], (instregex "SH(R|L)D(16|32|64)rri8")>;
799
800 // m,r,i.
801 def WriteShDmr : SchedWriteRes<[]> {
802 let NumMicroOps = 5;
803 }
804 def : InstRW<[WriteShDmr], (instregex "SH(R|L)D(16|32|64)mri8")>;
805
806 // r,r,cl.
807 def WriteShlDCL : SchedWriteRes<[HWPort0156]> {
808 let Latency = 3;
809 let NumMicroOps = 4;
810 }
811 def : InstRW<[WriteShlDCL], (instregex "SHLD(16|32|64)rrCL")>;
812
813 // r,r,cl.
814 def WriteShrDCL : SchedWriteRes<[HWPort0156]> {
815 let Latency = 4;
816 let NumMicroOps = 4;
817 }
818 def : InstRW<[WriteShrDCL], (instregex "SHRD(16|32|64)rrCL")>;
819
820 // m,r,cl.
821 def WriteShDmrCL : SchedWriteRes<[]> {
822 let NumMicroOps = 7;
823 }
824 def : InstRW<[WriteShDmrCL], (instregex "SH(R|L)D(16|32|64)mrCL")>;
825
826483 // BT.
827 // r,r/i.
828 def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>;
829
830484 // m,r.
831485 def WriteBTmr : SchedWriteRes<[]> {
832486 let NumMicroOps = 10;
833487 }
834488 def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
835489
836 // m,i.
837 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
838
839490 // BTR BTS BTC.
840 // r,r,i.
841 def : InstRW<[WriteShift], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
842
843491 // m,r.
844492 def WriteBTRSCmr : SchedWriteRes<[]> {
845493 let NumMicroOps = 11;
846494 }
847495 def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
848496
849 // m,i.
850 def : InstRW<[WriteShiftLd], (instregex "BT(R|S|C)(16|32|64)mi8")>;
851
852 // BSF BSR.
853 // r,r.
854 def : InstRW<[WriteP1_Lat3], (instregex "BS(R|F)(16|32|64)rr")>;
855 // r,m.
856 def : InstRW<[WriteP1_Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>;
857
858 // SETcc.
859 // r.
860 def : InstRW<[WriteShift],
861 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
862 // m.
863 def WriteSetCCm : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
864 let NumMicroOps = 3;
865 }
866 def : InstRW<[WriteSetCCm],
867 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>;
868
869 // CLD STD.
870 def WriteCldStd : SchedWriteRes<[HWPort15, HWPort6]> {
871 let NumMicroOps = 3;
872 }
873 def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>;
874
875 // LZCNT TZCNT.
876 // r,r.
877 def : InstRW<[WriteP1_Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>;
878 // r,m.
879 def : InstRW<[WriteP1_Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>;
880
881 // ANDN.
882 // r,r.
883 def : InstRW<[WriteP15], (instregex "ANDN(32|64)rr")>;
884 // r,m.
885 def : InstRW<[WriteP15Ld], (instregex "ANDN(32|64)rm")>;
886
887 // BLSI BLSMSK BLSR.
888 // r,r.
889 def : InstRW<[WriteP15], (instregex "BLS(I|MSK|R)(32|64)rr")>;
890 // r,m.
891 def : InstRW<[WriteP15Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>;
892
893 // BEXTR.
894 // r,r,r.
895 def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>;
896 // r,m,r.
897 def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>;
898
899 // BZHI.
900 // r,r,r.
901 def : InstRW<[WriteP15], (instregex "BZHI(32|64)rr")>;
902 // r,m,r.
903 def : InstRW<[WriteP15Ld], (instregex "BZHI(32|64)rm")>;
904
905 // PDEP PEXT.
906 // r,r,r.
907 def : InstRW<[WriteP1_Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
908 // r,m,r.
909 def : InstRW<[WriteP1_Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
910
911497 //-- Control transfer instructions --//
912498
913 // J(E|R)CXZ.
914 def WriteJCXZ : SchedWriteRes<[HWPort0156, HWPort6]> {
915 let NumMicroOps = 2;
916 }
917 def : InstRW<[WriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>;
918
919 // LOOP.
920 def WriteLOOP : SchedWriteRes<[]> {
921 let NumMicroOps = 7;
922 }
923 def : InstRW<[WriteLOOP], (instregex "LOOP")>;
924
925 // LOOP(N)E
926 def WriteLOOPE : SchedWriteRes<[]> {
927 let NumMicroOps = 11;
928 }
929 def : InstRW<[WriteLOOPE], (instregex "LOOPE", "LOOPNE")>;
930
931499 // CALL.
932 // r.
933 def WriteCALLr : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
934 let NumMicroOps = 3;
935 }
936 def : InstRW<[WriteCALLr], (instregex "CALL(16|32)r")>;
937
938 // m.
939 def WriteCALLm : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
940 let NumMicroOps = 4;
941 let ResourceCycles = [2, 1, 1];
942 }
943 def : InstRW<[WriteCALLm], (instregex "CALL(16|32)m")>;
944
945 // RET.
946 def WriteRET : SchedWriteRes<[HWPort237, HWPort6]> {
947 let NumMicroOps = 2;
948 }
949 def : InstRW<[WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)")>;
950
951500 // i.
952501 def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
953502 let NumMicroOps = 4;
975524
976525 // LODSD/Q.
977526 def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>;
978
979 // STOS.
980 def WriteSTOS : SchedWriteRes<[HWPort23, HWPort0156, HWPort4]> {
981 let NumMicroOps = 3;
982 }
983 def : InstRW<[WriteSTOS], (instregex "STOS(B|L|Q|W)")>;
984527
985528 // MOVS.
986529 def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
1001544 }
1002545 def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
1003546
1004 //-- Synchronization instructions --//
1005
1006 // XADD.
1007 def WriteXADD : SchedWriteRes<[]> {
1008 let NumMicroOps = 5;
1009 }
1010 def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
1011
1012 // CMPXCHG.
1013 def WriteCMPXCHG : SchedWriteRes<[]> {
1014 let NumMicroOps = 6;
1015 }
1016 def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
1017
1018 // CMPXCHG8B.
1019 def WriteCMPXCHG8B : SchedWriteRes<[]> {
1020 let NumMicroOps = 15;
1021 }
1022 def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>;
1023
1024 // CMPXCHG16B.
1025 def WriteCMPXCHG16B : SchedWriteRes<[]> {
1026 let NumMicroOps = 22;
1027 }
1028 def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
1029
1030547 //-- Other --//
1031548
1032 // PAUSE.
1033 def WritePAUSE : SchedWriteRes<[HWPort05, HWPort6]> {
1034 let NumMicroOps = 5;
1035 let ResourceCycles = [1, 3];
1036 }
1037 def : InstRW<[WritePAUSE], (instregex "PAUSE")>;
1038
1039 // LEAVE.
1040 def : InstRW<[Write2P0156_P23], (instregex "LEAVE")>;
1041
1042 // XGETBV.
1043 def WriteXGETBV : SchedWriteRes<[]> {
1044 let NumMicroOps = 8;
1045 }
1046 def : InstRW<[WriteXGETBV], (instregex "XGETBV")>;
1047
1048 // RDTSC.
1049 def WriteRDTSC : SchedWriteRes<[]> {
1050 let NumMicroOps = 15;
1051 }
1052 def : InstRW<[WriteRDTSC], (instregex "RDTSC")>;
1053
1054 // RDPMC.
549 // RDPMC.f
1055550 def WriteRDPMC : SchedWriteRes<[]> {
1056551 let NumMicroOps = 34;
1057552 }
1070565 // FLD.
1071566 // m80.
1072567 def : InstRW<[WriteP01], (instregex "LD_Frr")>;
1073
1074 def WriteLD_F80m : SchedWriteRes<[HWPort01, HWPort23]> {
1075 let Latency = 4;
1076 let NumMicroOps = 4;
1077 let ResourceCycles = [2, 2];
1078 }
1079 def : InstRW<[WriteLD_F80m], (instregex "LD_F80m")>;
1080568
1081569 // FBLD.
1082570 // m80.
1090578 // r.
1091579 def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>;
1092580
1093 // m80.
1094 def WriteST_FP80m : SchedWriteRes<[HWPort0156, HWPort23, HWPort4]> {
1095 let NumMicroOps = 7;
1096 let ResourceCycles = [3, 2, 2];
1097 }
1098 def : InstRW<[WriteST_FP80m], (instregex "ST_FP80m")>;
1099
1100 // FBSTP.
1101 // m80.
1102 def WriteFBSTP : SchedWriteRes<[]> {
1103 let NumMicroOps = 226;
1104 }
1105 def : InstRW<[WriteFBSTP], (instregex "FBSTPm")>;
1106
1107 // FXCHG.
1108 def : InstRW<[WriteNop], (instregex "XCH_F")>;
1109
1110 // FILD.
1111 def WriteFILD : SchedWriteRes<[HWPort01, HWPort23]> {
1112 let Latency = 6;
1113 let NumMicroOps = 2;
1114 }
1115 def : InstRW<[WriteFILD], (instregex "ILD_F(16|32|64)m")>;
1116
1117 // FIST(P) FISTTP.
1118 def WriteFIST : SchedWriteRes<[HWPort1, HWPort23, HWPort4]> {
1119 let Latency = 7;
1120 let NumMicroOps = 3;
1121 }
1122 def : InstRW<[WriteFIST], (instregex "IST_(F|FP)(16|32)m")>;
1123
1124581 // FLDZ.
1125582 def : InstRW<[WriteP01], (instregex "LD_F0")>;
1126583
1127 // FLD1.
1128 def : InstRW<[Write2P01], (instregex "LD_F1")>;
1129
1130584 // FLDPI FLDL2E etc.
1131585 def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)" "FLDL(G|N)2")>;
1132
1133 // FCMOVcc.
1134 def WriteFCMOVcc : SchedWriteRes<[HWPort0, HWPort5]> {
1135 let Latency = 2;
1136 let NumMicroOps = 3;
1137 let ResourceCycles = [2, 1];
1138 }
1139 def : InstRW<[WriteFCMOVcc], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>;
1140
1141 // FNSTSW.
1142 // AX.
1143 def WriteFNSTSW : SchedWriteRes<[HWPort0, HWPort0156]> {
1144 let NumMicroOps = 2;
1145 }
1146 def : InstRW<[WriteFNSTSW], (instregex "FNSTSW16r")>;
1147
1148 // m16.
1149 def WriteFNSTSWm : SchedWriteRes<[HWPort0, HWPort4, HWPort237]> {
1150 let Latency = 6;
1151 let NumMicroOps = 3;
1152 }
1153 def : InstRW<[WriteFNSTSWm], (instregex "FNSTSWm")>;
1154
1155 // FLDCW.
1156 def WriteFLDCW : SchedWriteRes<[HWPort01, HWPort23, HWPort6]> {
1157 let Latency = 7;
1158 let NumMicroOps = 3;
1159 }
1160 def : InstRW<[WriteFLDCW], (instregex "FLDCW16m")>;
1161
1162 // FNSTCW.
1163 def WriteFNSTCW : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
1164 let NumMicroOps = 3;
1165 }
1166 def : InstRW<[WriteFNSTCW], (instregex "FNSTCW16m")>;
1167
1168 // FINCSTP FDECSTP.
1169 def : InstRW<[WriteP01], (instregex "FINCSTP", "FDECSTP")>;
1170586
1171587 // FFREE.
1172588 def : InstRW<[WriteP01], (instregex "FFREE")>;
1190606
1191607 // FCHS.
1192608 def : InstRW<[WriteP0], (instregex "CHS_F")>;
1193
1194 // FCOM(P) FUCOM(P).
1195 // r.
1196 def : InstRW<[WriteP1], (instregex "COM_FST0r", "COMP_FST0r", "UCOM_Fr",
1197 "UCOM_FPr")>;
1198 // m.
1199 def : InstRW<[WriteP1_P23], (instregex "FCOM(32|64)m", "FCOMP(32|64)m")>;
1200609
1201610 // FCOMPP FUCOMPP.
1202611 // r.
1207616 def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
1208617 "UCOM_FIPr")>;
1209618
1210 // FICOM(P).
1211 def : InstRW<[Write2P1_P23], (instregex "FICOM(16|32)m", "FICOMP(16|32)m")>;
1212
1213619 // FTST.
1214620 def : InstRW<[WriteP1], (instregex "TST_F")>;
1215621
1271677 def : InstRW<[WriteFNINIT], (instregex "FNINIT")>;
1272678
1273679 //=== Integer MMX and XMM Instructions ===//
1274 //-- Move instructions --//
1275
1276 // MOVD.
1277 // r32/64 <- (x)mm.
1278 def : InstRW<[WriteP0], (instregex "MMX_MOVD64grr", "MMX_MOVD64from64rr",
1279 "VMOVPDI2DIrr", "MOVPDI2DIrr")>;
1280
1281 // (x)mm <- r32/64.
1282 def : InstRW<[WriteP5], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr",
1283 "VMOVDI2PDIrr", "MOVDI2PDIrr")>;
1284
1285 // MOVQ.
1286 // r64 <- (x)mm.
1287 def : InstRW<[WriteP0], (instregex "VMOVPQIto64rr")>;
1288
1289 // (x)mm <- r64.
1290 def : InstRW<[WriteP5], (instregex "VMOV64toPQIrr", "VMOVZQI2PQIrr")>;
1291
1292 // (x)mm <- (x)mm.
1293 def : InstRW<[WriteP015], (instregex "MMX_MOVQ64rr")>;
1294
1295 // (V)MOVDQA/U.
1296 // x <- x.
1297 def : InstRW<[WriteP015], (instregex "MOVDQ(A|U)rr", "VMOVDQ(A|U)rr",
1298 "MOVDQ(A|U)rr_REV", "VMOVDQ(A|U)rr_REV",
1299 "VMOVDQ(A|U)Yrr", "VMOVDQ(A|U)Yrr_REV")>;
1300
1301 // MOVDQ2Q.
1302 def : InstRW<[WriteP01_P5], (instregex "MMX_MOVDQ2Qrr")>;
1303
1304 // MOVQ2DQ.
1305 def : InstRW<[WriteP015], (instregex "MMX_MOVQ2DQrr")>;
1306
1307
1308 // PACKSSWB/DW.
1309 // mm <- mm.
1310 def WriteMMXPACKSSrr : SchedWriteRes<[HWPort5]> {
1311 let Latency = 2;
1312 let NumMicroOps = 3;
1313 let ResourceCycles = [3];
1314 }
1315 def : InstRW<[WriteMMXPACKSSrr], (instregex "MMX_PACKSSDWirr",
1316 "MMX_PACKSSWBirr", "MMX_PACKUSWBirr")>;
1317
1318 // mm <- m64.
1319 def WriteMMXPACKSSrm : SchedWriteRes<[HWPort23, HWPort5]> {
1320 let Latency = 4;
1321 let NumMicroOps = 3;
1322 let ResourceCycles = [1, 3];
1323 }
1324 def : InstRW<[WriteMMXPACKSSrm], (instregex "MMX_PACKSSDWirm",
1325 "MMX_PACKSSWBirm", "MMX_PACKUSWBirm")>;
1326
1327 // VPMOVSX/ZX BW BD BQ DW DQ.
1328 // y <- x.
1329 def WriteVPMOVSX : SchedWriteRes<[HWPort5]> {
1330 let Latency = 3;
1331 let NumMicroOps = 1;
1332 }
1333 def : InstRW<[WriteVPMOVSX], (instregex "VPMOV(SX|ZX)(BW|BQ|DW|DQ)Yrr")>;
1334680
1335681 // PBLENDW.
1336682 // x,x,i / v,v,v,i
1345691 }
1346692 def : InstRW<[WritePBLENDWm, ReadAfterLd], (instregex "(V?)PBLENDW(Y?)rmi")>;
1347693
1348 // VPBLENDD.
1349 // v,v,v,i.
1350 def WriteVPBLENDDr : SchedWriteRes<[HWPort015]>;
1351 def : InstRW<[WriteVPBLENDDr], (instregex "VPBLENDD(Y?)rri")>;
1352
1353 // v,v,m,i
1354 def WriteVPBLENDDm : SchedWriteRes<[HWPort015, HWPort23]> {
1355 let NumMicroOps = 2;
1356 let Latency = 4;
1357 let ResourceCycles = [1, 1];
1358 }
1359 def : InstRW<[WriteVPBLENDDm, ReadAfterLd], (instregex "VPBLENDD(Y?)rmi")>;
1360
1361 // MASKMOVQ.
1362 def WriteMASKMOVQ : SchedWriteRes<[HWPort0, HWPort4, HWPort23]> {
1363 let Latency = 13;
1364 let NumMicroOps = 4;
1365 let ResourceCycles = [1, 1, 2];
1366 }
1367 def : InstRW<[WriteMASKMOVQ], (instregex "MMX_MASKMOVQ(64)?")>;
1368
1369 // MASKMOVDQU.
1370 def WriteMASKMOVDQU : SchedWriteRes<[HWPort04, HWPort56, HWPort23]> {
1371 let Latency = 14;
1372 let NumMicroOps = 10;
1373 let ResourceCycles = [4, 2, 4];
1374 }
1375 def : InstRW<[WriteMASKMOVDQU], (instregex "(V?)MASKMOVDQU(64)?")>;
1376
1377 // VPMASKMOV D/Q.
1378 // v,v,m.
1379 def WriteVPMASKMOVr : SchedWriteRes<[HWPort5, HWPort23]> {
1380 let Latency = 4;
1381 let NumMicroOps = 3;
1382 let ResourceCycles = [2, 1];
1383 }
1384 def : InstRW<[WriteVPMASKMOVr, ReadAfterLd],
1385 (instregex "VPMASKMOV(D|Q)(Y?)rm")>;
1386
1387 // m, v,v.
1388 def WriteVPMASKMOVm : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1389 let Latency = 13;
1390 let NumMicroOps = 4;
1391 let ResourceCycles = [1, 1, 1, 1];
1392 }
1393 def : InstRW<[WriteVPMASKMOVm], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
1394
1395694 // PMOVMSKB.
1396695 def WritePMOVMSKB : SchedWriteRes<[HWPort0]> {
1397696 let Latency = 3;
1398697 }
1399698 def : InstRW<[WritePMOVMSKB], (instregex "(V|MMX_)?PMOVMSKB(Y?)rr")>;
1400
1401 // PEXTR B/W/D/Q.
1402 // r32,x,i.
1403 def WritePEXTRr : SchedWriteRes<[HWPort0, HWPort5]> {
1404 let Latency = 2;
1405 let NumMicroOps = 2;
1406 let ResourceCycles = [1, 1];
1407 }
1408 def : InstRW<[WritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWirri")>;
1409
1410 // m8,x,i.
1411 def WritePEXTRm : SchedWriteRes<[HWPort23, HWPort4, HWPort5]> {
1412 let NumMicroOps = 3;
1413 let ResourceCycles = [1, 1, 1];
1414 }
1415 def : InstRW<[WritePEXTRm], (instregex "PEXTR(B|W|D|Q)mr")>;
1416
1417 // VPBROADCAST B/W.
1418 // x, m8/16.
1419 def WriteVPBROADCAST128Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
1420 let Latency = 5;
1421 let NumMicroOps = 3;
1422 let ResourceCycles = [1, 1, 1];
1423 }
1424 def : InstRW<[WriteVPBROADCAST128Ld, ReadAfterLd],
1425 (instregex "VPBROADCAST(B|W)rm")>;
1426
1427 // y, m8/16
1428 def WriteVPBROADCAST256Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
1429 let Latency = 7;
1430 let NumMicroOps = 3;
1431 let ResourceCycles = [1, 1, 1];
1432 }
1433 def : InstRW<[WriteVPBROADCAST256Ld, ReadAfterLd],
1434 (instregex "VPBROADCAST(B|W)Yrm")>;
1435699
1436700 // VPGATHERDD.
1437701 // x.
1520784 let ResourceCycles = [1, 2, 1];
1521785 }
1522786
1523 // PHADD|PHSUB (S) W/D.
1524 // v <- v,v.
1525 def WritePHADDSUBr : SchedWriteRes<[HWPort1, HWPort5]> {
1526 let Latency = 3;
1527 let NumMicroOps = 3;
1528 let ResourceCycles = [1, 2];
1529 }
1530 def : InstRW<[WritePHADDSUBr], (instregex "MMX_PHADD(W?)rr64",
1531 "MMX_PHADDSWrr64",
1532 "MMX_PHSUB(W|D)rr64",
1533 "MMX_PHSUBSWrr64",
1534 "(V?)PH(ADD|SUB)(W|D)(Y?)rr",
1535 "(V?)PH(ADD|SUB)SWrr(256)?")>;
1536
1537 // v <- v,m.
1538 def WritePHADDSUBm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
1539 let Latency = 6;
1540 let NumMicroOps = 3;
1541 let ResourceCycles = [1, 2, 1];
1542 }
1543 def : InstRW<[WritePHADDSUBm, ReadAfterLd],
1544 (instregex "MMX_PHADD(W?)rm64",
1545 "MMX_PHADDSWrm64",
1546 "MMX_PHSUB(W|D)rm64",
1547 "MMX_PHSUBSWrm64",
1548 "(V?)PH(ADD|SUB)(W|D)(Y?)rm",
1549 "(V?)PH(ADD|SUB)SWrm(128|256)?")>;
1550
1551 // PCMPGTQ.
1552 // v <- v,v.
1553 def WritePCMPGTQr : SchedWriteRes<[HWPort0]> {
1554 let Latency = 5;
1555 let NumMicroOps = 1;
1556 }
1557 def : InstRW<[WritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>;
1558
1559 // v <- v,m.
1560 def WritePCMPGTQm : SchedWriteRes<[HWPort0, HWPort23]> {
1561 let Latency = 5;
1562 let NumMicroOps = 2;
1563 let ResourceCycles = [1, 1];
1564 }
1565 def : InstRW<[WritePCMPGTQm, ReadAfterLd], (instregex "(V?)PCMPGTQ(Y?)rm")>;
1566
1567 // PMULLD.
1568 // x,x / y,y,y.
1569 def WritePMULLDr : SchedWriteRes<[HWPort0]> {
1570 let Latency = 10;
1571 let NumMicroOps = 2;
1572 let ResourceCycles = [2];
1573 }
1574 def : InstRW<[WritePMULLDr], (instregex "(V?)PMULLD(Y?)rr")>;
1575
1576 // x,m / y,y,m.
1577 def WritePMULLDm : SchedWriteRes<[HWPort0, HWPort23]> {
1578 let Latency = 10;
1579 let NumMicroOps = 3;
1580 let ResourceCycles = [2, 1];
1581 }
1582 def : InstRW<[WritePMULLDm, ReadAfterLd], (instregex "(V?)PMULLD(Y?)rm")>;
1583
1584 //-- Logic instructions --//
1585
1586 // PTEST.
1587 // v,v.
1588 def WritePTESTr : SchedWriteRes<[HWPort0, HWPort5]> {
1589 let Latency = 2;
1590 let NumMicroOps = 2;
1591 let ResourceCycles = [1, 1];
1592 }
1593 def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rr")>;
1594
1595 // v,m.
1596 def WritePTESTm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> {
1597 let Latency = 6;
1598 let NumMicroOps = 3;
1599 let ResourceCycles = [1, 1, 1];
1600 }
1601 def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rm")>;
1602
1603 // PSLL,PSRL,PSRA W/D/Q.
1604 // x,x / v,v,x.
1605 def WritePShift : SchedWriteRes<[HWPort0, HWPort5]> {
1606 let Latency = 2;
1607 let NumMicroOps = 2;
1608 let ResourceCycles = [1, 1];
1609 }
1610 def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>;
1611
1612 // PSLL,PSRL DQ.
1613 def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>;
1614
1615 //-- Other --//
1616
1617 // EMMS.
1618 def WriteEMMS : SchedWriteRes<[]> {
1619 let Latency = 13;
1620 let NumMicroOps = 31;
1621 }
1622 def : InstRW<[WriteEMMS], (instregex "MMX_EMMS")>;
1623
1624787 //=== Floating Point XMM and YMM Instructions ===//
1625 //-- Move instructions --//
1626
1627 // MOVMSKP S/D.
1628 // r32 <- x.
1629 def WriteMOVMSKPr : SchedWriteRes<[HWPort0]> {
1630 let Latency = 3;
1631 }
1632 def : InstRW<[WriteMOVMSKPr], (instregex "(V?)MOVMSKP(S|D)rr")>;
1633
1634 // r32 <- y.
1635 def WriteVMOVMSKPYr : SchedWriteRes<[HWPort0]> {
1636 let Latency = 2;
1637 }
1638 def : InstRW<[WriteVMOVMSKPYr], (instregex "VMOVMSKP(S|D)Yrr")>;
1639
1640 // VPERM2F128.
1641 def : InstRW<[WriteFShuffle256], (instregex "VPERM2F128rr")>;
1642 def : InstRW<[WriteFShuffle256Ld, ReadAfterLd], (instregex "VPERM2F128rm")>;
1643
1644 // BLENDVP S/D.
1645 def : InstRW<[WriteFVarBlend], (instregex "BLENDVP(S|D)rr0")>;
1646 def : InstRW<[WriteFVarBlendLd, ReadAfterLd], (instregex "BLENDVP(S|D)rm0")>;
1647
1648 // VBROADCASTF128.
1649 def : InstRW<[WriteLoad], (instregex "VBROADCASTF128")>;
1650
1651 // EXTRACTPS.
1652 // r32,x,i.
1653 def WriteEXTRACTPSr : SchedWriteRes<[HWPort0, HWPort5]> {
1654 let NumMicroOps = 2;
1655 let ResourceCycles = [1, 1];
1656 }
1657 def : InstRW<[WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
1658
1659 // m32,x,i.
1660 def WriteEXTRACTPSm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> {
1661 let Latency = 4;
1662 let NumMicroOps = 3;
1663 let ResourceCycles = [1, 1, 1];
1664 }
1665 def : InstRW<[WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
1666
1667 // VEXTRACTF128.
1668 // x,y,i.
1669 def : InstRW<[WriteFShuffle256], (instregex "VEXTRACTF128rr")>;
1670
1671 // m128,y,i.
1672 def WriteVEXTRACTF128m : SchedWriteRes<[HWPort23, HWPort4]> {
1673 let Latency = 4;
1674 let NumMicroOps = 2;
1675 let ResourceCycles = [1, 1];
1676 }
1677 def : InstRW<[WriteVEXTRACTF128m], (instregex "VEXTRACTF128mr")>;
1678
1679 // VINSERTF128.
1680 // y,y,x,i.
1681 def : InstRW<[WriteFShuffle256], (instregex "VINSERTF128rr")>;
1682
1683 // y,y,m128,i.
1684 def WriteVINSERTF128m : SchedWriteRes<[HWPort015, HWPort23]> {
1685 let Latency = 4;
1686 let NumMicroOps = 2;
1687 let ResourceCycles = [1, 1];
1688 }
1689 def : InstRW<[WriteFShuffle256, ReadAfterLd], (instregex "VINSERTF128rm")>;
1690
1691 // VMASKMOVP S/D.
1692 // v,v,m.
1693 def WriteVMASKMOVPrm : SchedWriteRes<[HWPort5, HWPort23]> {
1694 let Latency = 4;
1695 let NumMicroOps = 3;
1696 let ResourceCycles = [2, 1];
1697 }
1698 def : InstRW<[WriteVMASKMOVPrm], (instregex "VMASKMOVP(S|D)(Y?)rm")>;
1699
1700 // m128,x,x.
1701 def WriteVMASKMOVPmr : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1702 let Latency = 13;
1703 let NumMicroOps = 4;
1704 let ResourceCycles = [1, 1, 1, 1];
1705 }
1706 def : InstRW<[WriteVMASKMOVPmr], (instregex "VMASKMOVP(S|D)mr")>;
1707
1708 // m256,y,y.
1709 def WriteVMASKMOVPYmr : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1710 let Latency = 14;
1711 let NumMicroOps = 4;
1712 let ResourceCycles = [1, 1, 1, 1];
1713 }
1714 def : InstRW<[WriteVMASKMOVPYmr], (instregex "VMASKMOVP(S|D)Ymr")>;
1715788
1716789 // VGATHERDPS.
1717790 // x.
1765838 }
1766839 def : InstRW<[WriteVGATHERQPD256, ReadAfterLd], (instregex "VGATHERQPDYrm")>;
1767840
1768 //-- Conversion instructions --//
1769
1770 // CVTPD2PS.
1771 // x,x.
1772 def : InstRW<[WriteP1_P5_Lat4], (instregex "(V?)CVTPD2PSrr")>;
1773
1774 // x,m128.
1775 def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(V?)CVTPD2PS(X?)rm")>;
1776
1777 // x,y.
1778 def WriteCVTPD2PSYrr : SchedWriteRes<[HWPort1, HWPort5]> {
841 // Remaining instrs.
842
843 def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> {
844 let Latency = 1;
845 let NumMicroOps = 1;
846 let ResourceCycles = [1];
847 }
848 def: InstRW<[HWWriteResGroup0], (instregex "LDDQUrm")>;
849 def: InstRW<[HWWriteResGroup0], (instregex "LD_F32m")>;
850 def: InstRW<[HWWriteResGroup0], (instregex "LD_F64m")>;
851 def: InstRW<[HWWriteResGroup0], (instregex "LD_F80m")>;
852 def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64from64rm")>;
853 def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64rm")>;
854 def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVD64to64rm")>;
855 def: InstRW<[HWWriteResGroup0], (instregex "MMX_MOVQ64rm")>;
856 def: InstRW<[HWWriteResGroup0], (instregex "MOV(16|32|64)rm")>;
857 def: InstRW<[HWWriteResGroup0], (instregex "MOV64toPQIrm")>;
858 def: InstRW<[HWWriteResGroup0], (instregex "MOV8rm")>;
859 def: InstRW<[HWWriteResGroup0], (instregex "MOVAPDrm")>;
860 def: InstRW<[HWWriteResGroup0], (instregex "MOVAPSrm")>;
861 def: InstRW<[HWWriteResGroup0], (instregex "MOVDDUPrm")>;
862 def: InstRW<[HWWriteResGroup0], (instregex "MOVDI2PDIrm")>;
863 def: InstRW<[HWWriteResGroup0], (instregex "MOVDQArm")>;
864 def: InstRW<[HWWriteResGroup0], (instregex "MOVDQUrm")>;
865 def: InstRW<[HWWriteResGroup0], (instregex "MOVNTDQArm")>;
866 def: InstRW<[HWWriteResGroup0], (instregex "MOVSHDUPrm")>;
867 def: InstRW<[HWWriteResGroup0], (instregex "MOVSLDUPrm")>;
868 def: InstRW<[HWWriteResGroup0], (instregex "MOVSSrm")>;
869 def: InstRW<[HWWriteResGroup0], (instregex "MOVSX(16|32|64)rm16")>;
870 def: InstRW<[HWWriteResGroup0], (instregex "MOVSX(16|32|64)rm32")>;
871 def: InstRW<[HWWriteResGroup0], (instregex "MOVSX(16|32|64)rm8")>;
872 def: InstRW<[HWWriteResGroup0], (instregex "MOVUPDrm")>;
873 def: InstRW<[HWWriteResGroup0], (instregex "MOVUPSrm")>;
874 def: InstRW<[HWWriteResGroup0], (instregex "MOVZX(16|32|64)rm16")>;
875 def: InstRW<[HWWriteResGroup0], (instregex "MOVZX(16|32|64)rm8")>;
876 def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHNTA")>;
877 def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT0")>;
878 def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT1")>;
879 def: InstRW<[HWWriteResGroup0], (instregex "PREFETCHT2")>;
880 def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTF128")>;
881 def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTI128")>;
882 def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSDYrm")>;
883 def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSYrm")>;
884 def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm")>;
885 def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUYrm")>;
886 def: InstRW<[HWWriteResGroup0], (instregex "VLDDQUrm")>;
887 def: InstRW<[HWWriteResGroup0], (instregex "VMOV64toPQIrm")>;
888 def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDYrm")>;
889 def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPDrm")>;
890 def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSYrm")>;
891 def: InstRW<[HWWriteResGroup0], (instregex "VMOVAPSrm")>;
892 def: InstRW<[HWWriteResGroup0], (instregex "VMOVDDUPYrm")>;
893 def: InstRW<[HWWriteResGroup0], (instregex "VMOVDDUPrm")>;
894 def: InstRW<[HWWriteResGroup0], (instregex "VMOVDI2PDIrm")>;
895 def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQAYrm")>;
896 def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQArm")>;
897 def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUYrm")>;
898 def: InstRW<[HWWriteResGroup0], (instregex "VMOVDQUrm")>;
899 def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQAYrm")>;
900 def: InstRW<[HWWriteResGroup0], (instregex "VMOVNTDQArm")>;
901 def: InstRW<[HWWriteResGroup0], (instregex "VMOVQI2PQIrm")>;
902 def: InstRW<[HWWriteResGroup0], (instregex "VMOVSDrm")>;
903 def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPYrm")>;
904 def: InstRW<[HWWriteResGroup0], (instregex "VMOVSHDUPrm")>;
905 def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPYrm")>;
906 def: InstRW<[HWWriteResGroup0], (instregex "VMOVSLDUPrm")>;
907 def: InstRW<[HWWriteResGroup0], (instregex "VMOVSSrm")>;
908 def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDYrm")>;
909 def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPDrm")>;
910 def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSYrm")>;
911 def: InstRW<[HWWriteResGroup0], (instregex "VMOVUPSrm")>;
912 def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDYrm")>;
913 def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTDrm")>;
914 def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQYrm")>;
915 def: InstRW<[HWWriteResGroup0], (instregex "VPBROADCASTQrm")>;
916
917 def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
918 let Latency = 1;
919 let NumMicroOps = 2;
920 let ResourceCycles = [1,1];
921 }
922 def: InstRW<[HWWriteResGroup1], (instregex "FBSTPm")>;
923 def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64from64rm")>;
924 def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVD64mr")>;
925 def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVNTQmr")>;
926 def: InstRW<[HWWriteResGroup1], (instregex "MMX_MOVQ64mr")>;
927 def: InstRW<[HWWriteResGroup1], (instregex "MOV(16|32|64)mr")>;
928 def: InstRW<[HWWriteResGroup1], (instregex "MOV8mi")>;
929 def: InstRW<[HWWriteResGroup1], (instregex "MOV8mr")>;
930 def: InstRW<[HWWriteResGroup1], (instregex "MOVAPDmr")>;
931 def: InstRW<[HWWriteResGroup1], (instregex "MOVAPSmr")>;
932 def: InstRW<[HWWriteResGroup1], (instregex "MOVDQAmr")>;
933 def: InstRW<[HWWriteResGroup1], (instregex "MOVDQUmr")>;
934 def: InstRW<[HWWriteResGroup1], (instregex "MOVHPDmr")>;
935 def: InstRW<[HWWriteResGroup1], (instregex "MOVHPSmr")>;
936 def: InstRW<[HWWriteResGroup1], (instregex "MOVLPDmr")>;
937 def: InstRW<[HWWriteResGroup1], (instregex "MOVLPSmr")>;
938 def: InstRW<[HWWriteResGroup1], (instregex "MOVNTDQmr")>;
939 def: InstRW<[HWWriteResGroup1], (instregex "MOVNTI_64mr")>;
940 def: InstRW<[HWWriteResGroup1], (instregex "MOVNTImr")>;
941 def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPDmr")>;
942 def: InstRW<[HWWriteResGroup1], (instregex "MOVNTPSmr")>;
943 def: InstRW<[HWWriteResGroup1], (instregex "MOVPDI2DImr")>;
944 def: InstRW<[HWWriteResGroup1], (instregex "MOVPQI2QImr")>;
945 def: InstRW<[HWWriteResGroup1], (instregex "MOVPQIto64mr")>;
946 def: InstRW<[HWWriteResGroup1], (instregex "MOVSSmr")>;
947 def: InstRW<[HWWriteResGroup1], (instregex "MOVUPDmr")>;
948 def: InstRW<[HWWriteResGroup1], (instregex "MOVUPSmr")>;
949 def: InstRW<[HWWriteResGroup1], (instregex "ST_FP32m")>;
950 def: InstRW<[HWWriteResGroup1], (instregex "ST_FP64m")>;
951 def: InstRW<[HWWriteResGroup1], (instregex "ST_FP80m")>;
952 def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTF128mr")>;
953 def: InstRW<[HWWriteResGroup1], (instregex "VEXTRACTI128mr")>;
954 def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDYmr")>;
955 def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPDmr")>;
956 def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSYmr")>;
957 def: InstRW<[HWWriteResGroup1], (instregex "VMOVAPSmr")>;
958 def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAYmr")>;
959 def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQAmr")>;
960 def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUYmr")>;
961 def: InstRW<[HWWriteResGroup1], (instregex "VMOVDQUmr")>;
962 def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPDmr")>;
963 def: InstRW<[HWWriteResGroup1], (instregex "VMOVHPSmr")>;
964 def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPDmr")>;
965 def: InstRW<[HWWriteResGroup1], (instregex "VMOVLPSmr")>;
966 def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQYmr")>;
967 def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTDQmr")>;
968 def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDYmr")>;
969 def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPDmr")>;
970 def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSYmr")>;
971 def: InstRW<[HWWriteResGroup1], (instregex "VMOVNTPSmr")>;
972 def: InstRW<[HWWriteResGroup1], (instregex "VMOVPDI2DImr")>;
973 def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQI2QImr")>;
974 def: InstRW<[HWWriteResGroup1], (instregex "VMOVPQIto64mr")>;
975 def: InstRW<[HWWriteResGroup1], (instregex "VMOVSDmr")>;
976 def: InstRW<[HWWriteResGroup1], (instregex "VMOVSSmr")>;
977 def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDYmr")>;
978 def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPDmr")>;
979 def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSYmr")>;
980 def: InstRW<[HWWriteResGroup1], (instregex "VMOVUPSmr")>;
981 def: InstRW<[HWWriteResGroup1], (instregex "VMPTRSTm")>;
982
983 def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
984 let Latency = 1;
985 let NumMicroOps = 1;
986 let ResourceCycles = [1];
987 }
988 def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64from64rr")>;
989 def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64grr")>;
990 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PMOVMSKBrr")>;
991 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDri")>;
992 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLDrr")>;
993 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQri")>;
994 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLQrr")>;
995 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWri")>;
996 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSLLWrr")>;
997 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADri")>;
998 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRADrr")>;
999 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWri")>;
1000 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRAWrr")>;
1001 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDri")>;
1002 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLDrr")>;
1003 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQri")>;
1004 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLQrr")>;
1005 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWri")>;
1006 def: InstRW<[HWWriteResGroup2], (instregex "MMX_PSRLWrr")>;
1007 def: InstRW<[HWWriteResGroup2], (instregex "MOVPDI2DIrr")>;
1008 def: InstRW<[HWWriteResGroup2], (instregex "MOVPQIto64rr")>;
1009 def: InstRW<[HWWriteResGroup2], (instregex "PSLLDri")>;
1010 def: InstRW<[HWWriteResGroup2], (instregex "PSLLQri")>;
1011 def: InstRW<[HWWriteResGroup2], (instregex "PSLLWri")>;
1012 def: InstRW<[HWWriteResGroup2], (instregex "PSRADri")>;
1013 def: InstRW<[HWWriteResGroup2], (instregex "PSRAWri")>;
1014 def: InstRW<[HWWriteResGroup2], (instregex "PSRLDri")>;
1015 def: InstRW<[HWWriteResGroup2], (instregex "PSRLQri")>;
1016 def: InstRW<[HWWriteResGroup2], (instregex "PSRLWri")>;
1017 def: InstRW<[HWWriteResGroup2], (instregex "VMOVPDI2DIrr")>;
1018 def: InstRW<[HWWriteResGroup2], (instregex "VMOVPQIto64rr")>;
1019 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDYri")>;
1020 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLDri")>;
1021 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQYri")>;
1022 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLQri")>;
1023 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQYrr")>;
1024 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQrr")>;
1025 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWYri")>;
1026 def: InstRW<[HWWriteResGroup2], (instregex "VPSLLWri")>;
1027 def: InstRW<[HWWriteResGroup2], (instregex "VPSRADYri")>;
1028 def: InstRW<[HWWriteResGroup2], (instregex "VPSRADri")>;
1029 def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWYri")>;
1030 def: InstRW<[HWWriteResGroup2], (instregex "VPSRAWri")>;
1031 def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDYri")>;
1032 def: InstRW<[HWWriteResGroup2], (instregex "VPSRLDri")>;
1033 def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQYri")>;
1034 def: InstRW<[HWWriteResGroup2], (instregex "VPSRLQri")>;
1035 def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQYrr")>;
1036 def: InstRW<[HWWriteResGroup2], (instregex "VPSRLVQrr")>;
1037 def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWYri")>;
1038 def: InstRW<[HWWriteResGroup2], (instregex "VPSRLWri")>;
1039 def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDYrr")>;
1040 def: InstRW<[HWWriteResGroup2], (instregex "VTESTPDrr")>;
1041 def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSYrr")>;
1042 def: InstRW<[HWWriteResGroup2], (instregex "VTESTPSrr")>;
1043
1044 def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> {
1045 let Latency = 1;
1046 let NumMicroOps = 1;
1047 let ResourceCycles = [1];
1048 }
1049 def: InstRW<[HWWriteResGroup3], (instregex "COMP_FST0r")>;
1050 def: InstRW<[HWWriteResGroup3], (instregex "COM_FST0r")>;
1051 def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
1052 def: InstRW<[HWWriteResGroup3], (instregex "MMX_MASKMOVQ64")>;
1053 def: InstRW<[HWWriteResGroup3], (instregex "UCOM_FPr")>;
1054 def: InstRW<[HWWriteResGroup3], (instregex "UCOM_Fr")>;
1055 def: InstRW<[HWWriteResGroup3], (instregex "VMASKMOVDQU")>;
1056
1057 def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> {
1058 let Latency = 1;
1059 let NumMicroOps = 1;
1060 let ResourceCycles = [1];
1061 }
1062 def: InstRW<[HWWriteResGroup4], (instregex "ANDNPDrr")>;
1063 def: InstRW<[HWWriteResGroup4], (instregex "ANDNPSrr")>;
1064 def: InstRW<[HWWriteResGroup4], (instregex "ANDPDrr")>;
1065 def: InstRW<[HWWriteResGroup4], (instregex "ANDPSrr")>;
1066 def: InstRW<[HWWriteResGroup4], (instregex "INSERTPSrr")>;
1067 def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64rr")>;
1068 def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVD64to64rr")>;
1069 def: InstRW<[HWWriteResGroup4], (instregex "MMX_MOVQ2DQrr")>;
1070 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PALIGNR64irr")>;
1071 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFBrr64")>;
1072 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PSHUFWri")>;
1073 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHBWirr")>;
1074 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHDQirr")>;
1075 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKHWDirr")>;
1076 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLBWirr")>;
1077 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLDQirr")>;
1078 def: InstRW<[HWWriteResGroup4], (instregex "MMX_PUNPCKLWDirr")>;
1079 def: InstRW<[HWWriteResGroup4], (instregex "MOV64toPQIrr")>;
1080 def: InstRW<[HWWriteResGroup4], (instregex "MOVAPDrr")>;
1081 def: InstRW<[HWWriteResGroup4], (instregex "MOVAPSrr")>;
1082 def: InstRW<[HWWriteResGroup4], (instregex "MOVDDUPrr")>;
1083 def: InstRW<[HWWriteResGroup4], (instregex "MOVDI2PDIrr")>;
1084 def: InstRW<[HWWriteResGroup4], (instregex "MOVHLPSrr")>;
1085 def: InstRW<[HWWriteResGroup4], (instregex "MOVLHPSrr")>;
1086 def: InstRW<[HWWriteResGroup4], (instregex "MOVSDrr(_REV?)")>;
1087 def: InstRW<[HWWriteResGroup4], (instregex "MOVSHDUPrr")>;
1088 def: InstRW<[HWWriteResGroup4], (instregex "MOVSLDUPrr")>;
1089 def: InstRW<[HWWriteResGroup4], (instregex "MOVSSrr(_REV?)")>;
1090 def: InstRW<[HWWriteResGroup4], (instregex "MOVUPDrr(_REV?)")>;
1091 def: InstRW<[HWWriteResGroup4], (instregex "MOVUPSrr(_REV?)")>;
1092 def: InstRW<[HWWriteResGroup4], (instregex "ORPDrr")>;
1093 def: InstRW<[HWWriteResGroup4], (instregex "ORPSrr")>;
1094 def: InstRW<[HWWriteResGroup4], (instregex "PACKSSDWrr")>;
1095 def: InstRW<[HWWriteResGroup4], (instregex "PACKSSWBrr")>;
1096 def: InstRW<[HWWriteResGroup4], (instregex "PACKUSDWrr")>;
1097 def: InstRW<[HWWriteResGroup4], (instregex "PACKUSWBrr")>;
1098 def: InstRW<[HWWriteResGroup4], (instregex "PALIGNRrri")>;
1099 def: InstRW<[HWWriteResGroup4], (instregex "PBLENDWrri")>;
1100 def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBDrr")>;
1101 def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBQrr")>;
1102 def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXBWrr")>;
1103 def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXDQrr")>;
1104 def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWDrr")>;
1105 def: InstRW<[HWWriteResGroup4], (instregex "PMOVSXWQrr")>;
1106 def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBDrr")>;
1107 def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBQrr")>;
1108 def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXBWrr")>;
1109 def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXDQrr")>;
1110 def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWDrr")>;
1111 def: InstRW<[HWWriteResGroup4], (instregex "PMOVZXWQrr")>;
1112 def: InstRW<[HWWriteResGroup4], (instregex "PSHUFBrr")>;
1113 def: InstRW<[HWWriteResGroup4], (instregex "PSHUFDri")>;
1114 def: InstRW<[HWWriteResGroup4], (instregex "PSHUFHWri")>;
1115 def: InstRW<[HWWriteResGroup4], (instregex "PSHUFLWri")>;
1116 def: InstRW<[HWWriteResGroup4], (instregex "PSLLDQri")>;
1117 def: InstRW<[HWWriteResGroup4], (instregex "PSRLDQri")>;
1118 def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHBWrr")>;
1119 def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHDQrr")>;
1120 def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHQDQrr")>;
1121 def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKHWDrr")>;
1122 def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLBWrr")>;
1123 def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLDQrr")>;
1124 def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLQDQrr")>;
1125 def: InstRW<[HWWriteResGroup4], (instregex "PUNPCKLWDrr")>;
1126 def: InstRW<[HWWriteResGroup4], (instregex "SHUFPDrri")>;
1127 def: InstRW<[HWWriteResGroup4], (instregex "SHUFPSrri")>;
1128 def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPDrr")>;
1129 def: InstRW<[HWWriteResGroup4], (instregex "UNPCKHPSrr")>;
1130 def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPDrr")>;
1131 def: InstRW<[HWWriteResGroup4], (instregex "UNPCKLPSrr")>;
1132 def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDYrr")>;
1133 def: InstRW<[HWWriteResGroup4], (instregex "VANDNPDrr")>;
1134 def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSYrr")>;
1135 def: InstRW<[HWWriteResGroup4], (instregex "VANDNPSrr")>;
1136 def: InstRW<[HWWriteResGroup4], (instregex "VANDPDYrr")>;
1137 def: InstRW<[HWWriteResGroup4], (instregex "VANDPDrr")>;
1138 def: InstRW<[HWWriteResGroup4], (instregex "VANDPSYrr")>;
1139 def: InstRW<[HWWriteResGroup4], (instregex "VANDPSrr")>;
1140 def: InstRW<[HWWriteResGroup4], (instregex "VBROADCASTSSrr")>;
1141 def: InstRW<[HWWriteResGroup4], (instregex "VINSERTPSrr")>;
1142 def: InstRW<[HWWriteResGroup4], (instregex "VMOV64toPQIrr")>;
1143 def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDYrr(_REV?)")>;
1144 def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPDrr(_REV?)")>;
1145 def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSYrr(_REV?)")>;
1146 def: InstRW<[HWWriteResGroup4], (instregex "VMOVAPSrr(_REV?)")>;
1147 def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPYrr")>;
1148 def: InstRW<[HWWriteResGroup4], (instregex "VMOVDDUPrr")>;
1149 def: InstRW<[HWWriteResGroup4], (instregex "VMOVDI2PDIrr")>;
1150 def: InstRW<[HWWriteResGroup4], (instregex "VMOVHLPSrr")>;
1151 def: InstRW<[HWWriteResGroup4], (instregex "VMOVLHPSrr")>;
1152 def: InstRW<[HWWriteResGroup4], (instregex "VMOVSDrr(_REV?)")>;
1153 def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPYrr")>;
1154 def: InstRW<[HWWriteResGroup4], (instregex "VMOVSHDUPrr")>;
1155 def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPYrr")>;
1156 def: InstRW<[HWWriteResGroup4], (instregex "VMOVSLDUPrr")>;
1157 def: InstRW<[HWWriteResGroup4], (instregex "VMOVSSrr(_REV?)")>;
1158 def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDYrr(_REV?)")>;
1159 def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPDrr(_REV?)")>;
1160 def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSYrr(_REV?)")>;
1161 def: InstRW<[HWWriteResGroup4], (instregex "VMOVUPSrr(_REV?)")>;
1162 def: InstRW<[HWWriteResGroup4], (instregex "VORPDYrr")>;
1163 def: InstRW<[HWWriteResGroup4], (instregex "VORPDrr")>;
1164 def: InstRW<[HWWriteResGroup4], (instregex "VORPSYrr")>;
1165 def: InstRW<[HWWriteResGroup4], (instregex "VORPSrr")>;
1166 def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWYrr")>;
1167 def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSDWrr")>;
1168 def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBYrr")>;
1169 def: InstRW<[HWWriteResGroup4], (instregex "VPACKSSWBrr")>;
1170 def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWYrr")>;
1171 def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSDWrr")>;
1172 def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBYrr")>;
1173 def: InstRW<[HWWriteResGroup4], (instregex "VPACKUSWBrr")>;
1174 def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRYrri")>;
1175 def: InstRW<[HWWriteResGroup4], (instregex "VPALIGNRrri")>;
1176 def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWYrri")>;
1177 def: InstRW<[HWWriteResGroup4], (instregex "VPBLENDWrri")>;
1178 def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTDrr")>;
1179 def: InstRW<[HWWriteResGroup4], (instregex "VPBROADCASTQrr")>;
1180 def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDYri")>;
1181 def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDYrr")>;
1182 def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDri")>;
1183 def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPDrr")>;
1184 def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSYri")>;
1185 def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSYrr")>;
1186 def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSri")>;
1187 def: InstRW<[HWWriteResGroup4], (instregex "VPERMILPSrr")>;
1188 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBDrr")>;
1189 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBQrr")>;
1190 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXBWrr")>;
1191 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXDQrr")>;
1192 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWDrr")>;
1193 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVSXWQrr")>;
1194 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBDrr")>;
1195 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBQrr")>;
1196 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXBWrr")>;
1197 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXDQrr")>;
1198 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWDrr")>;
1199 def: InstRW<[HWWriteResGroup4], (instregex "VPMOVZXWQrr")>;
1200 def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBYrr")>;
1201 def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFBrr")>;
1202 def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDYri")>;
1203 def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFDri")>;
1204 def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFHWYri")>;
1205 def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFHWri")>;
1206 def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWYri")>;
1207 def: InstRW<[HWWriteResGroup4], (instregex "VPSHUFLWri")>;
1208 def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQYri")>;
1209 def: InstRW<[HWWriteResGroup4], (instregex "VPSLLDQri")>;
1210 def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQYri")>;
1211 def: InstRW<[HWWriteResGroup4], (instregex "VPSRLDQri")>;
1212 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWYrr")>;
1213 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHBWrr")>;
1214 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQYrr")>;
1215 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHDQrr")>;
1216 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHQDQYrr")>;
1217 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHQDQrr")>;
1218 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDYrr")>;
1219 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKHWDrr")>;
1220 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLBWYrr")>;
1221 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLBWrr")>;
1222 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQYrr")>;
1223 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLDQrr")>;
1224 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQYrr")>;
1225 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLQDQrr")>;
1226 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDYrr")>;
1227 def: InstRW<[HWWriteResGroup4], (instregex "VPUNPCKLWDrr")>;
1228 def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDYrri")>;
1229 def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPDrri")>;
1230 def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSYrri")>;
1231 def: InstRW<[HWWriteResGroup4], (instregex "VSHUFPSrri")>;
1232 def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPDYrr")>;
1233 def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPDrr")>;
1234 def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPSYrr")>;
1235 def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKHPSrr")>;
1236 def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDYrr")>;
1237 def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPDrr")>;
1238 def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSYrr")>;
1239 def: InstRW<[HWWriteResGroup4], (instregex "VUNPCKLPSrr")>;
1240 def: InstRW<[HWWriteResGroup4], (instregex "VXORPDYrr")>;
1241 def: InstRW<[HWWriteResGroup4], (instregex "VXORPDrr")>;
1242 def: InstRW<[HWWriteResGroup4], (instregex "VXORPSYrr")>;
1243 def: InstRW<[HWWriteResGroup4], (instregex "VXORPSrr")>;
1244 def: InstRW<[HWWriteResGroup4], (instregex "XORPDrr")>;
1245 def: InstRW<[HWWriteResGroup4], (instregex "XORPSrr")>;
1246
1247 def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> {
1248 let Latency = 1;
1249 let NumMicroOps = 1;
1250 let ResourceCycles = [1];
1251 }
1252 def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>;
1253
1254 def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> {
1255 let Latency = 1;
1256 let NumMicroOps = 1;
1257 let ResourceCycles = [1];
1258 }
1259 def: InstRW<[HWWriteResGroup6], (instregex "FINCSTP")>;
1260 def: InstRW<[HWWriteResGroup6], (instregex "FNOP")>;
1261
1262 def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
1263 let Latency = 1;
1264 let NumMicroOps = 1;
1265 let ResourceCycles = [1];
1266 }
1267 def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)ri8")>;
1268 def: InstRW<[HWWriteResGroup7], (instregex "BT(16|32|64)rr")>;
1269 def: InstRW<[HWWriteResGroup7], (instregex "BTC(16|32|64)ri8")>;
1270 def: InstRW<[HWWriteResGroup7], (instregex "BTC(16|32|64)rr")>;
1271 def: InstRW<[HWWriteResGroup7], (instregex "BTR(16|32|64)ri8")>;
1272 def: InstRW<[HWWriteResGroup7], (instregex "BTR(16|32|64)rr")>;
1273 def: InstRW<[HWWriteResGroup7], (instregex "BTS(16|32|64)ri8")>;
1274 def: InstRW<[HWWriteResGroup7], (instregex "BTS(16|32|64)rr")>;
1275 def: InstRW<[HWWriteResGroup7], (instregex "CDQ")>;
1276 def: InstRW<[HWWriteResGroup7], (instregex "CQO")>;
1277 def: InstRW<[HWWriteResGroup7], (instregex "JAE_1")>;
1278 def: InstRW<[HWWriteResGroup7], (instregex "JAE_4")>;
1279 def: InstRW<[HWWriteResGroup7], (instregex "JA_1")>;
1280 def: InstRW<[HWWriteResGroup7], (instregex "JA_4")>;
1281 def: InstRW<[HWWriteResGroup7], (instregex "JBE_1")>;
1282 def: InstRW<[HWWriteResGroup7], (instregex "JBE_4")>;
1283 def: InstRW<[HWWriteResGroup7], (instregex "JB_1")>;
1284 def: InstRW<[HWWriteResGroup7], (instregex "JB_4")>;
1285 def: InstRW<[HWWriteResGroup7], (instregex "JE_1")>;
1286 def: InstRW<[HWWriteResGroup7], (instregex "JE_4")>;
1287 def: InstRW<[HWWriteResGroup7], (instregex "JGE_1")>;
1288 def: InstRW<[HWWriteResGroup7], (instregex "JGE_4")>;
1289 def: InstRW<[HWWriteResGroup7], (instregex "JG_1")>;
1290 def: InstRW<[HWWriteResGroup7], (instregex "JG_4")>;
1291 def: InstRW<[HWWriteResGroup7], (instregex "JLE_1")>;
1292 def: InstRW<[HWWriteResGroup7], (instregex "JLE_4")>;
1293 def: InstRW<[HWWriteResGroup7], (instregex "JL_1")>;
1294 def: InstRW<[HWWriteResGroup7], (instregex "JL_4")>;
1295 def: InstRW<[HWWriteResGroup7], (instregex "JMP_1")>;
1296 def: InstRW<[HWWriteResGroup7], (instregex "JMP_4")>;
1297 def: InstRW<[HWWriteResGroup7], (instregex "JNE_1")>;
1298 def: InstRW<[HWWriteResGroup7], (instregex "JNE_4")>;
1299 def: InstRW<[HWWriteResGroup7], (instregex "JNO_1")>;
1300 def: InstRW<[HWWriteResGroup7], (instregex "JNO_4")>;
1301 def: InstRW<[HWWriteResGroup7], (instregex "JNP_1")>;
1302 def: InstRW<[HWWriteResGroup7], (instregex "JNP_4")>;
1303 def: InstRW<[HWWriteResGroup7], (instregex "JNS_1")>;
1304 def: InstRW<[HWWriteResGroup7], (instregex "JNS_4")>;
1305 def: InstRW<[HWWriteResGroup7], (instregex "JO_1")>;
1306 def: InstRW<[HWWriteResGroup7], (instregex "JO_4")>;
1307 def: InstRW<[HWWriteResGroup7], (instregex "JP_1")>;
1308 def: InstRW<[HWWriteResGroup7], (instregex "JP_4")>;
1309 def: InstRW<[HWWriteResGroup7], (instregex "JS_1")>;
1310 def: InstRW<[HWWriteResGroup7], (instregex "JS_4")>;
1311 def: InstRW<[HWWriteResGroup7], (instregex "RORX32ri")>;
1312 def: InstRW<[HWWriteResGroup7], (instregex "RORX64ri")>;
1313 def: InstRW<[HWWriteResGroup7], (instregex "SAR(16|32|64)r1")>;
1314 def: InstRW<[HWWriteResGroup7], (instregex "SAR(16|32|64)ri")>;
1315 def: InstRW<[HWWriteResGroup7], (instregex "SAR8r1")>;
1316 def: InstRW<[HWWriteResGroup7], (instregex "SAR8ri")>;
1317 def: InstRW<[HWWriteResGroup7], (instregex "SARX32rr")>;
1318 def: InstRW<[HWWriteResGroup7], (instregex "SARX64rr")>;
1319 def: InstRW<[HWWriteResGroup7], (instregex "SETAEr")>;
1320 def: InstRW<[HWWriteResGroup7], (instregex "SETBr")>;
1321 def: InstRW<[HWWriteResGroup7], (instregex "SETEr")>;
1322 def: InstRW<[HWWriteResGroup7], (instregex "SETGEr")>;
1323 def: InstRW<[HWWriteResGroup7], (instregex "SETGr")>;
1324 def: InstRW<[HWWriteResGroup7], (instregex "SETLEr")>;
1325 def: InstRW<[HWWriteResGroup7], (instregex "SETLr")>;
1326 def: InstRW<[HWWriteResGroup7], (instregex "SETNEr")>;
1327 def: InstRW<[HWWriteResGroup7], (instregex "SETNOr")>;
1328 def: InstRW<[HWWriteResGroup7], (instregex "SETNPr")>;
1329 def: InstRW<[HWWriteResGroup7], (instregex "SETNSr")>;
1330 def: InstRW<[HWWriteResGroup7], (instregex "SETOr")>;
1331 def: InstRW<[HWWriteResGroup7], (instregex "SETPr")>;
1332 def: InstRW<[HWWriteResGroup7], (instregex "SETSr")>;
1333 def: InstRW<[HWWriteResGroup7], (instregex "SHL(16|32|64)r1")>;
1334 def: InstRW<[HWWriteResGroup7], (instregex "SHL(16|32|64)ri")>;
1335 def: InstRW<[HWWriteResGroup7], (instregex "SHL8r1")>;
1336 def: InstRW<[HWWriteResGroup7], (instregex "SHL8ri")>;
1337 def: InstRW<[HWWriteResGroup7], (instregex "SHLX32rr")>;
1338 def: InstRW<[HWWriteResGroup7], (instregex "SHLX64rr")>;
1339 def: InstRW<[HWWriteResGroup7], (instregex "SHR(16|32|64)r1")>;
1340 def: InstRW<[HWWriteResGroup7], (instregex "SHR(16|32|64)ri")>;
1341 def: InstRW<[HWWriteResGroup7], (instregex "SHR8r1")>;
1342 def: InstRW<[HWWriteResGroup7], (instregex "SHR8ri")>;
1343 def: InstRW<[HWWriteResGroup7], (instregex "SHRX32rr")>;
1344 def: InstRW<[HWWriteResGroup7], (instregex "SHRX64rr")>;
1345
1346 def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> {
1347 let Latency = 1;
1348 let NumMicroOps = 1;
1349 let ResourceCycles = [1];
1350 }
1351 def: InstRW<[HWWriteResGroup8], (instregex "ANDN32rr")>;
1352 def: InstRW<[HWWriteResGroup8], (instregex "ANDN64rr")>;
1353 def: InstRW<[HWWriteResGroup8], (instregex "BLSI32rr")>;
1354 def: InstRW<[HWWriteResGroup8], (instregex "BLSI64rr")>;
1355 def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK32rr")>;
1356 def: InstRW<[HWWriteResGroup8], (instregex "BLSMSK64rr")>;
1357 def: InstRW<[HWWriteResGroup8], (instregex "BLSR32rr")>;
1358 def: InstRW<[HWWriteResGroup8], (instregex "BLSR64rr")>;
1359 def: InstRW<[HWWriteResGroup8], (instregex "BZHI32rr")>;
1360 def: InstRW<[HWWriteResGroup8], (instregex "BZHI64rr")>;
1361 def: InstRW<[HWWriteResGroup8], (instregex "LEA(16|32|64)r")>;
1362 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSBrr64")>;
1363 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSDrr64")>;
1364 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PABSWrr64")>;
1365 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDBirr")>;
1366 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDDirr")>;
1367 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDQirr")>;
1368 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSBirr")>;
1369 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDSWirr")>;
1370 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSBirr")>;
1371 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDUSWirr")>;
1372 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PADDWirr")>;
1373 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGBirr")>;
1374 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PAVGWirr")>;
1375 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQBirr")>;
1376 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQDirr")>;
1377 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPEQWirr")>;
1378 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTBirr")>;
1379 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTDirr")>;
1380 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PCMPGTWirr")>;
1381 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXSWirr")>;
1382 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMAXUBirr")>;
1383 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINSWirr")>;
1384 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PMINUBirr")>;
1385 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNBrr64")>;
1386 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNDrr64")>;
1387 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSIGNWrr64")>;
1388 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBBirr")>;
1389 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBDirr")>;
1390 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBQirr")>;
1391 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSBirr")>;
1392 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBSWirr")>;
1393 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSBirr")>;
1394 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBUSWirr")>;
1395 def: InstRW<[HWWriteResGroup8], (instregex "MMX_PSUBWirr")>;
1396 def: InstRW<[HWWriteResGroup8], (instregex "PABSBrr")>;
1397 def: InstRW<[HWWriteResGroup8], (instregex "PABSDrr")>;
1398 def: InstRW<[HWWriteResGroup8], (instregex "PABSWrr")>;
1399 def: InstRW<[HWWriteResGroup8], (instregex "PADDBrr")>;
1400 def: InstRW<[HWWriteResGroup8], (instregex "PADDDrr")>;
1401 def: InstRW<[HWWriteResGroup8], (instregex "PADDQrr")>;
1402 def: InstRW<[HWWriteResGroup8], (instregex "PADDSBrr")>;
1403 def: InstRW<[HWWriteResGroup8], (instregex "PADDSWrr")>;
1404 def: InstRW<[HWWriteResGroup8], (instregex "PADDUSBrr")>;
1405 def: InstRW<[HWWriteResGroup8], (instregex "PADDUSWrr")>;
1406 def: InstRW<[HWWriteResGroup8], (instregex "PADDWrr")>;
1407 def: InstRW<[HWWriteResGroup8], (instregex "PAVGBrr")>;
1408 def: InstRW<[HWWriteResGroup8], (instregex "PAVGWrr")>;
1409 def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQBrr")>;
1410 def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQDrr")>;
1411 def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQQrr")>;
1412 def: InstRW<[HWWriteResGroup8], (instregex "PCMPEQWrr")>;
1413 def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTBrr")>;
1414 def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTDrr")>;
1415 def: InstRW<[HWWriteResGroup8], (instregex "PCMPGTWrr")>;
1416 def: InstRW<[HWWriteResGroup8], (instregex "PMAXSBrr")>;
1417 def: InstRW<[HWWriteResGroup8], (instregex "PMAXSDrr")>;
1418 def: InstRW<[HWWriteResGroup8], (instregex "PMAXSWrr")>;
1419 def: InstRW<[HWWriteResGroup8], (instregex "PMAXUBrr")>;
1420 def: InstRW<[HWWriteResGroup8], (instregex "PMAXUDrr")>;
1421 def: InstRW<[HWWriteResGroup8], (instregex "PMAXUWrr")>;
1422 def: InstRW<[HWWriteResGroup8], (instregex "PMINSBrr")>;
1423 def: InstRW<[HWWriteResGroup8], (instregex "PMINSDrr")>;
1424 def: InstRW<[HWWriteResGroup8], (instregex "PMINSWrr")>;
1425 def: InstRW<[HWWriteResGroup8], (instregex "PMINUBrr")>;
1426 def: InstRW<[HWWriteResGroup8], (instregex "PMINUDrr")>;
1427 def: InstRW<[HWWriteResGroup8], (instregex "PMINUWrr")>;
1428 def: InstRW<[HWWriteResGroup8], (instregex "PSIGNBrr128")>;
1429 def: InstRW<[HWWriteResGroup8], (instregex "PSIGNDrr128")>;
1430 def: InstRW<[HWWriteResGroup8], (instregex "PSIGNWrr128")>;
1431 def: InstRW<[HWWriteResGroup8], (instregex "PSUBBrr")>;
1432 def: InstRW<[HWWriteResGroup8], (instregex "PSUBDrr")>;
1433 def: InstRW<[HWWriteResGroup8], (instregex "PSUBQrr")>;
1434 def: InstRW<[HWWriteResGroup8], (instregex "PSUBSBrr")>;
1435 def: InstRW<[HWWriteResGroup8], (instregex "PSUBSWrr")>;
1436 def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSBrr")>;
1437 def: InstRW<[HWWriteResGroup8], (instregex "PSUBUSWrr")>;
1438 def: InstRW<[HWWriteResGroup8], (instregex "PSUBWrr")>;
1439 def: InstRW<[HWWriteResGroup8], (instregex "VPABSBYrr")>;
1440 def: InstRW<[HWWriteResGroup8], (instregex "VPABSBrr")>;
1441 def: InstRW<[HWWriteResGroup8], (instregex "VPABSDYrr")>;
1442 def: InstRW<[HWWriteResGroup8], (instregex "VPABSDrr")>;
1443 def: InstRW<[HWWriteResGroup8], (instregex "VPABSWYrr")>;
1444 def: InstRW<[HWWriteResGroup8], (instregex "VPABSWrr")>;
1445 def: InstRW<[HWWriteResGroup8], (instregex "VPADDBYrr")>;
1446 def: InstRW<[HWWriteResGroup8], (instregex "VPADDBrr")>;
1447 def: InstRW<[HWWriteResGroup8], (instregex "VPADDDYrr")>;
1448 def: InstRW<[HWWriteResGroup8], (instregex "VPADDDrr")>;
1449 def: InstRW<[HWWriteResGroup8], (instregex "VPADDQYrr")>;
1450 def: InstRW<[HWWriteResGroup8], (instregex "VPADDQrr")>;
1451 def: InstRW<[HWWriteResGroup8], (instregex "VPADDSBYrr")>;
1452 def: InstRW<[HWWriteResGroup8], (instregex "VPADDSBrr")>;
1453 def: InstRW<[HWWriteResGroup8], (instregex "VPADDSWYrr")>;
1454 def: InstRW<[HWWriteResGroup8], (instregex "VPADDSWrr")>;
1455 def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBYrr")>;
1456 def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSBrr")>;
1457 def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWYrr")>;
1458 def: InstRW<[HWWriteResGroup8], (instregex "VPADDUSWrr")>;
1459 def: InstRW<[HWWriteResGroup8], (instregex "VPADDWYrr")>;
1460 def: InstRW<[HWWriteResGroup8], (instregex "VPADDWrr")>;
1461 def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBYrr")>;
1462 def: InstRW<[HWWriteResGroup8], (instregex "VPAVGBrr")>;
1463 def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWYrr")>;
1464 def: InstRW<[HWWriteResGroup8], (instregex "VPAVGWrr")>;
1465 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBYrr")>;
1466 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQBrr")>;
1467 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDYrr")>;
1468 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQDrr")>;
1469 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQQYrr")>;
1470 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQQrr")>;
1471 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWYrr")>;
1472 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPEQWrr")>;
1473 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBYrr")>;
1474 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTBrr")>;
1475 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDYrr")>;
1476 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTDrr")>;
1477 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWYrr")>;
1478 def: InstRW<[HWWriteResGroup8], (instregex "VPCMPGTWrr")>;
1479 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBYrr")>;
1480 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSBrr")>;
1481 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDYrr")>;
1482 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSDrr")>;
1483 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWYrr")>;
1484 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXSWrr")>;
1485 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBYrr")>;
1486 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUBrr")>;
1487 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDYrr")>;
1488 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUDrr")>;
1489 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWYrr")>;
1490 def: InstRW<[HWWriteResGroup8], (instregex "VPMAXUWrr")>;
1491 def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBYrr")>;
1492 def: InstRW<[HWWriteResGroup8], (instregex "VPMINSBrr")>;
1493 def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDYrr")>;
1494 def: InstRW<[HWWriteResGroup8], (instregex "VPMINSDrr")>;
1495 def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWYrr")>;
1496 def: InstRW<[HWWriteResGroup8], (instregex "VPMINSWrr")>;
1497 def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBYrr")>;
1498 def: InstRW<[HWWriteResGroup8], (instregex "VPMINUBrr")>;
1499 def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDYrr")>;
1500 def: InstRW<[HWWriteResGroup8], (instregex "VPMINUDrr")>;
1501 def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWYrr")>;
1502 def: InstRW<[HWWriteResGroup8], (instregex "VPMINUWrr")>;
1503 def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBYrr256")>;
1504 def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNBrr128")>;
1505 def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDYrr256")>;
1506 def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNDrr128")>;
1507 def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWYrr256")>;
1508 def: InstRW<[HWWriteResGroup8], (instregex "VPSIGNWrr128")>;
1509 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBYrr")>;
1510 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBBrr")>;
1511 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDYrr")>;
1512 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBDrr")>;
1513 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQYrr")>;
1514 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBQrr")>;
1515 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBYrr")>;
1516 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSBrr")>;
1517 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWYrr")>;
1518 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBSWrr")>;
1519 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBYrr")>;
1520 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSBrr")>;
1521 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWYrr")>;
1522 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBUSWrr")>;
1523 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWYrr")>;
1524 def: InstRW<[HWWriteResGroup8], (instregex "VPSUBWrr")>;
1525
1526 def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> {
1527 let Latency = 1;
1528 let NumMicroOps = 1;
1529 let ResourceCycles = [1];
1530 }
1531 def: InstRW<[HWWriteResGroup9], (instregex "BLENDPDrri")>;
1532 def: InstRW<[HWWriteResGroup9], (instregex "BLENDPSrri")>;
1533 def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVD64from64rr")>;
1534 def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr(_REV?)")>;
1535 def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDNirr")>;
1536 def: InstRW<[HWWriteResGroup9], (instregex "MMX_PANDirr")>;
1537 def: InstRW<[HWWriteResGroup9], (instregex "MMX_PORirr")>;
1538 def: InstRW<[HWWriteResGroup9], (instregex "MMX_PXORirr")>;
1539 def: InstRW<[HWWriteResGroup9], (instregex "MOVDQArr(_REV?)")>;
1540 def: InstRW<[HWWriteResGroup9], (instregex "MOVDQUrr(_REV?)")>;
1541 def: InstRW<[HWWriteResGroup9], (instregex "MOVPQI2QIrr")>;
1542 def: InstRW<[HWWriteResGroup9], (instregex "PANDNrr")>;
1543 def: InstRW<[HWWriteResGroup9], (instregex "PANDrr")>;
1544 def: InstRW<[HWWriteResGroup9], (instregex "PORrr")>;
1545 def: InstRW<[HWWriteResGroup9], (instregex "PXORrr")>;
1546 def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDYrri")>;
1547 def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPDrri")>;
1548 def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSYrri")>;
1549 def: InstRW<[HWWriteResGroup9], (instregex "VBLENDPSrri")>;
1550 def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQAYrr(_REV?)")>;
1551 def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQArr(_REV?)")>;
1552 def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUYrr(_REV?)")>;
1553 def: InstRW<[HWWriteResGroup9], (instregex "VMOVDQUrr(_REV?)")>;
1554 def: InstRW<[HWWriteResGroup9], (instregex "VMOVPQI2QIrr")>;
1555 def: InstRW<[HWWriteResGroup9], (instregex "VMOVZPQILo2PQIrr")>;
1556 def: InstRW<[HWWriteResGroup9], (instregex "VPANDNYrr")>;
1557 def: InstRW<[HWWriteResGroup9], (instregex "VPANDNrr")>;
1558 def: InstRW<[HWWriteResGroup9], (instregex "VPANDYrr")>;
1559 def: InstRW<[HWWriteResGroup9], (instregex "VPANDrr")>;
1560 def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDYrri")>;
1561 def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDDrri")>;
1562 def: InstRW<[HWWriteResGroup9], (instregex "VPORYrr")>;
1563 def: InstRW<[HWWriteResGroup9], (instregex "VPORrr")>;
1564 def: InstRW<[HWWriteResGroup9], (instregex "VPXORYrr")>;
1565 def: InstRW<[HWWriteResGroup9], (instregex "VPXORrr")>;
1566
1567 def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
1568 let Latency = 1;
1569 let NumMicroOps = 1;
1570 let ResourceCycles = [1];
1571 }
1572 def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)ri8")>;
1573 def: InstRW<[HWWriteResGroup10], (instregex "ADD(16|32|64)rr(_REV?)")>;
1574 def: InstRW<[HWWriteResGroup10], (instregex "ADD8i8")>;
1575 def: InstRW<[HWWriteResGroup10], (instregex "ADD8ri")>;
1576 def: InstRW<[HWWriteResGroup10], (instregex "ADD8rr(_REV?)")>;
1577 def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)ri8")>;
1578 def: InstRW<[HWWriteResGroup10], (instregex "AND(16|32|64)rr(_REV?)")>;
1579 def: InstRW<[HWWriteResGroup10], (instregex "AND8i8")>;
1580 def: InstRW<[HWWriteResGroup10], (instregex "AND8ri")>;
1581 def: InstRW<[HWWriteResGroup10], (instregex "AND8rr(_REV?)")>;
1582 def: InstRW<[HWWriteResGroup10], (instregex "CBW")>;
1583 def: InstRW<[HWWriteResGroup10], (instregex "CLC")>;
1584 def: InstRW<[HWWriteResGroup10], (instregex "CMC")>;
1585 def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)ri8")>;
1586 def: InstRW<[HWWriteResGroup10], (instregex "CMP(16|32|64)rr(_REV?)")>;
1587 def: InstRW<[HWWriteResGroup10], (instregex "CMP8i8")>;
1588 def: InstRW<[HWWriteResGroup10], (instregex "CMP8ri")>;
1589 def: InstRW<[HWWriteResGroup10], (instregex "CMP8rr(_REV?)")>;
1590 def: InstRW<[HWWriteResGroup10], (instregex "CWDE")>;
1591 def: InstRW<[HWWriteResGroup10], (instregex "DEC(16|32|64)r")>;
1592 def: InstRW<[HWWriteResGroup10], (instregex "DEC8r")>;
1593 def: InstRW<[HWWriteResGroup10], (instregex "INC(16|32|64)r")>;
1594 def: InstRW<[HWWriteResGroup10], (instregex "INC8r")>;
1595 def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;
1596 def: InstRW<[HWWriteResGroup10], (instregex "MOV(16|32|64)rr(_REV?)")>;
1597 def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri(_alt?)")>;
1598 def: InstRW<[HWWriteResGroup10], (instregex "MOV8rr(_REV?)")>;
1599 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
1600 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
1601 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;
1602 def: InstRW<[HWWriteResGroup10], (instregex "MOVZX(16|32|64)rr16")>;
1603 def: InstRW<[HWWriteResGroup10], (instregex "MOVZX(16|32|64)rr8")>;
1604 def: InstRW<[HWWriteResGroup10], (instregex "NEG(16|32|64)r")>;
1605 def: InstRW<[HWWriteResGroup10], (instregex "NEG8r")>;
1606 def: InstRW<[HWWriteResGroup10], (instregex "NOOP")>;
1607 def: InstRW<[HWWriteResGroup10], (instregex "NOT(16|32|64)r")>;
1608 def: InstRW<[HWWriteResGroup10], (instregex "NOT8r")>;
1609 def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)ri8")>;
1610 def: InstRW<[HWWriteResGroup10], (instregex "OR(16|32|64)rr(_REV?)")>;
1611 def: InstRW<[HWWriteResGroup10], (instregex "OR8i8")>;
1612 def: InstRW<[HWWriteResGroup10], (instregex "OR8ri")>;
1613 def: InstRW<[HWWriteResGroup10], (instregex "OR8rr(_REV?)")>;
1614 def: InstRW<[HWWriteResGroup10], (instregex "SAHF")>;
1615 def: InstRW<[HWWriteResGroup10], (instregex "SGDT64m")>;
1616 def: InstRW<[HWWriteResGroup10], (instregex "SIDT64m")>;
1617 def: InstRW<[HWWriteResGroup10], (instregex "SLDT64m")>;
1618 def: InstRW<[HWWriteResGroup10], (instregex "SMSW16m")>;
1619 def: InstRW<[HWWriteResGroup10], (instregex "STC")>;
1620 def: InstRW<[HWWriteResGroup10], (instregex "STRm")>;
1621 def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)ri8")>;
1622 def: InstRW<[HWWriteResGroup10], (instregex "SUB(16|32|64)rr(_REV?)")>;
1623 def: InstRW<[HWWriteResGroup10], (instregex "SUB8i8")>;
1624 def: InstRW<[HWWriteResGroup10], (instregex "SUB8ri")>;
1625 def: InstRW<[HWWriteResGroup10], (instregex "SUB8rr(_REV?)")>;
1626 def: InstRW<[HWWriteResGroup10], (instregex "SYSCALL")>;
1627 def: InstRW<[HWWriteResGroup10], (instregex "TEST(16|32|64)rr")>;
1628 def: InstRW<[HWWriteResGroup10], (instregex "TEST8i8")>;
1629 def: InstRW<[HWWriteResGroup10], (instregex "TEST8ri")>;
1630 def: InstRW<[HWWriteResGroup10], (instregex "TEST8rr")>;
1631 def: InstRW<[HWWriteResGroup10], (instregex "XCHG(16|32|64)rr")>;
1632 def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)ri8")>;
1633 def: InstRW<[HWWriteResGroup10], (instregex "XOR(16|32|64)rr")>;
1634 def: InstRW<[HWWriteResGroup10], (instregex "XOR8i8")>;
1635 def: InstRW<[HWWriteResGroup10], (instregex "XOR8ri")>;
1636 def: InstRW<[HWWriteResGroup10], (instregex "XOR8rr")>;
1637
1638 def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> {
1639 let Latency = 1;
1640 let NumMicroOps = 2;
1641 let ResourceCycles = [1,1];
1642 }
1643 def: InstRW<[HWWriteResGroup11], (instregex "CVTPS2PDrm")>;
1644 def: InstRW<[HWWriteResGroup11], (instregex "CVTSS2SDrm")>;
1645 def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLDrm")>;
1646 def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLQrm")>;
1647 def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSLLWrm")>;
1648 def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRADrm")>;
1649 def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRAWrm")>;
1650 def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLDrm")>;
1651 def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLQrm")>;
1652 def: InstRW<[HWWriteResGroup11], (instregex "MMX_PSRLWrm")>;
1653 def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSYrm")>;
1654 def: InstRW<[HWWriteResGroup11], (instregex "VCVTPH2PSrm")>;
1655 def: InstRW<[HWWriteResGroup11], (instregex "VCVTPS2PDrm")>;
1656 def: InstRW<[HWWriteResGroup11], (instregex "VCVTSS2SDrm")>;
1657 def: InstRW<[HWWriteResGroup11], (instregex "VPSLLDYrm")>;
1658 def: InstRW<[HWWriteResGroup11], (instregex "VPSLLQYrm")>;
1659 def: InstRW<[HWWriteResGroup11], (instregex "VPSLLVQYrm")>;
1660 def: InstRW<[HWWriteResGroup11], (instregex "VPSLLVQrm")>;
1661 def: InstRW<[HWWriteResGroup11], (instregex "VPSLLWYrm")>;
1662 def: InstRW<[HWWriteResGroup11], (instregex "VPSRADYrm")>;
1663 def: InstRW<[HWWriteResGroup11], (instregex "VPSRAWYrm")>;
1664 def: InstRW<[HWWriteResGroup11], (instregex "VPSRLDYrm")>;
1665 def: InstRW<[HWWriteResGroup11], (instregex "VPSRLQYrm")>;
1666 def: InstRW<[HWWriteResGroup11], (instregex "VPSRLVQYrm")>;
1667 def: InstRW<[HWWriteResGroup11], (instregex "VPSRLVQrm")>;
1668 def: InstRW<[HWWriteResGroup11], (instregex "VPSRLWYrm")>;
1669 def: InstRW<[HWWriteResGroup11], (instregex "VTESTPDYrm")>;
1670 def: InstRW<[HWWriteResGroup11], (instregex "VTESTPDrm")>;
1671 def: InstRW<[HWWriteResGroup11], (instregex "VTESTPSYrm")>;
1672 def: InstRW<[HWWriteResGroup11], (instregex "VTESTPSrm")>;
1673
1674 def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
1675 let Latency = 1;
1676 let NumMicroOps = 2;
1677 let ResourceCycles = [1,1];
1678 }
1679 def: InstRW<[HWWriteResGroup12], (instregex "FCOM32m")>;
1680 def: InstRW<[HWWriteResGroup12], (instregex "FCOM64m")>;
1681 def: InstRW<[HWWriteResGroup12], (instregex "FCOMP32m")>;
1682 def: InstRW<[HWWriteResGroup12], (instregex "FCOMP64m")>;
1683
1684 def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> {
1685 let Latency = 1;
1686 let NumMicroOps = 2;
1687 let ResourceCycles = [1,1];
1688 }
1689 def: InstRW<[HWWriteResGroup13], (instregex "ANDNPDrm")>;
1690 def: InstRW<[HWWriteResGroup13], (instregex "ANDNPSrm")>;
1691 def: InstRW<[HWWriteResGroup13], (instregex "ANDPDrm")>;
1692 def: InstRW<[HWWriteResGroup13], (instregex "ANDPSrm")>;
1693 def: InstRW<[HWWriteResGroup13], (instregex "INSERTPSrm")>;
1694 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PALIGNR64irm")>;
1695 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PINSRWirmi")>;
1696 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PSHUFBrm64")>;
1697 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PSHUFWmi")>;
1698 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PUNPCKHBWirm")>;
1699 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PUNPCKHDQirm")>;
1700 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PUNPCKHWDirm")>;
1701 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PUNPCKLBWirm")>;
1702 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PUNPCKLDQirm")>;
1703 def: InstRW<[HWWriteResGroup13], (instregex "MMX_PUNPCKLWDirm")>;
1704 def: InstRW<[HWWriteResGroup13], (instregex "MOVHPDrm")>;
1705 def: InstRW<[HWWriteResGroup13], (instregex "MOVHPSrm")>;
1706 def: InstRW<[HWWriteResGroup13], (instregex "MOVLPDrm")>;
1707 def: InstRW<[HWWriteResGroup13], (instregex "MOVLPSrm")>;
1708 def: InstRW<[HWWriteResGroup13], (instregex "ORPDrm")>;
1709 def: InstRW<[HWWriteResGroup13], (instregex "ORPSrm")>;
1710 def: InstRW<[HWWriteResGroup13], (instregex "PACKSSDWrm")>;
1711 def: InstRW<[HWWriteResGroup13], (instregex "PACKSSWBrm")>;
1712 def: InstRW<[HWWriteResGroup13], (instregex "PACKUSDWrm")>;
1713 def: InstRW<[HWWriteResGroup13], (instregex "PACKUSWBrm")>;
1714 def: InstRW<[HWWriteResGroup13], (instregex "PALIGNRrmi")>;
1715 def: InstRW<[HWWriteResGroup13], (instregex "PBLENDWrmi")>;
1716 def: InstRW<[HWWriteResGroup13], (instregex "PINSRBrm")>;
1717 def: InstRW<[HWWriteResGroup13], (instregex "PINSRDrm")>;
1718 def: InstRW<[HWWriteResGroup13], (instregex "PINSRQrm")>;
1719 def: InstRW<[HWWriteResGroup13], (instregex "PINSRWrmi")>;
1720 def: InstRW<[HWWriteResGroup13], (instregex "PMOVSXBDrm")>;
1721 def: InstRW<[HWWriteResGroup13], (instregex "PMOVSXBQrm")>;
1722 def: InstRW<[HWWriteResGroup13], (instregex "PMOVSXBWrm")>;
1723 def: InstRW<[HWWriteResGroup13], (instregex "PMOVSXDQrm")>;
1724 def: InstRW<[HWWriteResGroup13], (instregex "PMOVSXWDrm")>;
1725 def: InstRW<[HWWriteResGroup13], (instregex "PMOVSXWQrm")>;
1726 def: InstRW<[HWWriteResGroup13], (instregex "PMOVZXBDrm")>;
1727 def: InstRW<[HWWriteResGroup13], (instregex "PMOVZXBQrm")>;
1728 def: InstRW<[HWWriteResGroup13], (instregex "PMOVZXBWrm")>;
1729 def: InstRW<[HWWriteResGroup13], (instregex "PMOVZXDQrm")>;
1730 def: InstRW<[HWWriteResGroup13], (instregex "PMOVZXWDrm")>;
1731 def: InstRW<[HWWriteResGroup13], (instregex "PMOVZXWQrm")>;
1732 def: InstRW<[HWWriteResGroup13], (instregex "PSHUFBrm")>;
1733 def: InstRW<[HWWriteResGroup13], (instregex "PSHUFDmi")>;
1734 def: InstRW<[HWWriteResGroup13], (instregex "PSHUFHWmi")>;
1735 def: InstRW<[HWWriteResGroup13], (instregex "PSHUFLWmi")>;
1736 def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKHBWrm")>;
1737 def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKHDQrm")>;
1738 def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKHQDQrm")>;
1739 def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKHWDrm")>;
1740 def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLBWrm")>;
1741 def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLDQrm")>;
1742 def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLQDQrm")>;
1743 def: InstRW<[HWWriteResGroup13], (instregex "PUNPCKLWDrm")>;
1744 def: InstRW<[HWWriteResGroup13], (instregex "SHUFPDrmi")>;
1745 def: InstRW<[HWWriteResGroup13], (instregex "SHUFPSrmi")>;
1746 def: InstRW<[HWWriteResGroup13], (instregex "UNPCKHPDrm")>;
1747 def: InstRW<[HWWriteResGroup13], (instregex "UNPCKHPSrm")>;
1748 def: InstRW<[HWWriteResGroup13], (instregex "UNPCKLPDrm")>;
1749 def: InstRW<[HWWriteResGroup13], (instregex "UNPCKLPSrm")>;
1750 def: InstRW<[HWWriteResGroup13], (instregex "VANDNPDYrm")>;
1751 def: InstRW<[HWWriteResGroup13], (instregex "VANDNPDrm")>;
1752 def: InstRW<[HWWriteResGroup13], (instregex "VANDNPSYrm")>;
1753 def: InstRW<[HWWriteResGroup13], (instregex "VANDNPSrm")>;
1754 def: InstRW<[HWWriteResGroup13], (instregex "VANDPDYrm")>;
1755 def: InstRW<[HWWriteResGroup13], (instregex "VANDPDrm")>;
1756 def: InstRW<[HWWriteResGroup13], (instregex "VANDPSYrm")>;
1757 def: InstRW<[HWWriteResGroup13], (instregex "VANDPSrm")>;
1758 def: InstRW<[HWWriteResGroup13], (instregex "VINSERTPSrm")>;
1759 def: InstRW<[HWWriteResGroup13], (instregex "VMOVHPDrm")>;
1760 def: InstRW<[HWWriteResGroup13], (instregex "VMOVHPSrm")>;
1761 def: InstRW<[HWWriteResGroup13], (instregex "VMOVLPDrm")>;
1762 def: InstRW<[HWWriteResGroup13], (instregex "VMOVLPSrm")>;
1763 def: InstRW<[HWWriteResGroup13], (instregex "VORPDYrm")>;
1764 def: InstRW<[HWWriteResGroup13], (instregex "VORPDrm")>;
1765 def: InstRW<[HWWriteResGroup13], (instregex "VORPSYrm")>;
1766 def: InstRW<[HWWriteResGroup13], (instregex "VORPSrm")>;
1767 def: InstRW<[HWWriteResGroup13], (instregex "VPACKSSDWYrm")>;
1768 def: InstRW<[HWWriteResGroup13], (instregex "VPACKSSDWrm")>;
1769 def: InstRW<[HWWriteResGroup13], (instregex "VPACKSSWBYrm")>;
1770 def: InstRW<[HWWriteResGroup13], (instregex "VPACKSSWBrm")>;
1771 def: InstRW<[HWWriteResGroup13], (instregex "VPACKUSDWYrm")>;
1772 def: InstRW<[HWWriteResGroup13], (instregex "VPACKUSDWrm")>;
1773 def: InstRW<[HWWriteResGroup13], (instregex "VPACKUSWBYrm")>;
1774 def: InstRW<[HWWriteResGroup13], (instregex "VPACKUSWBrm")>;
1775 def: InstRW<[HWWriteResGroup13], (instregex "VPALIGNRYrmi")>;
1776 def: InstRW<[HWWriteResGroup13], (instregex "VPALIGNRrmi")>;
1777 def: InstRW<[HWWriteResGroup13], (instregex "VPBLENDWYrmi")>;
1778 def: InstRW<[HWWriteResGroup13], (instregex "VPBLENDWrmi")>;
1779 def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPDYmi")>;
1780 def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPDYrm")>;
1781 def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPDmi")>;
1782 def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPDrm")>;
1783 def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPSYmi")>;
1784 def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPSYrm")>;
1785 def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPSmi")>;
1786 def: InstRW<[HWWriteResGroup13], (instregex "VPERMILPSrm")>;
1787 def: InstRW<[HWWriteResGroup13], (instregex "VPINSRBrm")>;
1788 def: InstRW<[HWWriteResGroup13], (instregex "VPINSRDrm")>;
1789 def: InstRW<[HWWriteResGroup13], (instregex "VPINSRQrm")>;
1790 def: InstRW<[HWWriteResGroup13], (instregex "VPINSRWrmi")>;
1791 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVSXBDrm")>;
1792 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVSXBQrm")>;
1793 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVSXBWrm")>;
1794 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVSXDQrm")>;
1795 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVSXWDrm")>;
1796 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVSXWQrm")>;
1797 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVZXBDrm")>;
1798 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVZXBQrm")>;
1799 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVZXBWrm")>;
1800 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVZXDQrm")>;
1801 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVZXWDrm")>;
1802 def: InstRW<[HWWriteResGroup13], (instregex "VPMOVZXWQrm")>;
1803 def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFBYrm")>;
1804 def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFBrm")>;
1805 def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFDYmi")>;
1806 def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFDmi")>;
1807 def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFHWYmi")>;
1808 def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFHWmi")>;
1809 def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFLWYmi")>;
1810 def: InstRW<[HWWriteResGroup13], (instregex "VPSHUFLWmi")>;
1811 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHBWYrm")>;
1812 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHBWrm")>;
1813 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHDQYrm")>;
1814 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHDQrm")>;
1815 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHQDQYrm")>;
1816 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHQDQrm")>;
1817 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHWDYrm")>;
1818 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKHWDrm")>;
1819 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLBWYrm")>;
1820 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLBWrm")>;
1821 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLDQYrm")>;
1822 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLDQrm")>;
1823 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLQDQYrm")>;
1824 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLQDQrm")>;
1825 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLWDYrm")>;
1826 def: InstRW<[HWWriteResGroup13], (instregex "VPUNPCKLWDrm")>;
1827 def: InstRW<[HWWriteResGroup13], (instregex "VSHUFPDYrmi")>;
1828 def: InstRW<[HWWriteResGroup13], (instregex "VSHUFPDrmi")>;
1829 def: InstRW<[HWWriteResGroup13], (instregex "VSHUFPSYrmi")>;
1830 def: InstRW<[HWWriteResGroup13], (instregex "VSHUFPSrmi")>;
1831 def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKHPDYrm")>;
1832 def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKHPDrm")>;
1833 def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKHPSYrm")>;
1834 def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKHPSrm")>;
1835 def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKLPDYrm")>;
1836 def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKLPDrm")>;
1837 def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKLPSYrm")>;
1838 def: InstRW<[HWWriteResGroup13], (instregex "VUNPCKLPSrm")>;
1839 def: InstRW<[HWWriteResGroup13], (instregex "VXORPDYrm")>;
1840 def: InstRW<[HWWriteResGroup13], (instregex "VXORPDrm")>;
1841 def: InstRW<[HWWriteResGroup13], (instregex "VXORPSYrm")>;
1842 def: InstRW<[HWWriteResGroup13], (instregex "VXORPSrm")>;
1843 def: InstRW<[HWWriteResGroup13], (instregex "XORPDrm")>;
1844 def: InstRW<[HWWriteResGroup13], (instregex "XORPSrm")>;
1845
1846 def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
1847 let Latency = 1;
1848 let NumMicroOps = 2;
1849 let ResourceCycles = [1,1];
1850 }
1851 def: InstRW<[HWWriteResGroup14], (instregex "FARJMP64")>;
1852 def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
1853
1854 def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> {
1855 let Latency = 1;
1856 let NumMicroOps = 2;
1857 let ResourceCycles = [1,1];
1858 }
1859 def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>;
1860 def: InstRW<[HWWriteResGroup15], (instregex "RORX32mi")>;
1861 def: InstRW<[HWWriteResGroup15], (instregex "RORX64mi")>;
1862 def: InstRW<[HWWriteResGroup15], (instregex "SARX32rm")>;
1863 def: InstRW<[HWWriteResGroup15], (instregex "SARX64rm")>;
1864 def: InstRW<[HWWriteResGroup15], (instregex "SHLX32rm")>;
1865 def: InstRW<[HWWriteResGroup15], (instregex "SHLX64rm")>;
1866 def: InstRW<[HWWriteResGroup15], (instregex "SHRX32rm")>;
1867 def: InstRW<[HWWriteResGroup15], (instregex "SHRX64rm")>;
1868
1869 def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
1870 let Latency = 1;
1871 let NumMicroOps = 2;
1872 let ResourceCycles = [1,1];
1873 }
1874 def: InstRW<[HWWriteResGroup16], (instregex "ANDN32rm")>;
1875 def: InstRW<[HWWriteResGroup16], (instregex "ANDN64rm")>;
1876 def: InstRW<[HWWriteResGroup16], (instregex "BLSI32rm")>;
1877 def: InstRW<[HWWriteResGroup16], (instregex "BLSI64rm")>;
1878 def: InstRW<[HWWriteResGroup16], (instregex "BLSMSK32rm")>;
1879 def: InstRW<[HWWriteResGroup16], (instregex "BLSMSK64rm")>;
1880 def: InstRW<[HWWriteResGroup16], (instregex "BLSR32rm")>;
1881 def: InstRW<[HWWriteResGroup16], (instregex "BLSR64rm")>;
1882 def: InstRW<[HWWriteResGroup16], (instregex "BZHI32rm")>;
1883 def: InstRW<[HWWriteResGroup16], (instregex "BZHI64rm")>;
1884 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSBrm64")>;
1885 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSDrm64")>;
1886 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PABSWrm64")>;
1887 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDBirm")>;
1888 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDDirm")>;
1889 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDQirm")>;
1890 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDSBirm")>;
1891 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDSWirm")>;
1892 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDUSBirm")>;
1893 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDUSWirm")>;
1894 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PADDWirm")>;
1895 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PAVGBirm")>;
1896 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PAVGWirm")>;
1897 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPEQBirm")>;
1898 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPEQDirm")>;
1899 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPEQWirm")>;
1900 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPGTBirm")>;
1901 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPGTDirm")>;
1902 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PCMPGTWirm")>;
1903 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMAXSWirm")>;
1904 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMAXUBirm")>;
1905 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMINSWirm")>;
1906 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PMINUBirm")>;
1907 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNBrm64")>;
1908 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNDrm64")>;
1909 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSIGNWrm64")>;
1910 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBBirm")>;
1911 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBDirm")>;
1912 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBQirm")>;
1913 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBSBirm")>;
1914 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBSWirm")>;
1915 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBUSBirm")>;
1916 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBUSWirm")>;
1917 def: InstRW<[HWWriteResGroup16], (instregex "MMX_PSUBWirm")>;
1918 def: InstRW<[HWWriteResGroup16], (instregex "MOVBE(16|32|64)rm")>;
1919 def: InstRW<[HWWriteResGroup16], (instregex "PABSBrm")>;
1920 def: InstRW<[HWWriteResGroup16], (instregex "PABSDrm")>;
1921 def: InstRW<[HWWriteResGroup16], (instregex "PABSWrm")>;
1922 def: InstRW<[HWWriteResGroup16], (instregex "PADDBrm")>;
1923 def: InstRW<[HWWriteResGroup16], (instregex "PADDDrm")>;
1924 def: InstRW<[HWWriteResGroup16], (instregex "PADDQrm")>;
1925 def: InstRW<[HWWriteResGroup16], (instregex "PADDSBrm")>;
1926 def: InstRW<[HWWriteResGroup16], (instregex "PADDSWrm")>;
1927 def: InstRW<[HWWriteResGroup16], (instregex "PADDUSBrm")>;
1928 def: InstRW<[HWWriteResGroup16], (instregex "PADDUSWrm")>;
1929 def: InstRW<[HWWriteResGroup16], (instregex "PADDWrm")>;
1930 def: InstRW<[HWWriteResGroup16], (instregex "PAVGBrm")>;
1931 def: InstRW<[HWWriteResGroup16], (instregex "PAVGWrm")>;
1932 def: InstRW<[HWWriteResGroup16], (instregex "PCMPEQBrm")>;
1933 def: InstRW<[HWWriteResGroup16], (instregex "PCMPEQDrm")>;
1934 def: InstRW<[HWWriteResGroup16], (instregex "PCMPEQQrm")>;
1935 def: InstRW<[HWWriteResGroup16], (instregex "PCMPEQWrm")>;
1936 def: InstRW<[HWWriteResGroup16], (instregex "PCMPGTBrm")>;
1937 def: InstRW<[HWWriteResGroup16], (instregex "PCMPGTDrm")>;
1938 def: InstRW<[HWWriteResGroup16], (instregex "PCMPGTWrm")>;
1939 def: InstRW<[HWWriteResGroup16], (instregex "PMAXSBrm")>;
1940 def: InstRW<[HWWriteResGroup16], (instregex "PMAXSDrm")>;
1941 def: InstRW<[HWWriteResGroup16], (instregex "PMAXSWrm")>;
1942 def: InstRW<[HWWriteResGroup16], (instregex "PMAXUBrm")>;
1943 def: InstRW<[HWWriteResGroup16], (instregex "PMAXUDrm")>;
1944 def: InstRW<[HWWriteResGroup16], (instregex "PMAXUWrm")>;
1945 def: InstRW<[HWWriteResGroup16], (instregex "PMINSBrm")>;
1946 def: InstRW<[HWWriteResGroup16], (instregex "PMINSDrm")>;
1947 def: InstRW<[HWWriteResGroup16], (instregex "PMINSWrm")>;
1948 def: InstRW<[HWWriteResGroup16], (instregex "PMINUBrm")>;
1949 def: InstRW<[HWWriteResGroup16], (instregex "PMINUDrm")>;
1950 def: InstRW<[HWWriteResGroup16], (instregex "PMINUWrm")>;
1951 def: InstRW<[HWWriteResGroup16], (instregex "PSIGNBrm128")>;
1952 def: InstRW<[HWWriteResGroup16], (instregex "PSIGNDrm128")>;
1953 def: InstRW<[HWWriteResGroup16], (instregex "PSIGNWrm128")>;
1954 def: InstRW<[HWWriteResGroup16], (instregex "PSUBBrm")>;
1955 def: InstRW<[HWWriteResGroup16], (instregex "PSUBDrm")>;
1956 def: InstRW<[HWWriteResGroup16], (instregex "PSUBQrm")>;
1957 def: InstRW<[HWWriteResGroup16], (instregex "PSUBSBrm")>;
1958 def: InstRW<[HWWriteResGroup16], (instregex "PSUBSWrm")>;
1959 def: InstRW<[HWWriteResGroup16], (instregex "PSUBUSBrm")>;
1960 def: InstRW<[HWWriteResGroup16], (instregex "PSUBUSWrm")>;
1961 def: InstRW<[HWWriteResGroup16], (instregex "PSUBWrm")>;
1962 def: InstRW<[HWWriteResGroup16], (instregex "VPABSBYrm")>;
1963 def: InstRW<[HWWriteResGroup16], (instregex "VPABSBrm")>;
1964 def: InstRW<[HWWriteResGroup16], (instregex "VPABSDYrm")>;
1965 def: InstRW<[HWWriteResGroup16], (instregex "VPABSDrm")>;
1966 def: InstRW<[HWWriteResGroup16], (instregex "VPABSWYrm")>;
1967 def: InstRW<[HWWriteResGroup16], (instregex "VPABSWrm")>;
1968 def: InstRW<[HWWriteResGroup16], (instregex "VPADDBYrm")>;
1969 def: InstRW<[HWWriteResGroup16], (instregex "VPADDBrm")>;
1970 def: InstRW<[HWWriteResGroup16], (instregex "VPADDDYrm")>;
1971 def: InstRW<[HWWriteResGroup16], (instregex "VPADDDrm")>;
1972 def: InstRW<[HWWriteResGroup16], (instregex "VPADDQYrm")>;
1973 def: InstRW<[HWWriteResGroup16], (instregex "VPADDQrm")>;
1974 def: InstRW<[HWWriteResGroup16], (instregex "VPADDSBYrm")>;
1975 def: InstRW<[HWWriteResGroup16], (instregex "VPADDSBrm")>;
1976 def: InstRW<[HWWriteResGroup16], (instregex "VPADDSWYrm")>;
1977 def: InstRW<[HWWriteResGroup16], (instregex "VPADDSWrm")>;
1978 def: InstRW<[HWWriteResGroup16], (instregex "VPADDUSBYrm")>;
1979 def: InstRW<[HWWriteResGroup16], (instregex "VPADDUSBrm")>;
1980 def: InstRW<[HWWriteResGroup16], (instregex "VPADDUSWYrm")>;
1981 def: InstRW<[HWWriteResGroup16], (instregex "VPADDUSWrm")>;
1982 def: InstRW<[HWWriteResGroup16], (instregex "VPADDWYrm")>;
1983 def: InstRW<[HWWriteResGroup16], (instregex "VPADDWrm")>;
1984 def: InstRW<[HWWriteResGroup16], (instregex "VPAVGBYrm")>;
1985 def: InstRW<[HWWriteResGroup16], (instregex "VPAVGBrm")>;
1986 def: InstRW<[HWWriteResGroup16], (instregex "VPAVGWYrm")>;
1987 def: InstRW<[HWWriteResGroup16], (instregex "VPAVGWrm")>;
1988 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPEQBYrm")>;
1989 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPEQBrm")>;
1990 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPEQDYrm")>;
1991 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPEQDrm")>;
1992 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPEQQYrm")>;
1993 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPEQQrm")>;
1994 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPEQWYrm")>;
1995 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPEQWrm")>;
1996 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPGTBYrm")>;
1997 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPGTBrm")>;
1998 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPGTDYrm")>;
1999 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPGTDrm")>;
2000 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPGTWYrm")>;
2001 def: InstRW<[HWWriteResGroup16], (instregex "VPCMPGTWrm")>;
2002 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXSBYrm")>;
2003 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXSBrm")>;
2004 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXSDYrm")>;
2005 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXSDrm")>;
2006 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXSWYrm")>;
2007 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXSWrm")>;
2008 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXUBYrm")>;
2009 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXUBrm")>;
2010 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXUDYrm")>;
2011 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXUDrm")>;
2012 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXUWYrm")>;
2013 def: InstRW<[HWWriteResGroup16], (instregex "VPMAXUWrm")>;
2014 def: InstRW<[HWWriteResGroup16], (instregex "VPMINSBYrm")>;
2015 def: InstRW<[HWWriteResGroup16], (instregex "VPMINSBrm")>;
2016 def: InstRW<[HWWriteResGroup16], (instregex "VPMINSDYrm")>;
2017 def: InstRW<[HWWriteResGroup16], (instregex "VPMINSDrm")>;
2018 def: InstRW<[HWWriteResGroup16], (instregex "VPMINSWYrm")>;
2019 def: InstRW<[HWWriteResGroup16], (instregex "VPMINSWrm")>;
2020 def: InstRW<[HWWriteResGroup16], (instregex "VPMINUBYrm")>;
2021 def: InstRW<[HWWriteResGroup16], (instregex "VPMINUBrm")>;
2022 def: InstRW<[HWWriteResGroup16], (instregex "VPMINUDYrm")>;
2023 def: InstRW<[HWWriteResGroup16], (instregex "VPMINUDrm")>;
2024 def: InstRW<[HWWriteResGroup16], (instregex "VPMINUWYrm")>;
2025 def: InstRW<[HWWriteResGroup16], (instregex "VPMINUWrm")>;
2026 def: InstRW<[HWWriteResGroup16], (instregex "VPSIGNBYrm256")>;
2027 def: InstRW<[HWWriteResGroup16], (instregex "VPSIGNBrm128")>;
2028 def: InstRW<[HWWriteResGroup16], (instregex "VPSIGNDYrm256")>;
2029 def: InstRW<[HWWriteResGroup16], (instregex "VPSIGNDrm128")>;
2030 def: InstRW<[HWWriteResGroup16], (instregex "VPSIGNWYrm256")>;
2031 def: InstRW<[HWWriteResGroup16], (instregex "VPSIGNWrm128")>;
2032 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBBYrm")>;
2033 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBBrm")>;
2034 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBDYrm")>;
2035 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBDrm")>;
2036 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBQYrm")>;
2037 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBQrm")>;
2038 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBSBYrm")>;
2039 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBSBrm")>;
2040 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBSWYrm")>;
2041 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBSWrm")>;
2042 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBUSBYrm")>;
2043 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBUSBrm")>;
2044 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBUSWYrm")>;
2045 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBUSWrm")>;
2046 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBWYrm")>;
2047 def: InstRW<[HWWriteResGroup16], (instregex "VPSUBWrm")>;
2048
2049 def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> {
2050 let Latency = 1;
2051 let NumMicroOps = 2;
2052 let ResourceCycles = [1,1];
2053 }
2054 def: InstRW<[HWWriteResGroup17], (instregex "BLENDPDrmi")>;
2055 def: InstRW<[HWWriteResGroup17], (instregex "BLENDPSrmi")>;
2056 def: InstRW<[HWWriteResGroup17], (instregex "MMX_PANDNirm")>;
2057 def: InstRW<[HWWriteResGroup17], (instregex "MMX_PANDirm")>;
2058 def: InstRW<[HWWriteResGroup17], (instregex "MMX_PORirm")>;
2059 def: InstRW<[HWWriteResGroup17], (instregex "MMX_PXORirm")>;
2060 def: InstRW<[HWWriteResGroup17], (instregex "PANDNrm")>;
2061 def: InstRW<[HWWriteResGroup17], (instregex "PANDrm")>;
2062 def: InstRW<[HWWriteResGroup17], (instregex "PORrm")>;
2063 def: InstRW<[HWWriteResGroup17], (instregex "PXORrm")>;
2064 def: InstRW<[HWWriteResGroup17], (instregex "VBLENDPDYrmi")>;
2065 def: InstRW<[HWWriteResGroup17], (instregex "VBLENDPDrmi")>;
2066 def: InstRW<[HWWriteResGroup17], (instregex "VBLENDPSYrmi")>;
2067 def: InstRW<[HWWriteResGroup17], (instregex "VBLENDPSrmi")>;
2068 def: InstRW<[HWWriteResGroup17], (instregex "VINSERTF128rm")>;
2069 def: InstRW<[HWWriteResGroup17], (instregex "VINSERTI128rm")>;
2070 def: InstRW<[HWWriteResGroup17], (instregex "VPANDNYrm")>;
2071 def: InstRW<[HWWriteResGroup17], (instregex "VPANDNrm")>;
2072 def: InstRW<[HWWriteResGroup17], (instregex "VPANDYrm")>;
2073 def: InstRW<[HWWriteResGroup17], (instregex "VPANDrm")>;
2074 def: InstRW<[HWWriteResGroup17], (instregex "VPBLENDDYrmi")>;
2075 def: InstRW<[HWWriteResGroup17], (instregex "VPBLENDDrmi")>;
2076 def: InstRW<[HWWriteResGroup17], (instregex "VPORYrm")>;
2077 def: InstRW<[HWWriteResGroup17], (instregex "VPORrm")>;
2078 def: InstRW<[HWWriteResGroup17], (instregex "VPXORYrm")>;
2079 def: InstRW<[HWWriteResGroup17], (instregex "VPXORrm")>;
2080
2081 def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> {
2082 let Latency = 1;
2083 let NumMicroOps = 2;
2084 let ResourceCycles = [1,1];
2085 }
2086 def: InstRW<[HWWriteResGroup18], (instregex "ADD(16|32|64)rm")>;
2087 def: InstRW<[HWWriteResGroup18], (instregex "ADD8rm")>;
2088 def: InstRW<[HWWriteResGroup18], (instregex "AND(16|32|64)rm")>;
2089 def: InstRW<[HWWriteResGroup18], (instregex "AND8rm")>;
2090 def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mi8")>;
2091 def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)mr")>;
2092 def: InstRW<[HWWriteResGroup18], (instregex "CMP(16|32|64)rm")>;
2093 def: InstRW<[HWWriteResGroup18], (instregex "CMP8mi")>;
2094 def: InstRW<[HWWriteResGroup18], (instregex "CMP8mr")>;
2095 def: InstRW<[HWWriteResGroup18], (instregex "CMP8rm")>;
2096 def: InstRW<[HWWriteResGroup18], (instregex "OR(16|32|64)rm")>;
2097 def: InstRW<[HWWriteResGroup18], (instregex "OR8rm")>;
2098 def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)r(mr?)")>;
2099 def: InstRW<[HWWriteResGroup18], (instregex "SUB(16|32|64)rm")>;
2100 def: InstRW<[HWWriteResGroup18], (instregex "SUB8rm")>;
2101 def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)rm")>;
2102 def: InstRW<[HWWriteResGroup18], (instregex "TEST8mi")>;
2103 def: InstRW<[HWWriteResGroup18], (instregex "TEST8rm")>;
2104 def: InstRW<[HWWriteResGroup18], (instregex "XOR(16|32|64)rm")>;
2105 def: InstRW<[HWWriteResGroup18], (instregex "XOR8rm")>;
2106
2107 def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> {
2108 let Latency = 1;
2109 let NumMicroOps = 2;
2110 let ResourceCycles = [1,1];
2111 }
2112 def: InstRW<[HWWriteResGroup19], (instregex "SFENCE")>;
2113
2114 def HWWriteResGroup20 : SchedWriteRes<[HWPort4,HWPort5,HWPort237]> {
2115 let Latency = 1;
2116 let NumMicroOps = 3;
2117 let ResourceCycles = [1,1,1];
2118 }
2119 def: InstRW<[HWWriteResGroup20], (instregex "EXTRACTPSmr")>;
2120 def: InstRW<[HWWriteResGroup20], (instregex "PEXTRBmr")>;
2121 def: InstRW<[HWWriteResGroup20], (instregex "PEXTRDmr")>;
2122 def: InstRW<[HWWriteResGroup20], (instregex "PEXTRQmr")>;
2123 def: InstRW<[HWWriteResGroup20], (instregex "PEXTRWmr")>;
2124 def: InstRW<[HWWriteResGroup20], (instregex "STMXCSR")>;
2125 def: InstRW<[HWWriteResGroup20], (instregex "VEXTRACTPSmr")>;
2126 def: InstRW<[HWWriteResGroup20], (instregex "VPEXTRBmr")>;
2127 def: InstRW<[HWWriteResGroup20], (instregex "VPEXTRDmr")>;
2128 def: InstRW<[HWWriteResGroup20], (instregex "VPEXTRQmr")>;
2129 def: InstRW<[HWWriteResGroup20], (instregex "VPEXTRWmr")>;
2130 def: InstRW<[HWWriteResGroup20], (instregex "VSTMXCSR")>;
2131
2132 def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> {
2133 let Latency = 1;
2134 let NumMicroOps = 3;
2135 let ResourceCycles = [1,1,1];
2136 }
2137 def: InstRW<[HWWriteResGroup21], (instregex "FNSTCW16m")>;
2138
2139 def HWWriteResGroup22 : SchedWriteRes<[HWPort4,HWPort237,HWPort06]> {
2140 let Latency = 1;
2141 let NumMicroOps = 3;
2142 let ResourceCycles = [1,1,1];
2143 }
2144 def: InstRW<[HWWriteResGroup22], (instregex "SETAEm")>;
2145 def: InstRW<[HWWriteResGroup22], (instregex "SETBm")>;
2146 def: InstRW<[HWWriteResGroup22], (instregex "SETEm")>;
2147 def: InstRW<[HWWriteResGroup22], (instregex "SETGEm")>;
2148 def: InstRW<[HWWriteResGroup22], (instregex "SETGm")>;
2149 def: InstRW<[HWWriteResGroup22], (instregex "SETLEm")>;
2150 def: InstRW<[HWWriteResGroup22], (instregex "SETLm")>;
2151 def: InstRW<[HWWriteResGroup22], (instregex "SETNEm")>;
2152 def: InstRW<[HWWriteResGroup22], (instregex "SETNOm")>;
2153 def: InstRW<[HWWriteResGroup22], (instregex "SETNPm")>;
2154 def: InstRW<[HWWriteResGroup22], (instregex "SETNSm")>;
2155 def: InstRW<[HWWriteResGroup22], (instregex "SETOm")>;
2156 def: InstRW<[HWWriteResGroup22], (instregex "SETPm")>;
2157 def: InstRW<[HWWriteResGroup22], (instregex "SETSm")>;
2158
2159 def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> {
2160 let Latency = 1;
2161 let NumMicroOps = 3;
2162 let ResourceCycles = [1,1,1];
2163 }
2164 def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>;
2165
2166 def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
2167 let Latency = 1;
2168 let NumMicroOps = 3;
2169 let ResourceCycles = [1,1,1];
2170 }
2171 def: InstRW<[HWWriteResGroup23_16], (instregex "MOVBE16mr")>;
2172
2173 def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> {
2174 let Latency = 1;
2175 let NumMicroOps = 3;
2176 let ResourceCycles = [1,1,1];
2177 }
2178 def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)r(mr?)")>;
2179 def: InstRW<[HWWriteResGroup24], (instregex "PUSH64i8")>;
2180 def: InstRW<[HWWriteResGroup24], (instregex "STOSB")>;
2181 def: InstRW<[HWWriteResGroup24], (instregex "STOSL")>;
2182 def: InstRW<[HWWriteResGroup24], (instregex "STOSQ")>;
2183 def: InstRW<[HWWriteResGroup24], (instregex "STOSW")>;
2184
2185 def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
2186 let Latency = 1;
2187 let NumMicroOps = 4;
2188 let ResourceCycles = [1,1,1,1];
2189 }
2190 def: InstRW<[HWWriteResGroup25], (instregex "BTC(16|32|64)mi8")>;
2191 def: InstRW<[HWWriteResGroup25], (instregex "BTR(16|32|64)mi8")>;
2192 def: InstRW<[HWWriteResGroup25], (instregex "BTS(16|32|64)mi8")>;
2193 def: InstRW<[HWWriteResGroup25], (instregex "SAR(16|32|64)m1")>;
2194 def: InstRW<[HWWriteResGroup25], (instregex "SAR(16|32|64)mi")>;
2195 def: InstRW<[HWWriteResGroup25], (instregex "SAR8m1")>;
2196 def: InstRW<[HWWriteResGroup25], (instregex "SAR8mi")>;
2197 def: InstRW<[HWWriteResGroup25], (instregex "SHL(16|32|64)m1")>;
2198 def: InstRW<[HWWriteResGroup25], (instregex "SHL(16|32|64)mi")>;
2199 def: InstRW<[HWWriteResGroup25], (instregex "SHL8m1")>;
2200 def: InstRW<[HWWriteResGroup25], (instregex "SHL8mi")>;
2201 def: InstRW<[HWWriteResGroup25], (instregex "SHR(16|32|64)m1")>;
2202 def: InstRW<[HWWriteResGroup25], (instregex "SHR(16|32|64)mi")>;
2203 def: InstRW<[HWWriteResGroup25], (instregex "SHR8m1")>;
2204 def: InstRW<[HWWriteResGroup25], (instregex "SHR8mi")>;
2205
2206 def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
2207 let Latency = 1;
2208 let NumMicroOps = 4;
2209 let ResourceCycles = [1,1,1,1];
2210 }
2211 def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mi8")>;
2212 def: InstRW<[HWWriteResGroup26], (instregex "ADD(16|32|64)mr")>;
2213 def: InstRW<[HWWriteResGroup26], (instregex "ADD8mi")>;
2214 def: InstRW<[HWWriteResGroup26], (instregex "ADD8mr")>;
2215 def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mi8")>;
2216 def: InstRW<[HWWriteResGroup26], (instregex "AND(16|32|64)mr")>;
2217 def: InstRW<[HWWriteResGroup26], (instregex "AND8mi")>;
2218 def: InstRW<[HWWriteResGroup26], (instregex "AND8mr")>;
2219 def: InstRW<[HWWriteResGroup26], (instregex "DEC(16|32|64)m")>;
2220 def: InstRW<[HWWriteResGroup26], (instregex "DEC8m")>;
2221 def: InstRW<[HWWriteResGroup26], (instregex "INC(16|32|64)m")>;
2222 def: InstRW<[HWWriteResGroup26], (instregex "INC8m")>;
2223 def: InstRW<[HWWriteResGroup26], (instregex "NEG(16|32|64)m")>;
2224 def: InstRW<[HWWriteResGroup26], (instregex "NEG8m")>;
2225 def: InstRW<[HWWriteResGroup26], (instregex "NOT(16|32|64)m")>;
2226 def: InstRW<[HWWriteResGroup26], (instregex "NOT8m")>;
2227 def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mi8")>;
2228 def: InstRW<[HWWriteResGroup26], (instregex "OR(16|32|64)mr")>;
2229 def: InstRW<[HWWriteResGroup26], (instregex "OR8mi")>;
2230 def: InstRW<[HWWriteResGroup26], (instregex "OR8mr")>;
2231 def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mi8")>;
2232 def: InstRW<[HWWriteResGroup26], (instregex "SUB(16|32|64)mr")>;
2233 def: InstRW<[HWWriteResGroup26], (instregex "SUB8mi")>;
2234 def: InstRW<[HWWriteResGroup26], (instregex "SUB8mr")>;
2235 def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mi8")>;
2236 def: InstRW<[HWWriteResGroup26], (instregex "XOR(16|32|64)mr")>;
2237 def: InstRW<[HWWriteResGroup26], (instregex "XOR8mi")>;
2238 def: InstRW<[HWWriteResGroup26], (instregex "XOR8mr")>;
2239
2240 def HWWriteResGroup27 : SchedWriteRes<[HWPort5]> {
2241 let Latency = 2;
2242 let NumMicroOps = 2;
2243 let ResourceCycles = [2];
2244 }
2245 def: InstRW<[HWWriteResGroup27], (instregex "BLENDVPDrr0")>;
2246 def: InstRW<[HWWriteResGroup27], (instregex "BLENDVPSrr0")>;
2247 def: InstRW<[HWWriteResGroup27], (instregex "MMX_PINSRWirri")>;
2248 def: InstRW<[HWWriteResGroup27], (instregex "PBLENDVBrr0")>;
2249 def: InstRW<[HWWriteResGroup27], (instregex "PINSRBrr")>;
2250 def: InstRW<[HWWriteResGroup27], (instregex "PINSRDrr")>;
2251 def: InstRW<[HWWriteResGroup27], (instregex "PINSRQrr")>;
2252 def: InstRW<[HWWriteResGroup27], (instregex "PINSRWrri")>;
2253 def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPDYrr")>;
2254 def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPDrr")>;
2255 def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPSYrr")>;
2256 def: InstRW<[HWWriteResGroup27], (instregex "VBLENDVPSrr")>;
2257 def: InstRW<[HWWriteResGroup27], (instregex "VPBLENDVBYrr")>;
2258 def: InstRW<[HWWriteResGroup27], (instregex "VPBLENDVBrr")>;
2259 def: InstRW<[HWWriteResGroup27], (instregex "VPINSRBrr")>;
2260 def: InstRW<[HWWriteResGroup27], (instregex "VPINSRDrr")>;
2261 def: InstRW<[HWWriteResGroup27], (instregex "VPINSRQrr")>;
2262 def: InstRW<[HWWriteResGroup27], (instregex "VPINSRWrri")>;
2263
2264 def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> {
2265 let Latency = 2;
2266 let NumMicroOps = 2;
2267 let ResourceCycles = [2];
2268 }
2269 def: InstRW<[HWWriteResGroup28], (instregex "FDECSTP")>;
2270
2271 def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> {
2272 let Latency = 2;
2273 let NumMicroOps = 2;
2274 let ResourceCycles = [2];
2275 }
2276 def: InstRW<[HWWriteResGroup29], (instregex "ROL(16|32|64)r1")>;
2277 def: InstRW<[HWWriteResGroup29], (instregex "ROL(16|32|64)ri")>;
2278 def: InstRW<[HWWriteResGroup29], (instregex "ROL8r1")>;
2279 def: InstRW<[HWWriteResGroup29], (instregex "ROL8ri")>;
2280 def: InstRW<[HWWriteResGroup29], (instregex "ROR(16|32|64)r1")>;
2281 def: InstRW<[HWWriteResGroup29], (instregex "ROR(16|32|64)ri")>;
2282 def: InstRW<[HWWriteResGroup29], (instregex "ROR8r1")>;
2283 def: InstRW<[HWWriteResGroup29], (instregex "ROR8ri")>;
2284
2285 def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
2286 let Latency = 2;
2287 let NumMicroOps = 2;
2288 let ResourceCycles = [2];
2289 }
2290 def: InstRW<[HWWriteResGroup30], (instregex "LFENCE")>;
2291 def: InstRW<[HWWriteResGroup30], (instregex "MFENCE")>;
2292 def: InstRW<[HWWriteResGroup30], (instregex "WAIT")>;
2293 def: InstRW<[HWWriteResGroup30], (instregex "XGETBV")>;
2294
2295 def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> {
2296 let Latency = 2;
2297 let NumMicroOps = 2;
2298 let ResourceCycles = [1,1];
2299 }
2300 def: InstRW<[HWWriteResGroup31], (instregex "CVTPS2PDrr")>;
2301 def: InstRW<[HWWriteResGroup31], (instregex "CVTSS2SDrr")>;
2302 def: InstRW<[HWWriteResGroup31], (instregex "EXTRACTPSrr")>;
2303 def: InstRW<[HWWriteResGroup31], (instregex "MMX_PEXTRWirri")>;
2304 def: InstRW<[HWWriteResGroup31], (instregex "PEXTRBrr")>;
2305 def: InstRW<[HWWriteResGroup31], (instregex "PEXTRDrr")>;
2306 def: InstRW<[HWWriteResGroup31], (instregex "PEXTRQrr")>;
2307 def: InstRW<[HWWriteResGroup31], (instregex "PEXTRWri")>;
2308 def: InstRW<[HWWriteResGroup31], (instregex "PEXTRWrr_REV")>;
2309 def: InstRW<[HWWriteResGroup31], (instregex "PSLLDrr")>;
2310 def: InstRW<[HWWriteResGroup31], (instregex "PSLLQrr")>;
2311 def: InstRW<[HWWriteResGroup31], (instregex "PSLLWrr")>;
2312 def: InstRW<[HWWriteResGroup31], (instregex "PSRADrr")>;
2313 def: InstRW<[HWWriteResGroup31], (instregex "PSRAWrr")>;
2314 def: InstRW<[HWWriteResGroup31], (instregex "PSRLDrr")>;
2315 def: InstRW<[HWWriteResGroup31], (instregex "PSRLQrr")>;
2316 def: InstRW<[HWWriteResGroup31], (instregex "PSRLWrr")>;
2317 def: InstRW<[HWWriteResGroup31], (instregex "PTESTrr")>;
2318 def: InstRW<[HWWriteResGroup31], (instregex "VCVTPH2PSYrr")>;
2319 def: InstRW<[HWWriteResGroup31], (instregex "VCVTPH2PSrr")>;
2320 def: InstRW<[HWWriteResGroup31], (instregex "VCVTPS2PDrr")>;
2321 def: InstRW<[HWWriteResGroup31], (instregex "VCVTSS2SDrr")>;
2322 def: InstRW<[HWWriteResGroup31], (instregex "VEXTRACTPSrr")>;
2323 def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRBrr")>;
2324 def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRDrr")>;
2325 def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRQrr")>;
2326 def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRWri")>;
2327 def: InstRW<[HWWriteResGroup31], (instregex "VPEXTRWrr_REV")>;
2328 def: InstRW<[HWWriteResGroup31], (instregex "VPSLLDrr")>;
2329 def: InstRW<[HWWriteResGroup31], (instregex "VPSLLQrr")>;
2330 def: InstRW<[HWWriteResGroup31], (instregex "VPSLLWrr")>;
2331 def: InstRW<[HWWriteResGroup31], (instregex "VPSRADrr")>;
2332 def: InstRW<[HWWriteResGroup31], (instregex "VPSRAWrr")>;
2333 def: InstRW<[HWWriteResGroup31], (instregex "VPSRLDrr")>;
2334 def: InstRW<[HWWriteResGroup31], (instregex "VPSRLQrr")>;
2335 def: InstRW<[HWWriteResGroup31], (instregex "VPSRLWrr")>;
2336 def: InstRW<[HWWriteResGroup31], (instregex "VPTESTrr")>;
2337
2338 def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> {
2339 let Latency = 2;
2340 let NumMicroOps = 2;
2341 let ResourceCycles = [1,1];
2342 }
2343 def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>;
2344
2345 def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> {
2346 let Latency = 2;
2347 let NumMicroOps = 2;
2348 let ResourceCycles = [1,1];
2349 }
2350 def: InstRW<[HWWriteResGroup33], (instregex "MMX_MOVDQ2Qrr")>;
2351
2352 def HWWriteResGroup34 : SchedWriteRes<[HWPort06,HWPort15]> {
2353 let Latency = 2;
2354 let NumMicroOps = 2;
2355 let ResourceCycles = [1,1];
2356 }
2357 def: InstRW<[HWWriteResGroup34], (instregex "BEXTR32rr")>;
2358 def: InstRW<[HWWriteResGroup34], (instregex "BEXTR64rr")>;
2359 def: InstRW<[HWWriteResGroup34], (instregex "BSWAP(16|32|64)r")>;
2360
2361 def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> {
2362 let Latency = 2;
2363 let NumMicroOps = 2;
2364 let ResourceCycles = [1,1];
2365 }
2366 def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)ri8")>;
2367 def: InstRW<[HWWriteResGroup35], (instregex "ADC(16|32|64)rr(_REV?)")>;
2368 def: InstRW<[HWWriteResGroup35], (instregex "ADC8i8")>;
2369 def: InstRW<[HWWriteResGroup35], (instregex "ADC8ri")>;
2370 def: InstRW<[HWWriteResGroup35], (instregex "ADC8rr(_REV?)")>;
2371 def: InstRW<[HWWriteResGroup35], (instregex "CMOVAE(16|32|64)rr")>;
2372 def: InstRW<[HWWriteResGroup35], (instregex "CMOVB(16|32|64)rr")>;
2373 def: InstRW<[HWWriteResGroup35], (instregex "CMOVE(16|32|64)rr")>;
2374 def: InstRW<[HWWriteResGroup35], (instregex "CMOVG(16|32|64)rr")>;
2375 def: InstRW<[HWWriteResGroup35], (instregex "CMOVGE(16|32|64)rr")>;
2376 def: InstRW<[HWWriteResGroup35], (instregex "CMOVL(16|32|64)rr")>;
2377 def: InstRW<[HWWriteResGroup35], (instregex "CMOVLE(16|32|64)rr")>;
2378 def: InstRW<[HWWriteResGroup35], (instregex "CMOVNE(16|32|64)rr")>;
2379 def: InstRW<[HWWriteResGroup35], (instregex "CMOVNO(16|32|64)rr")>;
2380 def: InstRW<[HWWriteResGroup35], (instregex "CMOVNP(16|32|64)rr")>;
2381 def: InstRW<[HWWriteResGroup35], (instregex "CMOVNS(16|32|64)rr")>;
2382 def: InstRW<[HWWriteResGroup35], (instregex "CMOVO(16|32|64)rr")>;
2383 def: InstRW<[HWWriteResGroup35], (instregex "CMOVP(16|32|64)rr")>;
2384 def: InstRW<[HWWriteResGroup35], (instregex "CMOVS(16|32|64)rr")>;
2385 def: InstRW<[HWWriteResGroup35], (instregex "CWD")>;
2386 def: InstRW<[HWWriteResGroup35], (instregex "JRCXZ")>;
2387 def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)ri8")>;
2388 def: InstRW<[HWWriteResGroup35], (instregex "SBB(16|32|64)rr(_REV?)")>;
2389 def: InstRW<[HWWriteResGroup35], (instregex "SBB8i8")>;
2390 def: InstRW<[HWWriteResGroup35], (instregex "SBB8ri")>;
2391 def: InstRW<[HWWriteResGroup35], (instregex "SBB8rr(_REV?)")>;
2392 def: InstRW<[HWWriteResGroup35], (instregex "SETAr")>;
2393 def: InstRW<[HWWriteResGroup35], (instregex "SETBEr")>;
2394
2395 def HWWriteResGroup36 : SchedWriteRes<[HWPort5,HWPort23]> {
2396 let Latency = 2;
2397 let NumMicroOps = 3;
2398 let ResourceCycles = [2,1];
2399 }
2400 def: InstRW<[HWWriteResGroup36], (instregex "BLENDVPDrm0")>;
2401 def: InstRW<[HWWriteResGroup36], (instregex "BLENDVPSrm0")>;
2402 def: InstRW<[HWWriteResGroup36], (instregex "MMX_PACKSSDWirm")>;
2403 def: InstRW<[HWWriteResGroup36], (instregex "MMX_PACKSSWBirm")>;
2404 def: InstRW<[HWWriteResGroup36], (instregex "MMX_PACKUSWBirm")>;
2405 def: InstRW<[HWWriteResGroup36], (instregex "PBLENDVBrm0")>;
2406 def: InstRW<[HWWriteResGroup36], (instregex "VBLENDVPDYrm")>;
2407 def: InstRW<[HWWriteResGroup36], (instregex "VBLENDVPDrm")>;
2408 def: InstRW<[HWWriteResGroup36], (instregex "VBLENDVPSYrm")>;
2409 def: InstRW<[HWWriteResGroup36], (instregex "VBLENDVPSrm")>;
2410 def: InstRW<[HWWriteResGroup36], (instregex "VMASKMOVPDYrm")>;
2411 def: InstRW<[HWWriteResGroup36], (instregex "VMASKMOVPDrm")>;
2412 def: InstRW<[HWWriteResGroup36], (instregex "VMASKMOVPSYrm")>;
2413 def: InstRW<[HWWriteResGroup36], (instregex "VMASKMOVPSrm")>;
2414 def: InstRW<[HWWriteResGroup36], (instregex "VPBLENDVBYrm")>;
2415 def: InstRW<[HWWriteResGroup36], (instregex "VPBLENDVBrm")>;
2416 def: InstRW<[HWWriteResGroup36], (instregex "VPMASKMOVDYrm")>;
2417 def: InstRW<[HWWriteResGroup36], (instregex "VPMASKMOVDrm")>;
2418 def: InstRW<[HWWriteResGroup36], (instregex "VPMASKMOVQYrm")>;
2419 def: InstRW<[HWWriteResGroup36], (instregex "VPMASKMOVQrm")>;
2420
2421 def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> {
2422 let Latency = 2;
2423 let NumMicroOps = 3;
2424 let ResourceCycles = [1,2];
2425 }
2426 def: InstRW<[HWWriteResGroup37], (instregex "LEAVE64")>;
2427 def: InstRW<[HWWriteResGroup37], (instregex "SCASB")>;
2428 def: InstRW<[HWWriteResGroup37], (instregex "SCASL")>;
2429 def: InstRW<[HWWriteResGroup37], (instregex "SCASQ")>;
2430 def: InstRW<[HWWriteResGroup37], (instregex "SCASW")>;
2431
2432 def HWWriteResGroup38 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
2433 let Latency = 2;
2434 let NumMicroOps = 3;
2435 let ResourceCycles = [1,1,1];
2436 }
2437 def: InstRW<[HWWriteResGroup38], (instregex "PSLLDrm")>;
2438 def: InstRW<[HWWriteResGroup38], (instregex "PSLLQrm")>;
2439 def: InstRW<[HWWriteResGroup38], (instregex "PSLLWrm")>;
2440 def: InstRW<[HWWriteResGroup38], (instregex "PSRADrm")>;
2441 def: InstRW<[HWWriteResGroup38], (instregex "PSRAWrm")>;
2442 def: InstRW<[HWWriteResGroup38], (instregex "PSRLDrm")>;
2443 def: InstRW<[HWWriteResGroup38], (instregex "PSRLQrm")>;
2444 def: InstRW<[HWWriteResGroup38], (instregex "PSRLWrm")>;
2445 def: InstRW<[HWWriteResGroup38], (instregex "PTESTrm")>;
2446 def: InstRW<[HWWriteResGroup38], (instregex "VPSLLDrm")>;
2447 def: InstRW<[HWWriteResGroup38], (instregex "VPSLLQrm")>;
2448 def: InstRW<[HWWriteResGroup38], (instregex "VPSLLWrm")>;
2449 def: InstRW<[HWWriteResGroup38], (instregex "VPSRADrm")>;
2450 def: InstRW<[HWWriteResGroup38], (instregex "VPSRAWrm")>;
2451 def: InstRW<[HWWriteResGroup38], (instregex "VPSRLDrm")>;
2452 def: InstRW<[HWWriteResGroup38], (instregex "VPSRLQrm")>;
2453 def: InstRW<[HWWriteResGroup38], (instregex "VPSRLWrm")>;
2454 def: InstRW<[HWWriteResGroup38], (instregex "VPTESTrm")>;
2455
2456 def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> {
2457 let Latency = 2;
2458 let NumMicroOps = 3;
2459 let ResourceCycles = [1,1,1];
2460 }
2461 def: InstRW<[HWWriteResGroup39], (instregex "FLDCW16m")>;
2462
2463 def HWWriteResGroup40 : SchedWriteRes<[HWPort0,HWPort23,HWPort0156]> {
2464 let Latency = 2;
2465 let NumMicroOps = 3;
2466 let ResourceCycles = [1,1,1];
2467 }
2468 def: InstRW<[HWWriteResGroup40], (instregex "LDMXCSR")>;
2469 def: InstRW<[HWWriteResGroup40], (instregex "VLDMXCSR")>;
2470
2471 def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> {
2472 let Latency = 2;
2473 let NumMicroOps = 3;
2474 let ResourceCycles = [1,1,1];
2475 }
2476 def: InstRW<[HWWriteResGroup41], (instregex "LRETQ")>;
2477 def: InstRW<[HWWriteResGroup41], (instregex "RETQ")>;
2478
2479 def HWWriteResGroup42 : SchedWriteRes<[HWPort23,HWPort06,HWPort15]> {
2480 let Latency = 2;
2481 let NumMicroOps = 3;
2482 let ResourceCycles = [1,1,1];
2483 }
2484 def: InstRW<[HWWriteResGroup42], (instregex "BEXTR32rm")>;
2485 def: InstRW<[HWWriteResGroup42], (instregex "BEXTR64rm")>;
2486
2487 def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
2488 let Latency = 2;
2489 let NumMicroOps = 3;
2490 let ResourceCycles = [1,1,1];
2491 }
2492 def: InstRW<[HWWriteResGroup43], (instregex "ADC(16|32|64)rm")>;
2493 def: InstRW<[HWWriteResGroup43], (instregex "ADC8rm")>;
2494 def: InstRW<[HWWriteResGroup43], (instregex "CMOVAE(16|32|64)rm")>;
2495 def: InstRW<[HWWriteResGroup43], (instregex "CMOVB(16|32|64)rm")>;
2496 def: InstRW<[HWWriteResGroup43], (instregex "CMOVE(16|32|64)rm")>;
2497 def: InstRW<[HWWriteResGroup43], (instregex "CMOVG(16|32|64)rm")>;
2498 def: InstRW<[HWWriteResGroup43], (instregex "CMOVGE(16|32|64)rm")>;
2499 def: InstRW<[HWWriteResGroup43], (instregex "CMOVL(16|32|64)rm")>;
2500 def: InstRW<[HWWriteResGroup43], (instregex "CMOVLE(16|32|64)rm")>;
2501 def: InstRW<[HWWriteResGroup43], (instregex "CMOVNE(16|32|64)rm")>;
2502 def: InstRW<[HWWriteResGroup43], (instregex "CMOVNO(16|32|64)rm")>;
2503 def: InstRW<[HWWriteResGroup43], (instregex "CMOVNP(16|32|64)rm")>;
2504 def: InstRW<[HWWriteResGroup43], (instregex "CMOVNS(16|32|64)rm")>;
2505 def: InstRW<[HWWriteResGroup43], (instregex "CMOVO(16|32|64)rm")>;
2506 def: InstRW<[HWWriteResGroup43], (instregex "CMOVP(16|32|64)rm")>;
2507 def: InstRW<[HWWriteResGroup43], (instregex "CMOVS(16|32|64)rm")>;
2508 def: InstRW<[HWWriteResGroup43], (instregex "SBB(16|32|64)rm")>;
2509 def: InstRW<[HWWriteResGroup43], (instregex "SBB8rm")>;
2510
2511 def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
2512 let Latency = 2;
2513 let NumMicroOps = 4;
2514 let ResourceCycles = [1,1,1,1];
2515 }
2516 def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>;
2517
2518 def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> {
2519 let Latency = 2;
2520 let NumMicroOps = 4;
2521 let ResourceCycles = [1,1,1,1];
2522 }
2523 def: InstRW<[HWWriteResGroup45], (instregex "CALL64pcrel32")>;
2524 def: InstRW<[HWWriteResGroup45], (instregex "SETAm")>;
2525 def: InstRW<[HWWriteResGroup45], (instregex "SETBEm")>;
2526
2527 def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> {
2528 let Latency = 2;
2529 let NumMicroOps = 5;
2530 let ResourceCycles = [1,1,1,2];
2531 }
2532 def: InstRW<[HWWriteResGroup46], (instregex "ROL(16|32|64)m1")>;
2533 def: InstRW<[HWWriteResGroup46], (instregex "ROL(16|32|64)mi")>;
2534 def: InstRW<[HWWriteResGroup46], (instregex "ROL8m1")>;
2535 def: InstRW<[HWWriteResGroup46], (instregex "ROL8mi")>;
2536 def: InstRW<[HWWriteResGroup46], (instregex "ROR(16|32|64)m1")>;
2537 def: InstRW<[HWWriteResGroup46], (instregex "ROR(16|32|64)mi")>;
2538 def: InstRW<[HWWriteResGroup46], (instregex "ROR8m1")>;
2539 def: InstRW<[HWWriteResGroup46], (instregex "ROR8mi")>;
2540
2541 def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
2542 let Latency = 2;
2543 let NumMicroOps = 5;
2544 let ResourceCycles = [1,1,1,2];
2545 }
2546 def: InstRW<[HWWriteResGroup47], (instregex "XADD(16|32|64)rm")>;
2547 def: InstRW<[HWWriteResGroup47], (instregex "XADD8rm")>;
2548
2549 def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
2550 let Latency = 2;
2551 let NumMicroOps = 5;
2552 let ResourceCycles = [1,1,1,1,1];
2553 }
2554 def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>;
2555 def: InstRW<[HWWriteResGroup48], (instregex "FARCALL64")>;
2556
2557 def HWWriteResGroup49 : SchedWriteRes<[HWPort0]> {
2558 let Latency = 3;
2559 let NumMicroOps = 1;
2560 let ResourceCycles = [1];
2561 }
2562 def: InstRW<[HWWriteResGroup49], (instregex "MOVMSKPDrr")>;
2563 def: InstRW<[HWWriteResGroup49], (instregex "MOVMSKPSrr")>;
2564 def: InstRW<[HWWriteResGroup49], (instregex "PMOVMSKBrr")>;
2565 def: InstRW<[HWWriteResGroup49], (instregex "VMOVMSKPDYrr")>;
2566 def: InstRW<[HWWriteResGroup49], (instregex "VMOVMSKPDrr")>;
2567 def: InstRW<[HWWriteResGroup49], (instregex "VMOVMSKPSYrr")>;
2568 def: InstRW<[HWWriteResGroup49], (instregex "VMOVMSKPSrr")>;
2569 def: InstRW<[HWWriteResGroup49], (instregex "VPMOVMSKBYrr")>;
2570 def: InstRW<[HWWriteResGroup49], (instregex "VPMOVMSKBrr")>;
2571
2572 def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
2573 let Latency = 3;
2574 let NumMicroOps = 1;
2575 let ResourceCycles = [1];
2576 }
2577 def: InstRW<[HWWriteResGroup50], (instregex "ADDPDrr")>;
2578 def: InstRW<[HWWriteResGroup50], (instregex "ADDPSrr")>;
2579 def: InstRW<[HWWriteResGroup50], (instregex "ADDSDrr")>;
2580 def: InstRW<[HWWriteResGroup50], (instregex "ADDSSrr")>;
2581 def: InstRW<[HWWriteResGroup50], (instregex "ADDSUBPDrr")>;
2582 def: InstRW<[HWWriteResGroup50], (instregex "ADDSUBPSrr")>;
2583 def: InstRW<[HWWriteResGroup50], (instregex "ADD_FPrST0")>;
2584 def: InstRW<[HWWriteResGroup50], (instregex "ADD_FST0r")>;
2585 def: InstRW<[HWWriteResGroup50], (instregex "ADD_FrST0")>;
2586 def: InstRW<[HWWriteResGroup50], (instregex "BSF(16|32|64)rr")>;
2587 def: InstRW<[HWWriteResGroup50], (instregex "BSR(16|32|64)rr")>;
2588 def: InstRW<[HWWriteResGroup50], (instregex "CMPPDrri")>;
2589 def: InstRW<[HWWriteResGroup50], (instregex "CMPPSrri")>;
2590 def: InstRW<[HWWriteResGroup50], (instregex "CMPSSrr")>;
2591 def: InstRW<[HWWriteResGroup50], (instregex "COMISDrr")>;
2592 def: InstRW<[HWWriteResGroup50], (instregex "COMISSrr")>;
2593 def: InstRW<[HWWriteResGroup50], (instregex "CVTDQ2PSrr")>;
2594 def: InstRW<[HWWriteResGroup50], (instregex "CVTPS2DQrr")>;
2595 def: InstRW<[HWWriteResGroup50], (instregex "CVTTPS2DQrr")>;
2596 def: InstRW<[HWWriteResGroup50], (instregex "IMUL64rr(i8?)")>;
2597 def: InstRW<[HWWriteResGroup50], (instregex "IMUL8r")>;
2598 def: InstRW<[HWWriteResGroup50], (instregex "LZCNT(16|32|64)rr")>;
2599 def: InstRW<[HWWriteResGroup50], (instregex "MAXPDrr")>;
2600 def: InstRW<[HWWriteResGroup50], (instregex "MAXPSrr")>;
2601 def: InstRW<[HWWriteResGroup50], (instregex "MAXSDrr")>;
2602 def: InstRW<[HWWriteResGroup50], (instregex "MAXSSrr")>;
2603 def: InstRW<[HWWriteResGroup50], (instregex "MINPDrr")>;
2604 def: InstRW<[HWWriteResGroup50], (instregex "MINPSrr")>;
2605 def: InstRW<[HWWriteResGroup50], (instregex "MINSDrr")>;
2606 def: InstRW<[HWWriteResGroup50], (instregex "MINSSrr")>;
2607 def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr")>;
2608 def: InstRW<[HWWriteResGroup50], (instregex "MUL8r")>;
2609 def: InstRW<[HWWriteResGroup50], (instregex "PDEP32rr")>;
2610 def: InstRW<[HWWriteResGroup50], (instregex "PDEP64rr")>;
2611 def: InstRW<[HWWriteResGroup50], (instregex "PEXT32rr")>;
2612 def: InstRW<[HWWriteResGroup50], (instregex "PEXT64rr")>;
2613 def: InstRW<[HWWriteResGroup50], (instregex "POPCNT(16|32|64)rr")>;
2614 def: InstRW<[HWWriteResGroup50], (instregex "SHLD(16|32|64)rri8")>;
2615 def: InstRW<[HWWriteResGroup50], (instregex "SHRD(16|32|64)rri8")>;
2616 def: InstRW<[HWWriteResGroup50], (instregex "SUBPDrr")>;
2617 def: InstRW<[HWWriteResGroup50], (instregex "SUBPSrr")>;
2618 def: InstRW<[HWWriteResGroup50], (instregex "SUBR_FPrST0")>;
2619 def: InstRW<[HWWriteResGroup50], (instregex "SUBR_FST0r")>;
2620 def: InstRW<[HWWriteResGroup50], (instregex "SUBR_FrST0")>;
2621 def: InstRW<[HWWriteResGroup50], (instregex "SUBSDrr")>;
2622 def: InstRW<[HWWriteResGroup50], (instregex "SUBSSrr")>;
2623 def: InstRW<[HWWriteResGroup50], (instregex "SUB_FPrST0")>;
2624 def: InstRW<[HWWriteResGroup50], (instregex "SUB_FST0r")>;
2625 def: InstRW<[HWWriteResGroup50], (instregex "SUB_FrST0")>;
2626 def: InstRW<[HWWriteResGroup50], (instregex "TZCNT(16|32|64)rr")>;
2627 def: InstRW<[HWWriteResGroup50], (instregex "UCOMISDrr")>;
2628 def: InstRW<[HWWriteResGroup50], (instregex "UCOMISSrr")>;
2629 def: InstRW<[HWWriteResGroup50], (instregex "VADDPDYrr")>;
2630 def: InstRW<[HWWriteResGroup50], (instregex "VADDPDrr")>;
2631 def: InstRW<[HWWriteResGroup50], (instregex "VADDPSYrr")>;
2632 def: InstRW<[HWWriteResGroup50], (instregex "VADDPSrr")>;
2633 def: InstRW<[HWWriteResGroup50], (instregex "VADDSDrr")>;
2634 def: InstRW<[HWWriteResGroup50], (instregex "VADDSSrr")>;
2635 def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPDYrr")>;
2636 def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPDrr")>;
2637 def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPSYrr")>;
2638 def: InstRW<[HWWriteResGroup50], (instregex "VADDSUBPSrr")>;
2639 def: InstRW<[HWWriteResGroup50], (instregex "VCMPPDYrri")>;
2640 def: InstRW<[HWWriteResGroup50], (instregex "VCMPPDrri")>;
2641 def: InstRW<[HWWriteResGroup50], (instregex "VCMPPSYrri")>;
2642 def: InstRW<[HWWriteResGroup50], (instregex "VCMPPSrri")>;
2643 def: InstRW<[HWWriteResGroup50], (instregex "VCMPSDrr")>;
2644 def: InstRW<[HWWriteResGroup50], (instregex "VCMPSSrr")>;
2645 def: InstRW<[HWWriteResGroup50], (instregex "VCOMISDrr")>;
2646 def: InstRW<[HWWriteResGroup50], (instregex "VCOMISSrr")>;
2647 def: InstRW<[HWWriteResGroup50], (instregex "VCVTDQ2PSYrr")>;
2648 def: InstRW<[HWWriteResGroup50], (instregex "VCVTDQ2PSrr")>;
2649 def: InstRW<[HWWriteResGroup50], (instregex "VCVTPS2DQYrr")>;
2650 def: InstRW<[HWWriteResGroup50], (instregex "VCVTPS2DQrr")>;
2651 def: InstRW<[HWWriteResGroup50], (instregex "VCVTTPS2DQYrr")>;
2652 def: InstRW<[HWWriteResGroup50], (instregex "VCVTTPS2DQrr")>;
2653 def: InstRW<[HWWriteResGroup50], (instregex "VMAXPDYrr")>;
2654 def: InstRW<[HWWriteResGroup50], (instregex "VMAXPDrr")>;
2655 def: InstRW<[HWWriteResGroup50], (instregex "VMAXPSYrr")>;
2656 def: InstRW<[HWWriteResGroup50], (instregex "VMAXPSrr")>;
2657 def: InstRW<[HWWriteResGroup50], (instregex "VMAXSDrr")>;
2658 def: InstRW<[HWWriteResGroup50], (instregex "VMAXSSrr")>;
2659 def: InstRW<[HWWriteResGroup50], (instregex "VMINPDYrr")>;
2660 def: InstRW<[HWWriteResGroup50], (instregex "VMINPDrr")>;
2661 def: InstRW<[HWWriteResGroup50], (instregex "VMINPSYrr")>;
2662 def: InstRW<[HWWriteResGroup50], (instregex "VMINPSrr")>;
2663 def: InstRW<[HWWriteResGroup50], (instregex "VMINSDrr")>;
2664 def: InstRW<[HWWriteResGroup50], (instregex "VMINSSrr")>;
2665 def: InstRW<[HWWriteResGroup50], (instregex "VSUBPDYrr")>;
2666 def: InstRW<[HWWriteResGroup50], (instregex "VSUBPDrr")>;
2667 def: InstRW<[HWWriteResGroup50], (instregex "VSUBPSYrr")>;
2668 def: InstRW<[HWWriteResGroup50], (instregex "VSUBPSrr")>;
2669 def: InstRW<[HWWriteResGroup50], (instregex "VSUBSDrr")>;
2670 def: InstRW<[HWWriteResGroup50], (instregex "VSUBSSrr")>;
2671 def: InstRW<[HWWriteResGroup50], (instregex "VUCOMISDrr")>;
2672 def: InstRW<[HWWriteResGroup50], (instregex "VUCOMISSrr")>;
2673
2674 def HWWriteResGroup50_16 : SchedWriteRes<[HWPort1, HWPort0156]> {
2675 let Latency = 3;
2676 let NumMicroOps = 4;
2677 }
2678 def: InstRW<[HWWriteResGroup50_16], (instregex "IMUL16rr(i8?)")>;
2679
2680 def HWWriteResGroup50_32 : SchedWriteRes<[HWPort1, HWPort0156]> {
2681 let Latency = 3;
2682 let NumMicroOps = 3;
2683 }
2684 def: InstRW<[HWWriteResGroup50_32], (instregex "IMUL32rr(i8?)")>;
2685
2686 def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> {
2687 let Latency = 3;
2688 let NumMicroOps = 1;
2689 let ResourceCycles = [1];
2690 }
2691 def: InstRW<[HWWriteResGroup51], (instregex "VBROADCASTSDYrr")>;
2692 def: InstRW<[HWWriteResGroup51], (instregex "VBROADCASTSSYrr")>;
2693 def: InstRW<[HWWriteResGroup51], (instregex "VEXTRACTF128rr")>;
2694 def: InstRW<[HWWriteResGroup51], (instregex "VEXTRACTI128rr")>;
2695 def: InstRW<[HWWriteResGroup51], (instregex "VINSERTF128rr")>;
2696 def: InstRW<[HWWriteResGroup51], (instregex "VINSERTI128rr")>;
2697 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTBYrr")>;
2698 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTBrr")>;
2699 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTDYrr")>;
2700 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTQYrr")>;
2701 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTWYrr")>;
2702 def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCASTWrr")>;
2703 def: InstRW<[HWWriteResGroup51], (instregex "VPERM2F128rr")>;
2704 def: InstRW<[HWWriteResGroup51], (instregex "VPERM2I128rr")>;
2705 def: InstRW<[HWWriteResGroup51], (instregex "VPERMDYrr")>;
2706 def: InstRW<[HWWriteResGroup51], (instregex "VPERMPDYri")>;
2707 def: InstRW<[HWWriteResGroup51], (instregex "VPERMPSYrr")>;
2708 def: InstRW<[HWWriteResGroup51], (instregex "VPERMQYri")>;
2709 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBDYrr")>;
2710 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBQYrr")>;
2711 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXBWYrr")>;
2712 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXDQYrr")>;
2713 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXWDYrr")>;
2714 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVSXWQYrr")>;
2715 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBDYrr")>;
2716 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBQYrr")>;
2717 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXBWYrr")>;
2718 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXDQYrr")>;
2719 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXWDYrr")>;
2720 def: InstRW<[HWWriteResGroup51], (instregex "VPMOVZXWQYrr")>;
2721
2722 def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> {
2723 let Latency = 3;
2724 let NumMicroOps = 2;
2725 let ResourceCycles = [1,1];
2726 }
2727 def: InstRW<[HWWriteResGroup52], (instregex "ADDPDrm")>;
2728 def: InstRW<[HWWriteResGroup52], (instregex "ADDPSrm")>;
2729 def: InstRW<[HWWriteResGroup52], (instregex "ADDSDrm")>;
2730 def: InstRW<[HWWriteResGroup52], (instregex "ADDSSrm")>;
2731 def: InstRW<[HWWriteResGroup52], (instregex "ADDSUBPDrm")>;
2732 def: InstRW<[HWWriteResGroup52], (instregex "ADDSUBPSrm")>;
2733 def: InstRW<[HWWriteResGroup52], (instregex "ADD_F32m")>;
2734 def: InstRW<[HWWriteResGroup52], (instregex "ADD_F64m")>;
2735 def: InstRW<[HWWriteResGroup52], (instregex "BSF(16|32|64)rm")>;
2736 def: InstRW<[HWWriteResGroup52], (instregex "BSR(16|32|64)rm")>;
2737 def: InstRW<[HWWriteResGroup52], (instregex "CMPPDrmi")>;
2738 def: InstRW<[HWWriteResGroup52], (instregex "CMPPSrmi")>;
2739 def: InstRW<[HWWriteResGroup52], (instregex "CMPSSrm")>;
2740 def: InstRW<[HWWriteResGroup52], (instregex "COMISDrm")>;
2741 def: InstRW<[HWWriteResGroup52], (instregex "COMISSrm")>;
2742 def: InstRW<[HWWriteResGroup52], (instregex "CVTDQ2PSrm")>;
2743 def: InstRW<[HWWriteResGroup52], (instregex "CVTPS2DQrm")>;
2744 def: InstRW<[HWWriteResGroup52], (instregex "CVTTPS2DQrm")>;
2745 def: InstRW<[HWWriteResGroup52], (instregex "ILD_F16m")>;
2746 def: InstRW<[HWWriteResGroup52], (instregex "ILD_F32m")>;
2747 def: InstRW<[HWWriteResGroup52], (instregex "ILD_F64m")>;
2748 def: InstRW<[HWWriteResGroup52], (instregex "IMUL64m")>;
2749 def: InstRW<[HWWriteResGroup52], (instregex "IMUL64rm(i8?)")>;
2750 def: InstRW<[HWWriteResGroup52], (instregex "IMUL8m")>;
2751 def: InstRW<[HWWriteResGroup52], (instregex "LZCNT(16|32|64)rm")>;
2752 def: InstRW<[HWWriteResGroup52], (instregex "MAXPDrm")>;
2753 def: InstRW<[HWWriteResGroup52], (instregex "MAXPSrm")>;
2754 def: InstRW<[HWWriteResGroup52], (instregex "MAXSDrm")>;
2755 def: InstRW<[HWWriteResGroup52], (instregex "MAXSSrm")>;
2756 def: InstRW<[HWWriteResGroup52], (instregex "MINPDrm")>;
2757 def: InstRW<[HWWriteResGroup52], (instregex "MINPSrm")>;
2758 def: InstRW<[HWWriteResGroup52], (instregex "MINSDrm")>;
2759 def: InstRW<[HWWriteResGroup52], (instregex "MINSSrm")>;
2760 def: InstRW<[HWWriteResGroup52], (instregex "MMX_CVTPI2PSirm")>;
2761 def: InstRW<[HWWriteResGroup52], (instregex "MMX_CVTPS2PIirm")>;
2762 def: InstRW<[HWWriteResGroup52], (instregex "MMX_CVTTPS2PIirm")>;
2763 def: InstRW<[HWWriteResGroup52], (instregex "MUL64m")>;
2764 def: InstRW<[HWWriteResGroup52], (instregex "MUL8m")>;
2765 def: InstRW<[HWWriteResGroup52], (instregex "PDEP32rm")>;
2766 def: InstRW<[HWWriteResGroup52], (instregex "PDEP64rm")>;
2767 def: InstRW<[HWWriteResGroup52], (instregex "PEXT32rm")>;
2768 def: InstRW<[HWWriteResGroup52], (instregex "PEXT64rm")>;
2769 def: InstRW<[HWWriteResGroup52], (instregex "POPCNT(16|32|64)rm")>;
2770 def: InstRW<[HWWriteResGroup52], (instregex "SUBPDrm")>;
2771 def: InstRW<[HWWriteResGroup52], (instregex "SUBPSrm")>;
2772 def: InstRW<[HWWriteResGroup52], (instregex "SUBR_F32m")>;
2773 def: InstRW<[HWWriteResGroup52], (instregex "SUBR_F64m")>;
2774 def: InstRW<[HWWriteResGroup52], (instregex "SUBSDrm")>;
2775 def: InstRW<[HWWriteResGroup52], (instregex "SUBSSrm")>;
2776 def: InstRW<[HWWriteResGroup52], (instregex "SUB_F32m")>;
2777 def: InstRW<[HWWriteResGroup52], (instregex "SUB_F64m")>;
2778 def: InstRW<[HWWriteResGroup52], (instregex "TZCNT(16|32|64)rm")>;
2779 def: InstRW<[HWWriteResGroup52], (instregex "UCOMISDrm")>;
2780 def: InstRW<[HWWriteResGroup52], (instregex "UCOMISSrm")>;
2781 def: InstRW<[HWWriteResGroup52], (instregex "VADDPDYrm")>;
2782 def: InstRW<[HWWriteResGroup52], (instregex "VADDPDrm")>;
2783 def: InstRW<[HWWriteResGroup52], (instregex "VADDPSYrm")>;
2784 def: InstRW<[HWWriteResGroup52], (instregex "VADDPSrm")>;
2785 def: InstRW<[HWWriteResGroup52], (instregex "VADDSDrm")>;
2786 def: InstRW<[HWWriteResGroup52], (instregex "VADDSSrm")>;
2787 def: InstRW<[HWWriteResGroup52], (instregex "VADDSUBPDYrm")>;
2788 def: InstRW<[HWWriteResGroup52], (instregex "VADDSUBPDrm")>;
2789 def: InstRW<[HWWriteResGroup52], (instregex "VADDSUBPSYrm")>;
2790 def: InstRW<[HWWriteResGroup52], (instregex "VADDSUBPSrm")>;
2791 def: InstRW<[HWWriteResGroup52], (instregex "VCMPPDYrmi")>;
2792 def: InstRW<[HWWriteResGroup52], (instregex "VCMPPDrmi")>;
2793 def: InstRW<[HWWriteResGroup52], (instregex "VCMPPSYrmi")>;
2794 def: InstRW<[HWWriteResGroup52], (instregex "VCMPPSrmi")>;
2795 def: InstRW<[HWWriteResGroup52], (instregex "VCMPSDrm")>;
2796 def: InstRW<[HWWriteResGroup52], (instregex "VCMPSSrm")>;
2797 def: InstRW<[HWWriteResGroup52], (instregex "VCOMISDrm")>;
2798 def: InstRW<[HWWriteResGroup52], (instregex "VCOMISSrm")>;
2799 def: InstRW<[HWWriteResGroup52], (instregex "VCVTDQ2PSYrm")>;
2800 def: InstRW<[HWWriteResGroup52], (instregex "VCVTDQ2PSrm")>;
2801 def: InstRW<[HWWriteResGroup52], (instregex "VCVTPS2DQYrm")>;
2802 def: InstRW<[HWWriteResGroup52], (instregex "VCVTPS2DQrm")>;
2803 def: InstRW<[HWWriteResGroup52], (instregex "VCVTTPS2DQYrm")>;
2804 def: InstRW<[HWWriteResGroup52], (instregex "VCVTTPS2DQrm")>;
2805 def: InstRW<[HWWriteResGroup52], (instregex "VMAXPDYrm")>;
2806 def: InstRW<[HWWriteResGroup52], (instregex "VMAXPDrm")>;
2807 def: InstRW<[HWWriteResGroup52], (instregex "VMAXPSYrm")>;
2808 def: InstRW<[HWWriteResGroup52], (instregex "VMAXPSrm")>;
2809 def: InstRW<[HWWriteResGroup52], (instregex "VMAXSDrm")>;
2810 def: InstRW<[HWWriteResGroup52], (instregex "VMAXSSrm")>;
2811 def: InstRW<[HWWriteResGroup52], (instregex "VMINPDYrm")>;
2812 def: InstRW<[HWWriteResGroup52], (instregex "VMINPDrm")>;
2813 def: InstRW<[HWWriteResGroup52], (instregex "VMINPSYrm")>;
2814 def: InstRW<[HWWriteResGroup52], (instregex "VMINPSrm")>;
2815 def: InstRW<[HWWriteResGroup52], (instregex "VMINSDrm")>;
2816 def: InstRW<[HWWriteResGroup52], (instregex "VMINSSrm")>;
2817 def: InstRW<[HWWriteResGroup52], (instregex "VSUBPDYrm")>;
2818 def: InstRW<[HWWriteResGroup52], (instregex "VSUBPDrm")>;
2819 def: InstRW<[HWWriteResGroup52], (instregex "VSUBPSYrm")>;
2820 def: InstRW<[HWWriteResGroup52], (instregex "VSUBPSrm")>;
2821 def: InstRW<[HWWriteResGroup52], (instregex "VSUBSDrm")>;
2822 def: InstRW<[HWWriteResGroup52], (instregex "VSUBSSrm")>;
2823 def: InstRW<[HWWriteResGroup52], (instregex "VUCOMISDrm")>;
2824 def: InstRW<[HWWriteResGroup52], (instregex "VUCOMISSrm")>;
2825
2826 def HWWriteResGroup52_16 : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
2827 let Latency = 3;
2828 let NumMicroOps = 4;
2829 }
2830 def: InstRW<[HWWriteResGroup52_16], (instregex "IMUL16m")>;
2831 def: InstRW<[HWWriteResGroup52_16], (instregex "IMUL16rm(i8?)")>;
2832 def: InstRW<[HWWriteResGroup52_16], (instregex "MUL16m")>;
2833
2834 def HWWriteResGroup52_32 : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
2835 let Latency = 3;
2836 let NumMicroOps = 3;
2837 }
2838 def: InstRW<[HWWriteResGroup52_32], (instregex "IMUL32m")>;
2839 def: InstRW<[HWWriteResGroup52_32], (instregex "IMUL32rm(i8?)")>;
2840 def: InstRW<[HWWriteResGroup52_32], (instregex "MUL32m")>;
2841
2842 def HWWriteResGroup53 : SchedWriteRes<[HWPort5,HWPort23]> {
2843 let Latency = 3;
2844 let NumMicroOps = 2;
2845 let ResourceCycles = [1,1];
2846 }
2847 def: InstRW<[HWWriteResGroup53], (instregex "VPERM2F128rm")>;
2848 def: InstRW<[HWWriteResGroup53], (instregex "VPERM2I128rm")>;
2849 def: InstRW<[HWWriteResGroup53], (instregex "VPERMDYrm")>;
2850 def: InstRW<[HWWriteResGroup53], (instregex "VPERMPDYmi")>;
2851 def: InstRW<[HWWriteResGroup53], (instregex "VPERMPSYrm")>;
2852 def: InstRW<[HWWriteResGroup53], (instregex "VPERMQYmi")>;
2853 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVSXBDYrm")>;
2854 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVSXBQYrm")>;
2855 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVSXBWYrm")>;
2856 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVSXDQYrm")>;
2857 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVSXWDYrm")>;
2858 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVSXWQYrm")>;
2859 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXBDYrm")>;
2860 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXBQYrm")>;
2861 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXBWYrm")>;
2862 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXDQYrm")>;
2863 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXWDYrm")>;
2864 def: InstRW<[HWWriteResGroup53], (instregex "VPMOVZXWQYrm")>;
2865
2866 def HWWriteResGroup54 : SchedWriteRes<[HWPort0156]> {
2867 let Latency = 3;
2868 let NumMicroOps = 3;
2869 let ResourceCycles = [3];
2870 }
2871 def: InstRW<[HWWriteResGroup54], (instregex "XADD(16|32|64)rr")>;
2872 def: InstRW<[HWWriteResGroup54], (instregex "XADD8rr")>;
2873 def: InstRW<[HWWriteResGroup54], (instregex "XCHG8rr")>;
2874
2875 def HWWriteResGroup55 : SchedWriteRes<[HWPort0,HWPort5]> {
2876 let Latency = 3;
2877 let NumMicroOps = 3;
2878 let ResourceCycles = [2,1];
2879 }
2880 def: InstRW<[HWWriteResGroup55], (instregex "VPSLLVDYrr")>;
2881 def: InstRW<[HWWriteResGroup55], (instregex "VPSLLVDrr")>;
2882 def: InstRW<[HWWriteResGroup55], (instregex "VPSRAVDYrr")>;
2883 def: InstRW<[HWWriteResGroup55], (instregex "VPSRAVDrr")>;
2884 def: InstRW<[HWWriteResGroup55], (instregex "VPSRLVDYrr")>;
2885 def: InstRW<[HWWriteResGroup55], (instregex "VPSRLVDrr")>;
2886
2887 def HWWriteResGroup56 : SchedWriteRes<[HWPort5,HWPort15]> {
2888 let Latency = 3;
2889 let NumMicroOps = 3;
2890 let ResourceCycles = [2,1];
2891 }
2892 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDSWrr64")>;
2893 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDWrr64")>;
2894 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDrr64")>;
2895 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBDrr64")>;
2896 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBSWrr64")>;
2897 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBWrr64")>;
2898 def: InstRW<[HWWriteResGroup56], (instregex "PHADDDrr")>;
2899 def: InstRW<[HWWriteResGroup56], (instregex "PHADDSWrr128")>;
2900 def: InstRW<[HWWriteResGroup56], (instregex "PHADDWrr")>;
2901 def: InstRW<[HWWriteResGroup56], (instregex "PHSUBDrr")>;
2902 def: InstRW<[HWWriteResGroup56], (instregex "PHSUBSWrr128")>;
2903 def: InstRW<[HWWriteResGroup56], (instregex "PHSUBWrr")>;
2904 def: InstRW<[HWWriteResGroup56], (instregex "VPHADDDYrr")>;
2905 def: InstRW<[HWWriteResGroup56], (instregex "VPHADDDrr")>;
2906 def: InstRW<[HWWriteResGroup56], (instregex "VPHADDSWrr128")>;
2907 def: InstRW<[HWWriteResGroup56], (instregex "VPHADDSWrr256")>;
2908 def: InstRW<[HWWriteResGroup56], (instregex "VPHADDWYrr")>;
2909 def: InstRW<[HWWriteResGroup56], (instregex "VPHADDWrr")>;
2910 def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBDYrr")>;
2911 def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBDrr")>;
2912 def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBSWrr128")>;
2913 def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBSWrr256")>;
2914 def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBWYrr")>;
2915 def: InstRW<[HWWriteResGroup56], (instregex "VPHSUBWrr")>;
2916
2917 def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> {
2918 let Latency = 3;
2919 let NumMicroOps = 3;
2920 let ResourceCycles = [2,1];
2921 }
2922 def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKSSDWirr")>;
2923 def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKSSWBirr")>;
2924 def: InstRW<[HWWriteResGroup57], (instregex "MMX_PACKUSWBirr")>;
2925
2926 def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> {
2927 let Latency = 3;
2928 let NumMicroOps = 3;
2929 let ResourceCycles = [1,2];
2930 }
2931 def: InstRW<[HWWriteResGroup58], (instregex "CLD")>;
2932
2933 def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> {
2934 let Latency = 3;
2935 let NumMicroOps = 3;
2936 let ResourceCycles = [1,2];
2937 }
2938 def: InstRW<[HWWriteResGroup59], (instregex "CMOVA(16|32|64)rr")>;
2939 def: InstRW<[HWWriteResGroup59], (instregex "CMOVBE(16|32|64)rr")>;
2940 def: InstRW<[HWWriteResGroup59], (instregex "RCL(16|32|64)r1")>;
2941 def: InstRW<[HWWriteResGroup59], (instregex "RCL(16|32|64)ri")>;
2942 def: InstRW<[HWWriteResGroup59], (instregex "RCL8r1")>;
2943 def: InstRW<[HWWriteResGroup59], (instregex "RCL8ri")>;
2944 def: InstRW<[HWWriteResGroup59], (instregex "RCR(16|32|64)r1")>;
2945 def: InstRW<[HWWriteResGroup59], (instregex "RCR(16|32|64)ri")>;
2946 def: InstRW<[HWWriteResGroup59], (instregex "RCR8r1")>;
2947 def: InstRW<[HWWriteResGroup59], (instregex "RCR8ri")>;
2948
2949 def HWWriteResGroup60 : SchedWriteRes<[HWPort06,HWPort0156]> {
2950 let Latency = 3;
2951 let NumMicroOps = 3;
2952 let ResourceCycles = [2,1];
2953 }
2954 def: InstRW<[HWWriteResGroup60], (instregex "ROL(16|32|64)rCL")>;
2955 def: InstRW<[HWWriteResGroup60], (instregex "ROL8rCL")>;
2956 def: InstRW<[HWWriteResGroup60], (instregex "ROR(16|32|64)rCL")>;
2957 def: InstRW<[HWWriteResGroup60], (instregex "ROR8rCL")>;
2958 def: InstRW<[HWWriteResGroup60], (instregex "SAR(16|32|64)rCL")>;
2959 def: InstRW<[HWWriteResGroup60], (instregex "SAR8rCL")>;
2960 def: InstRW<[HWWriteResGroup60], (instregex "SHL(16|32|64)rCL")>;
2961 def: InstRW<[HWWriteResGroup60], (instregex "SHL8rCL")>;
2962 def: InstRW<[HWWriteResGroup60], (instregex "SHR(16|32|64)rCL")>;
2963 def: InstRW<[HWWriteResGroup60], (instregex "SHR8rCL")>;
2964
2965 def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> {
2966 let Latency = 3;
2967 let NumMicroOps = 3;
2968 let ResourceCycles = [1,1,1];
2969 }
2970 def: InstRW<[HWWriteResGroup61], (instregex "FNSTSWm")>;
2971
2972 def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> {
2973 let Latency = 3;
2974 let NumMicroOps = 3;
2975 let ResourceCycles = [1,1,1];
2976 }
2977 def: InstRW<[HWWriteResGroup62], (instregex "ISTT_FP16m")>;
2978 def: InstRW<[HWWriteResGroup62], (instregex "ISTT_FP32m")>;
2979 def: InstRW<[HWWriteResGroup62], (instregex "ISTT_FP64m")>;
2980 def: InstRW<[HWWriteResGroup62], (instregex "IST_F16m")>;
2981 def: InstRW<[HWWriteResGroup62], (instregex "IST_F32m")>;
2982 def: InstRW<[HWWriteResGroup62], (instregex "IST_FP16m")>;
2983 def: InstRW<[HWWriteResGroup62], (instregex "IST_FP32m")>;
2984 def: InstRW<[HWWriteResGroup62], (instregex "IST_FP64m")>;
2985
2986 def HWWriteResGroup63 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
2987 let Latency = 3;
2988 let NumMicroOps = 4;
2989 let ResourceCycles = [2,1,1];
2990 }
2991 def: InstRW<[HWWriteResGroup63], (instregex "VPSLLVDYrm")>;
2992 def: InstRW<[HWWriteResGroup63], (instregex "VPSLLVDrm")>;
2993 def: InstRW<[HWWriteResGroup63], (instregex "VPSRAVDYrm")>;
2994 def: InstRW<[HWWriteResGroup63], (instregex "VPSRAVDrm")>;
2995 def: InstRW<[HWWriteResGroup63], (instregex "VPSRLVDYrm")>;
2996 def: InstRW<[HWWriteResGroup63], (instregex "VPSRLVDrm")>;
2997
2998 def HWWriteResGroup64 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
2999 let Latency = 3;
3000 let NumMicroOps = 4;
3001 let ResourceCycles = [2,1,1];
3002 }
3003 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDSWrm64")>;
3004 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDWrm64")>;
3005 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDrm64")>;
3006 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBDrm64")>;
3007 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBSWrm64")>;
3008 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBWrm64")>;
3009 def: InstRW<[HWWriteResGroup64], (instregex "PHADDDrm")>;
3010 def: InstRW<[HWWriteResGroup64], (instregex "PHADDSWrm128")>;
3011 def: InstRW<[HWWriteResGroup64], (instregex "PHADDWrm")>;
3012 def: InstRW<[HWWriteResGroup64], (instregex "PHSUBDrm")>;
3013 def: InstRW<[HWWriteResGroup64], (instregex "PHSUBSWrm128")>;
3014 def: InstRW<[HWWriteResGroup64], (instregex "PHSUBWrm")>;
3015 def: InstRW<[HWWriteResGroup64], (instregex "VPHADDDYrm")>;
3016 def: InstRW<[HWWriteResGroup64], (instregex "VPHADDDrm")>;
3017 def: InstRW<[HWWriteResGroup64], (instregex "VPHADDSWrm128")>;
3018 def: InstRW<[HWWriteResGroup64], (instregex "VPHADDSWrm256")>;
3019 def: InstRW<[HWWriteResGroup64], (instregex "VPHADDWYrm")>;
3020 def: InstRW<[HWWriteResGroup64], (instregex "VPHADDWrm")>;
3021 def: InstRW<[HWWriteResGroup64], (instregex "VPHSUBDYrm")>;
3022 def: InstRW<[HWWriteResGroup64], (instregex "VPHSUBDrm")>;
3023 def: InstRW<[HWWriteResGroup64], (instregex "VPHSUBSWrm128")>;
3024 def: InstRW<[HWWriteResGroup64], (instregex "VPHSUBSWrm256")>;
3025 def: InstRW<[HWWriteResGroup64], (instregex "VPHSUBWYrm")>;
3026 def: InstRW<[HWWriteResGroup64], (instregex "VPHSUBWrm")>;
3027
3028 def HWWriteResGroup65 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
3029 let Latency = 3;
3030 let NumMicroOps = 4;
3031 let ResourceCycles = [1,1,2];
3032 }
3033 def: InstRW<[HWWriteResGroup65], (instregex "CMOVA(16|32|64)rm")>;
3034 def: InstRW<[HWWriteResGroup65], (instregex "CMOVBE(16|32|64)rm")>;
3035
3036 def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
3037 let Latency = 3;
3038 let NumMicroOps = 5;
3039 let ResourceCycles = [1,1,1,2];
3040 }
3041 def: InstRW<[HWWriteResGroup66], (instregex "RCL(16|32|64)m1")>;
3042 def: InstRW<[HWWriteResGroup66], (instregex "RCL(16|32|64)mi")>;
3043 def: InstRW<[HWWriteResGroup66], (instregex "RCL8m1")>;
3044 def: InstRW<[HWWriteResGroup66], (instregex "RCL8mi")>;
3045 def: InstRW<[HWWriteResGroup66], (instregex "RCR(16|32|64)m1")>;
3046 def: InstRW<[HWWriteResGroup66], (instregex "RCR(16|32|64)mi")>;
3047 def: InstRW<[HWWriteResGroup66], (instregex "RCR8m1")>;
3048 def: InstRW<[HWWriteResGroup66], (instregex "RCR8mi")>;
3049
3050 def HWWriteResGroup67 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
3051 let Latency = 3;
3052 let NumMicroOps = 5;
3053 let ResourceCycles = [1,1,2,1];
3054 }
3055 def: InstRW<[HWWriteResGroup67], (instregex "ROR(16|32|64)mCL")>;
3056 def: InstRW<[HWWriteResGroup67], (instregex "ROR8mCL")>;
3057
3058 def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
3059 let Latency = 3;
3060 let NumMicroOps = 6;
3061 let ResourceCycles = [1,1,1,3];
3062 }
3063 def: InstRW<[HWWriteResGroup68], (instregex "ADC(16|32|64)mi8")>;
3064 def: InstRW<[HWWriteResGroup68], (instregex "ADC8mi")>;
3065 def: InstRW<[HWWriteResGroup68], (instregex "ADD8mi")>;
3066 def: InstRW<[HWWriteResGroup68], (instregex "AND8mi")>;
3067 def: InstRW<[HWWriteResGroup68], (instregex "OR8mi")>;
3068 def: InstRW<[HWWriteResGroup68], (instregex "SUB8mi")>;
3069 def: InstRW<[HWWriteResGroup68], (instregex "XCHG(16|32|64)rm")>;
3070 def: InstRW<[HWWriteResGroup68], (instregex "XCHG8rm")>;
3071 def: InstRW<[HWWriteResGroup68], (instregex "XOR8mi")>;
3072
3073 def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> {
3074 let Latency = 3;
3075 let NumMicroOps = 6;
3076 let ResourceCycles = [1,1,1,2,1];
3077 }
3078 def: InstRW<[HWWriteResGroup69], (instregex "ADC(16|32|64)mr")>;
3079 def: InstRW<[HWWriteResGroup69], (instregex "ADC8mr")>;
3080 def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG(16|32|64)rm")>;
3081 def: InstRW<[HWWriteResGroup69], (instregex "CMPXCHG8rm")>;
3082 def: InstRW<[HWWriteResGroup69], (instregex "ROL(16|32|64)mCL")>;
3083 def: InstRW<[HWWriteResGroup69], (instregex "ROL8mCL")>;
3084 def: InstRW<[HWWriteResGroup69], (instregex "SAR(16|32|64)mCL")>;
3085 def: InstRW<[HWWriteResGroup69], (instregex "SAR8mCL")>;
3086 def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mi8")>;
3087 def: InstRW<[HWWriteResGroup69], (instregex "SBB(16|32|64)mr")>;
3088 def: InstRW<[HWWriteResGroup69], (instregex "SBB8mi")>;
3089 def: InstRW<[HWWriteResGroup69], (instregex "SBB8mr")>;
3090 def: InstRW<[HWWriteResGroup69], (instregex "SHL(16|32|64)mCL")>;
3091 def: InstRW<[HWWriteResGroup69], (instregex "SHL8mCL")>;
3092 def: InstRW<[HWWriteResGroup69], (instregex "SHR(16|32|64)mCL")>;
3093 def: InstRW<[HWWriteResGroup69], (instregex "SHR8mCL")>;
3094
3095 def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
3096 let Latency = 4;
3097 let NumMicroOps = 2;
3098 let ResourceCycles = [1,1];
3099 }
3100 def: InstRW<[HWWriteResGroup70], (instregex "CVTSD2SI64rr")>;
3101 def: InstRW<[HWWriteResGroup70], (instregex "CVTSD2SIrr")>;
3102 def: InstRW<[HWWriteResGroup70], (instregex "CVTSS2SI64rr")>;
3103 def: InstRW<[HWWriteResGroup70], (instregex "CVTSS2SIrr")>;
3104 def: InstRW<[HWWriteResGroup70], (instregex "CVTTSD2SI64rr")>;
3105 def: InstRW<[HWWriteResGroup70], (instregex "CVTTSD2SIrr")>;
3106 def: InstRW<[HWWriteResGroup70], (instregex "CVTTSS2SI64rr")>;
3107 def: InstRW<[HWWriteResGroup70], (instregex "CVTTSS2SIrr")>;
3108 def: InstRW<[HWWriteResGroup70], (instregex "VCVTSD2SI64rr")>;
3109 def: InstRW<[HWWriteResGroup70], (instregex "VCVTSD2SIrr")>;
3110 def: InstRW<[HWWriteResGroup70], (instregex "VCVTSS2SI64rr")>;
3111 def: InstRW<[HWWriteResGroup70], (instregex "VCVTSS2SIrr")>;
3112 def: InstRW<[HWWriteResGroup70], (instregex "VCVTTSD2SI64rr")>;
3113 def: InstRW<[HWWriteResGroup70], (instregex "VCVTTSD2SIrr")>;
3114 def: InstRW<[HWWriteResGroup70], (instregex "VCVTTSS2SI64rr")>;
3115 def: InstRW<[HWWriteResGroup70], (instregex "VCVTTSS2SIrr")>;
3116
3117 def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> {
3118 let Latency = 4;
3119 let NumMicroOps = 2;
3120 let ResourceCycles = [1,1];
3121 }
3122 def: InstRW<[HWWriteResGroup71], (instregex "VCVTPS2PDYrr")>;
3123 def: InstRW<[HWWriteResGroup71], (instregex "VPSLLDYrr")>;
3124 def: InstRW<[HWWriteResGroup71], (instregex "VPSLLQYrr")>;
3125 def: InstRW<[HWWriteResGroup71], (instregex "VPSLLWYrr")>;
3126 def: InstRW<[HWWriteResGroup71], (instregex "VPSRADYrr")>;
3127 def: InstRW<[HWWriteResGroup71], (instregex "VPSRAWYrr")>;
3128 def: InstRW<[HWWriteResGroup71], (instregex "VPSRLDYrr")>;
3129 def: InstRW<[HWWriteResGroup71], (instregex "VPSRLQYrr")>;
3130 def: InstRW<[HWWriteResGroup71], (instregex "VPSRLWYrr")>;
3131 def: InstRW<[HWWriteResGroup71], (instregex "VPTESTYrr")>;
3132
3133 def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> {
3134 let Latency = 4;
3135 let NumMicroOps = 2;
3136 let ResourceCycles = [1,1];
3137 }
3138 def: InstRW<[HWWriteResGroup72], (instregex "FNSTSW16r")>;
3139
3140 def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
3141 let Latency = 4;
3142 let NumMicroOps = 2;
3143 let ResourceCycles = [1,1];
3144 }
3145 def: InstRW<[HWWriteResGroup73], (instregex "CVTDQ2PDrr")>;
3146 def: InstRW<[HWWriteResGroup73], (instregex "CVTPD2DQrr")>;
3147 def: InstRW<[HWWriteResGroup73], (instregex "CVTPD2PSrr")>;
3148 def: InstRW<[HWWriteResGroup73], (instregex "CVTSD2SSrr")>;
3149 def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SD64rr")>;
3150 def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SDrr")>;
3151 def: InstRW<[HWWriteResGroup73], (instregex "CVTSI2SSrr")>;
3152 def: InstRW<[HWWriteResGroup73], (instregex "CVTTPD2DQrr")>;
3153 def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPD2PIirr")>;
3154 def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPI2PDirr")>;
3155 def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTPS2PIirr")>;
3156 def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTTPD2PIirr")>;
3157 def: InstRW<[HWWriteResGroup73], (instregex "MMX_CVTTPS2PIirr")>;
3158 def: InstRW<[HWWriteResGroup73], (instregex "VCVTDQ2PDrr")>;
3159 def: InstRW<[HWWriteResGroup73], (instregex "VCVTPD2DQrr")>;
3160 def: InstRW<[HWWriteResGroup73], (instregex "VCVTPD2PSrr")>;
3161 def: InstRW<[HWWriteResGroup73], (instregex "VCVTPS2PHrr")>;
3162 def: InstRW<[HWWriteResGroup73], (instregex "VCVTSD2SSrr")>;
3163 def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SD64rr")>;
3164 def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SDrr")>;
3165 def: InstRW<[HWWriteResGroup73], (instregex "VCVTSI2SSrr")>;
3166 def: InstRW<[HWWriteResGroup73], (instregex "VCVTTPD2DQrr")>;
3167
3168 def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> {
3169 let Latency = 4;
3170 let NumMicroOps = 2;
3171 let ResourceCycles = [1,1];
3172 }
3173 def: InstRW<[HWWriteResGroup74], (instregex "IMUL64r")>;
3174 def: InstRW<[HWWriteResGroup74], (instregex "MUL64r")>;
3175 def: InstRW<[HWWriteResGroup74], (instregex "MULX64rr")>;
3176
3177 def HWWriteResGroup74_16 : SchedWriteRes<[HWPort1, HWPort0156]> {
3178 let Latency = 4;
3179 let NumMicroOps = 4;
3180 }
3181 def: InstRW<[HWWriteResGroup74_16], (instregex "IMUL16r")>;
3182 def: InstRW<[HWWriteResGroup74_16], (instregex "MUL16r")>;
3183
3184 def HWWriteResGroup74_32 : SchedWriteRes<[HWPort1,HWPort0156]> {
3185 let Latency = 4;
3186