llvm.org GIT mirror llvm / b0d5cdd
Fix PR3453 and probably a bunch of other potential crashes or wrong code with codegen of large integers: eliminate the legacy getIntegerVTBitMask and getIntegerVTSignBit methods, which returned their value as a uint64_t, so couldn't handle huge types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63494 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan Sands 10 years ago
7 changed file(s) with 57 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
438438 else {
439439 return *this;
440440 }
441 }
442
443 /// getIntegerVTBitMask - Return an integer with 1's every place there are
444 /// bits in the specified integer value type. FIXME: Should return an apint.
445 uint64_t getIntegerVTBitMask() const {
446 assert(isInteger() && "Only applies to integers!");
447 MVT EltVT = isVector() ? getVectorElementType() : *this;
448 assert(EltVT.getSizeInBits() <= 64 &&
449 "getIntegerVTBitMask doesn't use APInt!");
450 return ~uint64_t(0UL) >> (64-EltVT.getSizeInBits());
451 }
452
453 /// getIntegerVTSignBit - Return an integer with a 1 in the position of the
454 /// sign bit for the specified integer value type. FIXME: Should return an
455 /// apint.
456 uint64_t getIntegerVTSignBit() const {
457 assert(isInteger() && !isVector() && "Only applies to int scalars!");
458 return uint64_t(1UL) << (getSizeInBits()-1);
459441 }
460442
461443 /// getMVTString - This function returns value type as a string,
24972497 if (DAG.MaskedValueIsZero(SDValue(N, 0),
24982498 APInt::getAllOnesValue(VT.getSizeInBits())))
24992499 return DAG.getConstant(0, VT);
2500 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c))
2501 // iff (trunc c) == c
2500 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
25022501 if (N1.getOpcode() == ISD::TRUNCATE &&
25032502 N1.getOperand(0).getOpcode() == ISD::AND &&
25042503 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
25062505 if (ConstantSDNode *N101C = dyn_cast(N101)) {
25072506 MVT TruncVT = N1.getValueType();
25082507 SDValue N100 = N1.getOperand(0).getOperand(0);
2509 uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
2510 N101C->getZExtValue();
2508 APInt TruncC = N101C->getAPIntValue();
2509 TruncC.trunc(TruncVT.getSizeInBits());
25112510 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
25122511 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
25132512 DAG.getNode(ISD::TRUNCATE,
26312630 }
26322631 }
26332632
2634 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c))
2635 // iff (trunc c) == c
2633 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
26362634 if (N1.getOpcode() == ISD::TRUNCATE &&
26372635 N1.getOperand(0).getOpcode() == ISD::AND &&
26382636 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
26402638 if (ConstantSDNode *N101C = dyn_cast(N101)) {
26412639 MVT TruncVT = N1.getValueType();
26422640 SDValue N100 = N1.getOperand(0).getOperand(0);
2643 uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
2644 N101C->getZExtValue();
2641 APInt TruncC = N101C->getAPIntValue();
2642 TruncC.trunc(TruncVT.getSizeInBits());
26452643 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
26462644 DAG.getNode(ISD::AND, N->getDebugLoc(),
26472645 TruncVT,
27562754 }
27572755 }
27582756
2759 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
2760 // iff (trunc c) == c
2757 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
27612758 if (N1.getOpcode() == ISD::TRUNCATE &&
27622759 N1.getOperand(0).getOpcode() == ISD::AND &&
27632760 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
27652762 if (ConstantSDNode *N101C = dyn_cast(N101)) {
27662763 MVT TruncVT = N1.getValueType();
27672764 SDValue N100 = N1.getOperand(0).getOperand(0);
2768 uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
2769 N101C->getZExtValue();
2765 APInt TruncC = N101C->getAPIntValue();
2766 TruncC.trunc(TruncVT.getSizeInBits());
27702767 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
27712768 DAG.getNode(ISD::AND, N->getDebugLoc(),
27722769 TruncVT,
43584355 SDValue Int = N0.getOperand(0);
43594356 MVT IntVT = Int.getValueType();
43604357 if (IntVT.isInteger() && !IntVT.isVector()) {
4361 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4362 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
4358 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4359 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
43634360 AddToWorkList(Int.getNode());
43644361 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
43654362 N->getValueType(0), Int);
43944391 MVT IntVT = Int.getValueType();
43954392 if (IntVT.isInteger() && !IntVT.isVector()) {
43964393 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4397 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
4394 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
43984395 AddToWorkList(Int.getNode());
43994396 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
44004397 N->getValueType(0), Int);
31093109 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
31103110 Tmp2, DAG.getIntPtrConstant(i)),
31113111 CC);
3112 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
3113 DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
3114 DAG.getConstant(0, EltVT));
3112 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i], DAG.getConstant(
3113 APInt::getAllOnesValue(EltVT.getSizeInBits()),
3114 EltVT), DAG.getConstant(0, EltVT));
31153115 }
31163116 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
31173117 break;
62906290 unsigned len = VT.getSizeInBits();
62916291 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
62926292 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6293 SDValue Tmp2 = DAG.getConstant(VT.getIntegerVTBitMask() & mask[i], VT);
6293 unsigned EltSize = VT.isVector() ?
6294 VT.getVectorElementType().getSizeInBits() : len;
6295 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
62946296 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
62956297 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
62966298 DAG.getNode(ISD::AND, VT,
844844 SDValue NegOne;
845845 if (VT.isVector()) {
846846 MVT EltVT = VT.getVectorElementType();
847 SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
847 SDValue NegOneElt =
848 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT);
848849 std::vector NegOnes(VT.getVectorNumElements(), NegOneElt);
849850 NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT,
850851 &NegOnes[0], NegOnes.size());
851852 } else {
852 NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
853 NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
853854 }
854855
855856 return getNode(ISD::XOR, DL, VT, Val, NegOne);
27712772 return N1;
27722773 case ISD::OR:
27732774 if (!VT.isVector())
2774 return getConstant(VT.getIntegerVTBitMask(), VT);
2775 return getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
27752776 // For vectors, we can't easily build an all one vector, just return
27762777 // the LHS.
27772778 return N1;
52675267 // bits of the inputs before performing those operations.
52685268 if (FlipSigns) {
52695269 MVT EltVT = VT.getVectorElementType();
5270 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
5270 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5271 EltVT);
52715272 std::vector SignBits(VT.getVectorNumElements(), SignBit);
52725273 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
52735274 SignBits.size());
0 ; RUN: llvm-as < %s | llc -march=x86
1 ; PR3453
2
3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
4 target triple = "i386-pc-linux-gnu"
5 %struct.cl_engine = type { i32, i16, i32, i8**, i8**, i8*, i8*, i8*, i8*, i8*, i8*, i8* }
6 %struct.cl_limits = type { i32, i32, i32, i32, i16, i32 }
7 %struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
8 %struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
9 %struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
10 %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
11 %struct.cli_ctx = type { i8**, i32*, %struct.cli_matcher*, %struct.cl_engine*, %struct.cl_limits*, i32, i32, i32, i32, %struct.cli_dconf* }
12 %struct.cli_dconf = type { i32, i32, i32, i32, i32, i32, i32 }
13 %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
14
15 define fastcc i32 @cli_scanautoit(i32 %desc, %struct.cli_ctx* %ctx, i32 %offset) nounwind {
16 entry:
17 br i1 false, label %bb.i49.i72, label %bb14
18
19 bb.i49.i72: ; preds = %bb.i49.i72, %entry
20 %UNP.i1482.0 = phi i288 [ %.ins659, %bb.i49.i72 ], [ undef, %entry ] ; [#uses=1]
21 %0 = load i32* null, align 4 ; [#uses=1]
22 %1 = xor i32 %0, 17834 ; [#uses=1]
23 %2 = zext i32 %1 to i288 ; [#uses=1]
24 %3 = shl i288 %2, 160 ; [#uses=1]
25 %UNP.i1482.in658.mask = and i288 %UNP.i1482.0, -6277101733925179126504886505003981583386072424808101969921 ; [#uses=1]
26 %.ins659 = or i288 %3, %UNP.i1482.in658.mask ; [#uses=1]
27 br label %bb.i49.i72
28
29 bb14: ; preds = %entry
30 ret i32 -123
31 }
841841 // If sign-extended doesn't fit, does it fit as unsigned?
842842 unsigned ValueMask;
843843 unsigned UnsignedVal;
844 ValueMask = unsigned(MVT(VT).getIntegerVTBitMask());
844 ValueMask = unsigned(~uint32_t(0UL) >> (32-Size));
845845 UnsignedVal = unsigned(II->getValue());
846846
847847 if ((ValueMask & UnsignedVal) != UnsignedVal) {