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Covert this test to .s form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117684 91177308-0d34-0410-b5e6-96231b3b80d8 Owen Anderson 9 years ago
2 changed file(s) with 34 addition(s) and 122 deletion(s). Raw diff Collapse all Expand all
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test/MC/ARM/neon-convert-encoding.ll less more
None ; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
1
2 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
3 %tmp1 = load <2 x float>* %A
4 ; CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
5 %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
6 ret <2 x i32> %tmp2
7 }
8
9 define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
10 %tmp1 = load <2 x float>* %A
11 ; CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
12 %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
13 ret <2 x i32> %tmp2
14 }
15
16 define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
17 %tmp1 = load <2 x i32>* %A
18 ; CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
19 %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
20 ret <2 x float> %tmp2
21 }
22
23 define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
24 %tmp1 = load <2 x i32>* %A
25 ; CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
26 %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
27 ret <2 x float> %tmp2
28 }
29
30 define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
31 %tmp1 = load <4 x float>* %A
32 ; CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
33 %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
34 ret <4 x i32> %tmp2
35 }
36
37 define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
38 %tmp1 = load <4 x float>* %A
39 ; CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3]
40 %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
41 ret <4 x i32> %tmp2
42 }
43
44 define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
45 %tmp1 = load <4 x i32>* %A
46 ; CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
47 %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
48 ret <4 x float> %tmp2
49 }
50
51 define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
52 %tmp1 = load <4 x i32>* %A
53 ; CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3]
54 %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
55 ret <4 x float> %tmp2
56 }
57
58 define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
59 %tmp1 = load <2 x float>* %A
60 ; CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2
61 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
62 ret <2 x i32> %tmp2
63 }
64
65 define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
66 %tmp1 = load <2 x float>* %A
67 ; CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3]
68 %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
69 ret <2 x i32> %tmp2
70 }
71
72 define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
73 %tmp1 = load <2 x i32>* %A
74 ; CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
75 %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
76 ret <2 x float> %tmp2
77 }
78
79 define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
80 %tmp1 = load <2 x i32>* %A
81 ; CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
82 %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
83 ret <2 x float> %tmp2
84 }
85
86 declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
87 declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
88 declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
89 declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
90
91 define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
92 %tmp1 = load <4 x float>* %A
93 ; CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2]
94 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
95 ret <4 x i32> %tmp2
96 }
97
98 define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
99 %tmp1 = load <4 x float>* %A
100 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
101 ret <4 x i32> %tmp2
102 }
103
104 define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
105 %tmp1 = load <4 x i32>* %A
106 ; CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3]
107 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
108 ret <4 x float> %tmp2
109 }
110
111 define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
112 %tmp1 = load <4 x i32>* %A
113 ; CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
114 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
115 ret <4 x float> %tmp2
116 }
117
118 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
119 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
120 declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
121 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
0 // RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
1
2 // CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
3 vcvt.s32.f32 d16, d16
4 // CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
5 vcvt.u32.f32 d16, d16
6 // CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
7 vcvt.f32.s32 d16, d16
8 // CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
9 vcvt.f32.u32 d16, d16
10 // CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
11 vcvt.s32.f32 q8, q8
12 // CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3]
13 vcvt.u32.f32 q8, q8
14 // CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
15 vcvt.f32.s32 q8, q8
16 // CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3]
17 vcvt.f32.u32 q8, q8
18 // CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2]
19 vcvt.s32.f32 d16, d16, #1
20 // CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3]
21 vcvt.u32.f32 d16, d16, #1
22 // CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
23 vcvt.f32.s32 d16, d16, #1
24 // CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
25 vcvt.f32.u32 d16, d16, #1
26 // CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2]
27 vcvt.s32.f32 q8, q8, #1
28 // CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3]
29 vcvt.u32.f32 q8, q8, #1
30 // CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2]
31 vcvt.f32.s32 q8, q8, #1
32 // CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
33 vcvt.f32.u32 q8, q8, #1