llvm.org GIT mirror llvm / affc53d
[mips] Splitting up class definition from implementation. Also removed some unnecessary #includes. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204320 91177308-0d34-0410-b5e6-96231b3b80d8 Matheus Almeida 5 years ago
2 changed file(s) with 172 addition(s) and 130 deletion(s). Raw diff Collapse all Expand all
1010 //
1111 //===----------------------------------------------------------------------===//
1212 //
13
1314 #define DEBUG_TYPE "mccodeemitter"
14 #include "MCTargetDesc/MipsBaseInfo.h"
15
16 #include "MipsMCCodeEmitter.h"
1517 #include "MCTargetDesc/MipsFixupKinds.h"
1618 #include "MCTargetDesc/MipsMCExpr.h"
1719 #include "MCTargetDesc/MipsMCTargetDesc.h"
1820 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/MC/MCCodeEmitter.h"
21 #include "llvm/ADT/SmallVector.h"
2122 #include "llvm/MC/MCContext.h"
2223 #include "llvm/MC/MCExpr.h"
2324 #include "llvm/MC/MCInst.h"
2425 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCFixup.h"
2627 #include "llvm/MC/MCSubtargetInfo.h"
2728 #include "llvm/Support/raw_ostream.h"
2829
2930 #define GET_INSTRMAP_INFO
3031 #include "MipsGenInstrInfo.inc"
31
32 using namespace llvm;
33
34 namespace {
35 class MipsMCCodeEmitter : public MCCodeEmitter {
36 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
37 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
38 const MCInstrInfo &MCII;
39 MCContext &Ctx;
40 bool IsLittleEndian;
41
42 bool isMicroMips(const MCSubtargetInfo &STI) const {
43 return STI.getFeatureBits() & Mips::FeatureMicroMips;
44 }
45
46 public:
47 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) :
48 MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) { }
49
50 ~MipsMCCodeEmitter() {}
51
52 void EmitByte(unsigned char C, raw_ostream &OS) const {
53 OS << (char)C;
54 }
55
56 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
57 raw_ostream &OS) const {
58 // Output the instruction encoding in little endian byte order.
59 // Little-endian byte ordering:
60 // mips32r2: 4 | 3 | 2 | 1
61 // microMIPS: 2 | 1 | 4 | 3
62 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
63 EmitInstruction(Val>>16, 2, STI, OS);
64 EmitInstruction(Val, 2, STI, OS);
65 } else {
66 for (unsigned i = 0; i < Size; ++i) {
67 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
68 EmitByte((Val >> Shift) & 0xff, OS);
69 }
70 }
71 }
72
73 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
74 SmallVectorImpl &Fixups,
75 const MCSubtargetInfo &STI) const;
76
77 // getBinaryCodeForInstr - TableGen'erated function for getting the
78 // binary encoding for an instruction.
79 uint64_t getBinaryCodeForInstr(const MCInst &MI,
80 SmallVectorImpl &Fixups,
81 const MCSubtargetInfo &STI) const;
82
83 // getBranchJumpOpValue - Return binary encoding of the jump
84 // target operand. If the machine operand requires relocation,
85 // record the relocation and return zero.
86 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
87 SmallVectorImpl &Fixups,
88 const MCSubtargetInfo &STI) const;
89
90 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
91 // target operand. If the machine operand requires relocation,
92 // record the relocation and return zero.
93 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
94 SmallVectorImpl &Fixups,
95 const MCSubtargetInfo &STI) const;
96
97 // getBranchTargetOpValue - Return binary encoding of the branch
98 // target operand. If the machine operand requires relocation,
99 // record the relocation and return zero.
100 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
101 SmallVectorImpl &Fixups,
102 const MCSubtargetInfo &STI) const;
103
104 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
105 // target operand. If the machine operand requires relocation,
106 // record the relocation and return zero.
107 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
108 SmallVectorImpl &Fixups,
109 const MCSubtargetInfo &STI) const;
110
111 // getMachineOpValue - Return binary encoding of operand. If the machin
112 // operand requires relocation, record the relocation and return zero.
113 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
114 SmallVectorImpl &Fixups,
115 const MCSubtargetInfo &STI) const;
116
117 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
118 SmallVectorImpl &Fixups,
119 const MCSubtargetInfo &STI) const;
120
121 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
122 SmallVectorImpl &Fixups,
123 const MCSubtargetInfo &STI) const;
124 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
125 SmallVectorImpl &Fixups,
126 const MCSubtargetInfo &STI) const;
127 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
128 SmallVectorImpl &Fixups,
129 const MCSubtargetInfo &STI) const;
130 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
131 SmallVectorImpl &Fixups,
132 const MCSubtargetInfo &STI) const;
133
134 // getLSAImmEncoding - Return binary encoding of LSA immediate.
135 unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
136 SmallVectorImpl &Fixups,
137 const MCSubtargetInfo &STI) const;
138
139 unsigned
140 getExprOpValue(const MCExpr *Expr,SmallVectorImpl &Fixups,
141 const MCSubtargetInfo &STI) const;
142
143 }; // class MipsMCCodeEmitter
144 } // namespace
145
146 MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
147 const MCRegisterInfo &MRI,
148 const MCSubtargetInfo &STI,
149 MCContext &Ctx)
150 {
32 #undef GET_INSTRMAP_INFO
33
34 namespace llvm {
35 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
36 const MCRegisterInfo &MRI,
37 const MCSubtargetInfo &STI,
38 MCContext &Ctx) {
15139 return new MipsMCCodeEmitter(MCII, Ctx, false);
15240 }
15341
154 MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
155 const MCRegisterInfo &MRI,
156 const MCSubtargetInfo &STI,
157 MCContext &Ctx)
158 {
42 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
43 const MCRegisterInfo &MRI,
44 const MCSubtargetInfo &STI,
45 MCContext &Ctx) {
15946 return new MipsMCCodeEmitter(MCII, Ctx, true);
16047 }
161
48 } // End of namespace llvm.
16249
16350 // If the D instruction has a shift amount that is greater
16451 // than 31 (checked in calling routine), lower it to a D32 instruction
223110 InstIn.getOperand(3).setImm(size - 32);
224111 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTM : Mips::DINSM);
225112 return;
113 }
114
115 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
116 return STI.getFeatureBits() & Mips::FeatureMicroMips;
117 }
118
119 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
120 OS << (char)C;
121 }
122
123 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
124 const MCSubtargetInfo &STI,
125 raw_ostream &OS) const {
126 // Output the instruction encoding in little endian byte order.
127 // Little-endian byte ordering:
128 // mips32r2: 4 | 3 | 2 | 1
129 // microMIPS: 2 | 1 | 4 | 3
130 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
131 EmitInstruction(Val >> 16, 2, STI, OS);
132 EmitInstruction(Val, 2, STI, OS);
133 } else {
134 for (unsigned i = 0; i < Size; ++i) {
135 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
136 EmitByte((Val >> Shift) & 0xff, OS);
137 }
138 }
226139 }
227140
228141 /// EncodeInstruction - Emit the instruction.
0 //===-- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code -----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MipsMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 //
13
14 #ifndef MIPS_MC_CODE_EMITTER_H
15 #define MIPS_MC_CODE_EMITTER_H
16
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/Support/DataTypes.h"
19
20 using namespace llvm;
21
22 // Forward declarations.
23 namespace llvm {
24 class MCContext;
25 class MCExpr;
26 class MCInst;
27 class MCInstrInfo;
28 class MCFixup;
29 class MCOperand;
30 class MCSubtargetInfo;
31 class raw_ostream;
32 }
33
34 namespace {
35
36 class MipsMCCodeEmitter : public MCCodeEmitter {
37 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
38 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
39 const MCInstrInfo &MCII;
40 MCContext &Ctx;
41 bool IsLittleEndian;
42
43 bool isMicroMips(const MCSubtargetInfo &STI) const;
44
45 public:
46 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle)
47 : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}
48
49 ~MipsMCCodeEmitter() {}
50
51 void EmitByte(unsigned char C, raw_ostream &OS) const;
52
53 void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
54 raw_ostream &OS) const;
55
56 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
57 SmallVectorImpl &Fixups,
58 const MCSubtargetInfo &STI) const;
59
60 // getBinaryCodeForInstr - TableGen'erated function for getting the
61 // binary encoding for an instruction.
62 uint64_t getBinaryCodeForInstr(const MCInst &MI,
63 SmallVectorImpl &Fixups,
64 const MCSubtargetInfo &STI) const;
65
66 // getBranchJumpOpValue - Return binary encoding of the jump
67 // target operand. If the machine operand requires relocation,
68 // record the relocation and return zero.
69 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
70 SmallVectorImpl &Fixups,
71 const MCSubtargetInfo &STI) const;
72
73 // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump
74 // target operand. If the machine operand requires relocation,
75 // record the relocation and return zero.
76 unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
77 SmallVectorImpl &Fixups,
78 const MCSubtargetInfo &STI) const;
79
80 // getBranchTargetOpValue - Return binary encoding of the branch
81 // target operand. If the machine operand requires relocation,
82 // record the relocation and return zero.
83 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
84 SmallVectorImpl &Fixups,
85 const MCSubtargetInfo &STI) const;
86
87 // getBranchTargetOpValue - Return binary encoding of the microMIPS branch
88 // target operand. If the machine operand requires relocation,
89 // record the relocation and return zero.
90 unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
91 SmallVectorImpl &Fixups,
92 const MCSubtargetInfo &STI) const;
93
94 // getMachineOpValue - Return binary encoding of operand. If the machin
95 // operand requires relocation, record the relocation and return zero.
96 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
97 SmallVectorImpl &Fixups,
98 const MCSubtargetInfo &STI) const;
99
100 unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
101 SmallVectorImpl &Fixups,
102 const MCSubtargetInfo &STI) const;
103
104 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
105 SmallVectorImpl &Fixups,
106 const MCSubtargetInfo &STI) const;
107 unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
108 SmallVectorImpl &Fixups,
109 const MCSubtargetInfo &STI) const;
110 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
111 SmallVectorImpl &Fixups,
112 const MCSubtargetInfo &STI) const;
113 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
114 SmallVectorImpl &Fixups,
115 const MCSubtargetInfo &STI) const;
116
117 // getLSAImmEncoding - Return binary encoding of LSA immediate.
118 unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo,
119 SmallVectorImpl &Fixups,
120 const MCSubtargetInfo &STI) const;
121
122 unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl &Fixups,
123 const MCSubtargetInfo &STI) const;
124
125 }; // class MipsMCCodeEmitter
126 } // namespace
127
128 #endif