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[AVX512] Remove masked logic op intrinsics and autoupgrade them to native IR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275155 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 4 years ago
7 changed file(s) with 1197 addition(s) and 1276 deletion(s). Raw diff Collapse all Expand all
52285228 llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
52295229
52305230 }
5231 //Bitwise Ops
5232 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
5233 def int_x86_avx512_mask_pand_d_128 : GCCBuiltin<"__builtin_ia32_pandd128_mask">,
5234 Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
5235 llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
5236 def int_x86_avx512_mask_pand_d_256 : GCCBuiltin<"__builtin_ia32_pandd256_mask">,
5237 Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,
5238 llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
5239 def int_x86_avx512_mask_pand_d_512 : GCCBuiltin<"__builtin_ia32_pandd512_mask">,
5240 Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
5241 llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
5242 def int_x86_avx512_mask_pand_q_128 : GCCBuiltin<"__builtin_ia32_pandq128_mask">,
5243 Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
5244 llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
5245 def int_x86_avx512_mask_pand_q_256 : GCCBuiltin<"__builtin_ia32_pandq256_mask">,
5246 Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty,
5247 llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
5248 def int_x86_avx512_mask_pand_q_512 : GCCBuiltin<"__builtin_ia32_pandq512_mask">,
5249 Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
5250 llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
5251 def int_x86_avx512_mask_pandn_d_128 : GCCBuiltin<"__builtin_ia32_pandnd128_mask">,
5252 Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
5253 llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
5254 def int_x86_avx512_mask_pandn_d_256 : GCCBuiltin<"__builtin_ia32_pandnd256_mask">,
5255 Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,
5256 llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
5257 def int_x86_avx512_mask_pandn_d_512 : GCCBuiltin<"__builtin_ia32_pandnd512_mask">,
5258 Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
5259 llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
5260 def int_x86_avx512_mask_pandn_q_128 : GCCBuiltin<"__builtin_ia32_pandnq128_mask">,
5261 Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
5262 llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
5263 def int_x86_avx512_mask_pandn_q_256 : GCCBuiltin<"__builtin_ia32_pandnq256_mask">,
5264 Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty,
5265 llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
5266 def int_x86_avx512_mask_pandn_q_512 : GCCBuiltin<"__builtin_ia32_pandnq512_mask">,
5267 Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
5268 llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
5269 def int_x86_avx512_mask_por_d_128 : GCCBuiltin<"__builtin_ia32_pord128_mask">,
5270 Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
5271 llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
5272 def int_x86_avx512_mask_por_d_256 : GCCBuiltin<"__builtin_ia32_pord256_mask">,
5273 Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,
5274 llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
5275 def int_x86_avx512_mask_por_d_512 : GCCBuiltin<"__builtin_ia32_pord512_mask">,
5276 Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
5277 llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
5278 def int_x86_avx512_mask_por_q_128 : GCCBuiltin<"__builtin_ia32_porq128_mask">,
5279 Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
5280 llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
5281 def int_x86_avx512_mask_por_q_256 : GCCBuiltin<"__builtin_ia32_porq256_mask">,
5282 Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty,
5283 llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
5284 def int_x86_avx512_mask_por_q_512 : GCCBuiltin<"__builtin_ia32_porq512_mask">,
5285 Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
5286 llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
5287 def int_x86_avx512_mask_pxor_d_128 : GCCBuiltin<"__builtin_ia32_pxord128_mask">,
5288 Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty,
5289 llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
5290 def int_x86_avx512_mask_pxor_d_256 : GCCBuiltin<"__builtin_ia32_pxord256_mask">,
5291 Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_v8i32_ty,
5292 llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
5293 def int_x86_avx512_mask_pxor_d_512 : GCCBuiltin<"__builtin_ia32_pxord512_mask">,
5294 Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty,
5295 llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;
5296 def int_x86_avx512_mask_pxor_q_128 : GCCBuiltin<"__builtin_ia32_pxorq128_mask">,
5297 Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty,
5298 llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
5299 def int_x86_avx512_mask_pxor_q_256 : GCCBuiltin<"__builtin_ia32_pxorq256_mask">,
5300 Intrinsic<[llvm_v4i64_ty], [llvm_v4i64_ty, llvm_v4i64_ty,
5301 llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
5302 def int_x86_avx512_mask_pxor_q_512 : GCCBuiltin<"__builtin_ia32_pxorq512_mask">,
5303 Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_v8i64_ty,
5304 llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;
5305 }
5231
53065232 // Arithmetic ops
53075233 let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
53085234
238238 Name.startswith("avx512.mask.punpckh") ||
239239 Name.startswith("avx512.mask.unpckl.") ||
240240 Name.startswith("avx512.mask.unpckh.") ||
241 Name.startswith("avx512.mask.pand.") ||
242 Name.startswith("avx512.mask.pandn.") ||
243 Name.startswith("avx512.mask.por.") ||
244 Name.startswith("avx512.mask.pxor.") ||
241245 Name.startswith("sse41.pmovsx") ||
242246 Name.startswith("sse41.pmovzx") ||
243247 Name.startswith("avx2.pmovsx") ||
11801184
11811185 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
11821186 CI->getArgOperand(2));
1187 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) {
1188 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1));
1189 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1190 CI->getArgOperand(2));
1191 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) {
1192 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)),
1193 CI->getArgOperand(1));
1194 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1195 CI->getArgOperand(2));
1196 } else if (IsX86 && Name.startswith("avx512.mask.por.")) {
1197 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1));
1198 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1199 CI->getArgOperand(2));
1200 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) {
1201 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1));
1202 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1203 CI->getArgOperand(2));
11831204 } else {
11841205 llvm_unreachable("Unknown function for CallInst upgrade.");
11851206 }
874874 X86_INTRINSIC_DATA(avx512_mask_paddus_w_128, INTR_TYPE_2OP_MASK, X86ISD::ADDUS, 0),
875875 X86_INTRINSIC_DATA(avx512_mask_paddus_w_256, INTR_TYPE_2OP_MASK, X86ISD::ADDUS, 0),
876876 X86_INTRINSIC_DATA(avx512_mask_paddus_w_512, INTR_TYPE_2OP_MASK, X86ISD::ADDUS, 0),
877 X86_INTRINSIC_DATA(avx512_mask_pand_d_128, INTR_TYPE_2OP_MASK, ISD::AND, 0),
878 X86_INTRINSIC_DATA(avx512_mask_pand_d_256, INTR_TYPE_2OP_MASK, ISD::AND, 0),
879 X86_INTRINSIC_DATA(avx512_mask_pand_d_512, INTR_TYPE_2OP_MASK, ISD::AND, 0),
880 X86_INTRINSIC_DATA(avx512_mask_pand_q_128, INTR_TYPE_2OP_MASK, ISD::AND, 0),
881 X86_INTRINSIC_DATA(avx512_mask_pand_q_256, INTR_TYPE_2OP_MASK, ISD::AND, 0),
882 X86_INTRINSIC_DATA(avx512_mask_pand_q_512, INTR_TYPE_2OP_MASK, ISD::AND, 0),
883 X86_INTRINSIC_DATA(avx512_mask_pandn_d_128, INTR_TYPE_2OP_MASK, X86ISD::ANDNP, 0),
884 X86_INTRINSIC_DATA(avx512_mask_pandn_d_256, INTR_TYPE_2OP_MASK, X86ISD::ANDNP, 0),
885 X86_INTRINSIC_DATA(avx512_mask_pandn_d_512, INTR_TYPE_2OP_MASK, X86ISD::ANDNP, 0),
886 X86_INTRINSIC_DATA(avx512_mask_pandn_q_128, INTR_TYPE_2OP_MASK, X86ISD::ANDNP, 0),
887 X86_INTRINSIC_DATA(avx512_mask_pandn_q_256, INTR_TYPE_2OP_MASK, X86ISD::ANDNP, 0),
888 X86_INTRINSIC_DATA(avx512_mask_pandn_q_512, INTR_TYPE_2OP_MASK, X86ISD::ANDNP, 0),
889877 X86_INTRINSIC_DATA(avx512_mask_pavg_b_128, INTR_TYPE_2OP_MASK, X86ISD::AVG, 0),
890878 X86_INTRINSIC_DATA(avx512_mask_pavg_b_256, INTR_TYPE_2OP_MASK, X86ISD::AVG, 0),
891879 X86_INTRINSIC_DATA(avx512_mask_pavg_b_512, INTR_TYPE_2OP_MASK, X86ISD::AVG, 0),
12201208 X86ISD::PMULUDQ, 0),
12211209 X86_INTRINSIC_DATA(avx512_mask_pmulu_dq_512, INTR_TYPE_2OP_MASK,
12221210 X86ISD::PMULUDQ, 0),
1223 X86_INTRINSIC_DATA(avx512_mask_por_d_128, INTR_TYPE_2OP_MASK, ISD::OR, 0),
1224 X86_INTRINSIC_DATA(avx512_mask_por_d_256, INTR_TYPE_2OP_MASK, ISD::OR, 0),
1225 X86_INTRINSIC_DATA(avx512_mask_por_d_512, INTR_TYPE_2OP_MASK, ISD::OR, 0),
1226 X86_INTRINSIC_DATA(avx512_mask_por_q_128, INTR_TYPE_2OP_MASK, ISD::OR, 0),
1227 X86_INTRINSIC_DATA(avx512_mask_por_q_256, INTR_TYPE_2OP_MASK, ISD::OR, 0),
1228 X86_INTRINSIC_DATA(avx512_mask_por_q_512, INTR_TYPE_2OP_MASK, ISD::OR, 0),
12291211 X86_INTRINSIC_DATA(avx512_mask_prol_d_128, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VROTLI, 0),
12301212 X86_INTRINSIC_DATA(avx512_mask_prol_d_256, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VROTLI, 0),
12311213 X86_INTRINSIC_DATA(avx512_mask_prol_d_512, INTR_TYPE_2OP_IMM8_MASK, X86ISD::VROTLI, 0),
13731355 X86ISD::VPTERNLOG, 0),
13741356 X86_INTRINSIC_DATA(avx512_mask_pternlog_q_512, TERLOG_OP_MASK,
13751357 X86ISD::VPTERNLOG, 0),
1376 X86_INTRINSIC_DATA(avx512_mask_pxor_d_128, INTR_TYPE_2OP_MASK, ISD::XOR, 0),
1377 X86_INTRINSIC_DATA(avx512_mask_pxor_d_256, INTR_TYPE_2OP_MASK, ISD::XOR, 0),
1378 X86_INTRINSIC_DATA(avx512_mask_pxor_d_512, INTR_TYPE_2OP_MASK, ISD::XOR, 0),
1379 X86_INTRINSIC_DATA(avx512_mask_pxor_q_128, INTR_TYPE_2OP_MASK, ISD::XOR, 0),
1380 X86_INTRINSIC_DATA(avx512_mask_pxor_q_256, INTR_TYPE_2OP_MASK, ISD::XOR, 0),
1381 X86_INTRINSIC_DATA(avx512_mask_pxor_q_512, INTR_TYPE_2OP_MASK, ISD::XOR, 0),
13821358 X86_INTRINSIC_DATA(avx512_mask_range_pd_128, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
13831359 X86_INTRINSIC_DATA(avx512_mask_range_pd_256, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
13841360 X86_INTRINSIC_DATA(avx512_mask_range_pd_512, INTR_TYPE_3OP_MASK_RM, X86ISD::VRANGE, 0),
955955 ret void
956956 }
957957
958 define <16 x i32> @test_xor_epi32(<16 x i32> %a, <16 x i32> %b) {
959 ; CHECK-LABEL: test_xor_epi32:
960 ; CHECK: ## BB#0:
961 ; CHECK-NEXT: vpxord %zmm1, %zmm0, %zmm0
962 ; CHECK-NEXT: retq
963 %res = call <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
964 ret < 16 x i32> %res
965 }
966
967 define <16 x i32> @test_mask_xor_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
968 ; CHECK-LABEL: test_mask_xor_epi32:
969 ; CHECK: ## BB#0:
970 ; CHECK-NEXT: kmovw %edi, %k1
971 ; CHECK-NEXT: vpxord %zmm1, %zmm0, %zmm2 {%k1}
972 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
973 ; CHECK-NEXT: retq
974 %res = call <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
975 ret < 16 x i32> %res
976 }
977
978 declare <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
979
980 define <16 x i32> @test_or_epi32(<16 x i32> %a, <16 x i32> %b) {
981 ; CHECK-LABEL: test_or_epi32:
982 ; CHECK: ## BB#0:
983 ; CHECK-NEXT: vpord %zmm1, %zmm0, %zmm0
984 ; CHECK-NEXT: retq
985 %res = call <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
986 ret < 16 x i32> %res
987 }
988
989 define <16 x i32> @test_mask_or_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
990 ; CHECK-LABEL: test_mask_or_epi32:
991 ; CHECK: ## BB#0:
992 ; CHECK-NEXT: kmovw %edi, %k1
993 ; CHECK-NEXT: vpord %zmm1, %zmm0, %zmm2 {%k1}
994 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
995 ; CHECK-NEXT: retq
996 %res = call <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
997 ret < 16 x i32> %res
998 }
999
1000 declare <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1001
1002 define <16 x i32> @test_and_epi32(<16 x i32> %a, <16 x i32> %b) {
1003 ; CHECK-LABEL: test_and_epi32:
1004 ; CHECK: ## BB#0:
1005 ; CHECK-NEXT: vpandd %zmm1, %zmm0, %zmm0
1006 ; CHECK-NEXT: retq
1007 %res = call <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
1008 ret < 16 x i32> %res
1009 }
1010
1011 define <16 x i32> @test_mask_and_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
1012 ; CHECK-LABEL: test_mask_and_epi32:
1013 ; CHECK: ## BB#0:
1014 ; CHECK-NEXT: kmovw %edi, %k1
1015 ; CHECK-NEXT: vpandd %zmm1, %zmm0, %zmm2 {%k1}
1016 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
1017 ; CHECK-NEXT: retq
1018 %res = call <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1019 ret < 16 x i32> %res
1020 }
1021
1022 declare <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1023
1024 define <8 x i64> @test_xor_epi64(<8 x i64> %a, <8 x i64> %b) {
1025 ; CHECK-LABEL: test_xor_epi64:
1026 ; CHECK: ## BB#0:
1027 ; CHECK-NEXT: vpxorq %zmm1, %zmm0, %zmm0
1028 ; CHECK-NEXT: retq
1029 %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
1030 ret < 8 x i64> %res
1031 }
1032
1033 define <8 x i64> @test_mask_xor_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
1034 ; CHECK-LABEL: test_mask_xor_epi64:
1035 ; CHECK: ## BB#0:
1036 ; CHECK-NEXT: kmovw %edi, %k1
1037 ; CHECK-NEXT: vpxorq %zmm1, %zmm0, %zmm2 {%k1}
1038 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
1039 ; CHECK-NEXT: retq
1040 %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1041 ret < 8 x i64> %res
1042 }
1043
1044 declare <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
1045
1046 define <8 x i64> @test_or_epi64(<8 x i64> %a, <8 x i64> %b) {
1047 ; CHECK-LABEL: test_or_epi64:
1048 ; CHECK: ## BB#0:
1049 ; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm0
1050 ; CHECK-NEXT: retq
1051 %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
1052 ret < 8 x i64> %res
1053 }
1054
1055 define <8 x i64> @test_mask_or_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
1056 ; CHECK-LABEL: test_mask_or_epi64:
1057 ; CHECK: ## BB#0:
1058 ; CHECK-NEXT: kmovw %edi, %k1
1059 ; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm2 {%k1}
1060 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
1061 ; CHECK-NEXT: retq
1062 %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1063 ret < 8 x i64> %res
1064 }
1065
1066 declare <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
1067
1068 define <8 x i64> @test_and_epi64(<8 x i64> %a, <8 x i64> %b) {
1069 ; CHECK-LABEL: test_and_epi64:
1070 ; CHECK: ## BB#0:
1071 ; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm0
1072 ; CHECK-NEXT: retq
1073 %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
1074 ret < 8 x i64> %res
1075 }
1076
1077 define <8 x i64> @test_mask_and_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
1078 ; CHECK-LABEL: test_mask_and_epi64:
1079 ; CHECK: ## BB#0:
1080 ; CHECK-NEXT: kmovw %edi, %k1
1081 ; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm2 {%k1}
1082 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
1083 ; CHECK-NEXT: retq
1084 %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
1085 ret < 8 x i64> %res
1086 }
1087
1088 declare <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
19451945 ret <8 x double> %res
19461946 }
19471947
1948 define <16 x i32> @test_xor_epi32(<16 x i32> %a, <16 x i32> %b) {
1949 ; CHECK-LABEL: test_xor_epi32:
1950 ; CHECK: ## BB#0:
1951 ; CHECK-NEXT: vpxord %zmm1, %zmm0, %zmm0
1952 ; CHECK-NEXT: retq
1953 %res = call <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
1954 ret < 16 x i32> %res
1955 }
1956
1957 define <16 x i32> @test_mask_xor_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
1958 ; CHECK-LABEL: test_mask_xor_epi32:
1959 ; CHECK: ## BB#0:
1960 ; CHECK-NEXT: kmovw %edi, %k1
1961 ; CHECK-NEXT: vpxord %zmm1, %zmm0, %zmm2 {%k1}
1962 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
1963 ; CHECK-NEXT: retq
1964 %res = call <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1965 ret < 16 x i32> %res
1966 }
1967
1968 declare <16 x i32> @llvm.x86.avx512.mask.pxor.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1969
1970 define <16 x i32> @test_or_epi32(<16 x i32> %a, <16 x i32> %b) {
1971 ; CHECK-LABEL: test_or_epi32:
1972 ; CHECK: ## BB#0:
1973 ; CHECK-NEXT: vpord %zmm1, %zmm0, %zmm0
1974 ; CHECK-NEXT: retq
1975 %res = call <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
1976 ret < 16 x i32> %res
1977 }
1978
1979 define <16 x i32> @test_mask_or_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
1980 ; CHECK-LABEL: test_mask_or_epi32:
1981 ; CHECK: ## BB#0:
1982 ; CHECK-NEXT: kmovw %edi, %k1
1983 ; CHECK-NEXT: vpord %zmm1, %zmm0, %zmm2 {%k1}
1984 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
1985 ; CHECK-NEXT: retq
1986 %res = call <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
1987 ret < 16 x i32> %res
1988 }
1989
1990 declare <16 x i32> @llvm.x86.avx512.mask.por.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
1991
1992 define <16 x i32> @test_and_epi32(<16 x i32> %a, <16 x i32> %b) {
1993 ; CHECK-LABEL: test_and_epi32:
1994 ; CHECK: ## BB#0:
1995 ; CHECK-NEXT: vpandd %zmm1, %zmm0, %zmm0
1996 ; CHECK-NEXT: retq
1997 %res = call <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32> %a,<16 x i32> %b, <16 x i32>zeroinitializer, i16 -1)
1998 ret < 16 x i32> %res
1999 }
2000
2001 define <16 x i32> @test_mask_and_epi32(<16 x i32> %a,<16 x i32> %b, <16 x i32> %passThru, i16 %mask) {
2002 ; CHECK-LABEL: test_mask_and_epi32:
2003 ; CHECK: ## BB#0:
2004 ; CHECK-NEXT: kmovw %edi, %k1
2005 ; CHECK-NEXT: vpandd %zmm1, %zmm0, %zmm2 {%k1}
2006 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
2007 ; CHECK-NEXT: retq
2008 %res = call <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32> %a, <16 x i32> %b, <16 x i32> %passThru, i16 %mask)
2009 ret < 16 x i32> %res
2010 }
2011
2012 declare <16 x i32> @llvm.x86.avx512.mask.pand.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)
2013
2014 define <8 x i64> @test_xor_epi64(<8 x i64> %a, <8 x i64> %b) {
2015 ; CHECK-LABEL: test_xor_epi64:
2016 ; CHECK: ## BB#0:
2017 ; CHECK-NEXT: vpxorq %zmm1, %zmm0, %zmm0
2018 ; CHECK-NEXT: retq
2019 %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
2020 ret < 8 x i64> %res
2021 }
2022
2023 define <8 x i64> @test_mask_xor_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
2024 ; CHECK-LABEL: test_mask_xor_epi64:
2025 ; CHECK: ## BB#0:
2026 ; CHECK-NEXT: kmovw %edi, %k1
2027 ; CHECK-NEXT: vpxorq %zmm1, %zmm0, %zmm2 {%k1}
2028 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
2029 ; CHECK-NEXT: retq
2030 %res = call <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
2031 ret < 8 x i64> %res
2032 }
2033
2034 declare <8 x i64> @llvm.x86.avx512.mask.pxor.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
2035
2036 define <8 x i64> @test_or_epi64(<8 x i64> %a, <8 x i64> %b) {
2037 ; CHECK-LABEL: test_or_epi64:
2038 ; CHECK: ## BB#0:
2039 ; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm0
2040 ; CHECK-NEXT: retq
2041 %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
2042 ret < 8 x i64> %res
2043 }
2044
2045 define <8 x i64> @test_mask_or_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
2046 ; CHECK-LABEL: test_mask_or_epi64:
2047 ; CHECK: ## BB#0:
2048 ; CHECK-NEXT: kmovw %edi, %k1
2049 ; CHECK-NEXT: vporq %zmm1, %zmm0, %zmm2 {%k1}
2050 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
2051 ; CHECK-NEXT: retq
2052 %res = call <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
2053 ret < 8 x i64> %res
2054 }
2055
2056 declare <8 x i64> @llvm.x86.avx512.mask.por.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
2057
2058 define <8 x i64> @test_and_epi64(<8 x i64> %a, <8 x i64> %b) {
2059 ; CHECK-LABEL: test_and_epi64:
2060 ; CHECK: ## BB#0:
2061 ; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm0
2062 ; CHECK-NEXT: retq
2063 %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a,<8 x i64> %b, <8 x i64>zeroinitializer, i8 -1)
2064 ret < 8 x i64> %res
2065 }
2066
2067 define <8 x i64> @test_mask_and_epi64(<8 x i64> %a,<8 x i64> %b, <8 x i64> %passThru, i8 %mask) {
2068 ; CHECK-LABEL: test_mask_and_epi64:
2069 ; CHECK: ## BB#0:
2070 ; CHECK-NEXT: kmovw %edi, %k1
2071 ; CHECK-NEXT: vpandq %zmm1, %zmm0, %zmm2 {%k1}
2072 ; CHECK-NEXT: vmovaps %zmm2, %zmm0
2073 ; CHECK-NEXT: retq
2074 %res = call <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64> %a, <8 x i64> %b, <8 x i64> %passThru, i8 %mask)
2075 ret < 8 x i64> %res
2076 }
2077
2078 declare <8 x i64> @llvm.x86.avx512.mask.pand.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)
2079
2080
20811948 define <16 x i32> @test_mask_add_epi32_rr(<16 x i32> %a, <16 x i32> %b) {
20821949 ; CHECK-LABEL: test_mask_add_epi32_rr:
20831950 ; CHECK: ## BB#0:
14931493 %res2 = add <4 x i64> %res, %res1
14941494 ret <4 x i64> %res2
14951495 }
1496
1497 define <4 x i32> @test_mask_and_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
1498 ; CHECK-LABEL: test_mask_and_epi32_rr_128:
1499 ; CHECK: ## BB#0:
1500 ; CHECK-NEXT: vpandd %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdb,0xc1]
1501 ; CHECK-NEXT: retq ## encoding: [0xc3]
1502 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1503 ret <4 x i32> %res
1504 }
1505
1506 define <4 x i32> @test_mask_and_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
1507 ; CHECK-LABEL: test_mask_and_epi32_rrk_128:
1508 ; CHECK: ## BB#0:
1509 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1510 ; CHECK-NEXT: vpandd %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdb,0xd1]
1511 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
1512 ; CHECK-NEXT: retq ## encoding: [0xc3]
1513 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1514 ret <4 x i32> %res
1515 }
1516
1517 define <4 x i32> @test_mask_and_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
1518 ; CHECK-LABEL: test_mask_and_epi32_rrkz_128:
1519 ; CHECK: ## BB#0:
1520 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1521 ; CHECK-NEXT: vpandd %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdb,0xc1]
1522 ; CHECK-NEXT: retq ## encoding: [0xc3]
1523 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1524 ret <4 x i32> %res
1525 }
1526
1527 define <4 x i32> @test_mask_and_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
1528 ; CHECK-LABEL: test_mask_and_epi32_rm_128:
1529 ; CHECK: ## BB#0:
1530 ; CHECK-NEXT: vpandd (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdb,0x07]
1531 ; CHECK-NEXT: retq ## encoding: [0xc3]
1532 %b = load <4 x i32>, <4 x i32>* %ptr_b
1533 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1534 ret <4 x i32> %res
1535 }
1536
1537 define <4 x i32> @test_mask_and_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
1538 ; CHECK-LABEL: test_mask_and_epi32_rmk_128:
1539 ; CHECK: ## BB#0:
1540 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1541 ; CHECK-NEXT: vpandd (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdb,0x0f]
1542 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1543 ; CHECK-NEXT: retq ## encoding: [0xc3]
1544 %b = load <4 x i32>, <4 x i32>* %ptr_b
1545 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1546 ret <4 x i32> %res
1547 }
1548
1549 define <4 x i32> @test_mask_and_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
1550 ; CHECK-LABEL: test_mask_and_epi32_rmkz_128:
1551 ; CHECK: ## BB#0:
1552 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1553 ; CHECK-NEXT: vpandd (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdb,0x07]
1554 ; CHECK-NEXT: retq ## encoding: [0xc3]
1555 %b = load <4 x i32>, <4 x i32>* %ptr_b
1556 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1557 ret <4 x i32> %res
1558 }
1559
1560 define <4 x i32> @test_mask_and_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
1561 ; CHECK-LABEL: test_mask_and_epi32_rmb_128:
1562 ; CHECK: ## BB#0:
1563 ; CHECK-NEXT: vpandd (%rdi){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xdb,0x07]
1564 ; CHECK-NEXT: retq ## encoding: [0xc3]
1565 %q = load i32, i32* %ptr_b
1566 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1567 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1568 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1569 ret <4 x i32> %res
1570 }
1571
1572 define <4 x i32> @test_mask_and_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
1573 ; CHECK-LABEL: test_mask_and_epi32_rmbk_128:
1574 ; CHECK: ## BB#0:
1575 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1576 ; CHECK-NEXT: vpandd (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xdb,0x0f]
1577 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1578 ; CHECK-NEXT: retq ## encoding: [0xc3]
1579 %q = load i32, i32* %ptr_b
1580 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1581 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1582 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1583 ret <4 x i32> %res
1584 }
1585
1586 define <4 x i32> @test_mask_and_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
1587 ; CHECK-LABEL: test_mask_and_epi32_rmbkz_128:
1588 ; CHECK: ## BB#0:
1589 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1590 ; CHECK-NEXT: vpandd (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xdb,0x07]
1591 ; CHECK-NEXT: retq ## encoding: [0xc3]
1592 %q = load i32, i32* %ptr_b
1593 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1594 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1595 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1596 ret <4 x i32> %res
1597 }
1598
1599 declare <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
1600
1601 define <8 x i32> @test_mask_and_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
1602 ; CHECK-LABEL: test_mask_and_epi32_rr_256:
1603 ; CHECK: ## BB#0:
1604 ; CHECK-NEXT: vpandd %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdb,0xc1]
1605 ; CHECK-NEXT: retq ## encoding: [0xc3]
1606 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
1607 ret <8 x i32> %res
1608 }
1609
1610 define <8 x i32> @test_mask_and_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
1611 ; CHECK-LABEL: test_mask_and_epi32_rrk_256:
1612 ; CHECK: ## BB#0:
1613 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1614 ; CHECK-NEXT: vpandd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdb,0xd1]
1615 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
1616 ; CHECK-NEXT: retq ## encoding: [0xc3]
1617 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
1618 ret <8 x i32> %res
1619 }
1620
1621 define <8 x i32> @test_mask_and_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
1622 ; CHECK-LABEL: test_mask_and_epi32_rrkz_256:
1623 ; CHECK: ## BB#0:
1624 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1625 ; CHECK-NEXT: vpandd %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdb,0xc1]
1626 ; CHECK-NEXT: retq ## encoding: [0xc3]
1627 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
1628 ret <8 x i32> %res
1629 }
1630
1631 define <8 x i32> @test_mask_and_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
1632 ; CHECK-LABEL: test_mask_and_epi32_rm_256:
1633 ; CHECK: ## BB#0:
1634 ; CHECK-NEXT: vpandd (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdb,0x07]
1635 ; CHECK-NEXT: retq ## encoding: [0xc3]
1636 %b = load <8 x i32>, <8 x i32>* %ptr_b
1637 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
1638 ret <8 x i32> %res
1639 }
1640
1641 define <8 x i32> @test_mask_and_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
1642 ; CHECK-LABEL: test_mask_and_epi32_rmk_256:
1643 ; CHECK: ## BB#0:
1644 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1645 ; CHECK-NEXT: vpandd (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdb,0x0f]
1646 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1647 ; CHECK-NEXT: retq ## encoding: [0xc3]
1648 %b = load <8 x i32>, <8 x i32>* %ptr_b
1649 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
1650 ret <8 x i32> %res
1651 }
1652
1653 define <8 x i32> @test_mask_and_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
1654 ; CHECK-LABEL: test_mask_and_epi32_rmkz_256:
1655 ; CHECK: ## BB#0:
1656 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1657 ; CHECK-NEXT: vpandd (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdb,0x07]
1658 ; CHECK-NEXT: retq ## encoding: [0xc3]
1659 %b = load <8 x i32>, <8 x i32>* %ptr_b
1660 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
1661 ret <8 x i32> %res
1662 }
1663
1664 define <8 x i32> @test_mask_and_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
1665 ; CHECK-LABEL: test_mask_and_epi32_rmb_256:
1666 ; CHECK: ## BB#0:
1667 ; CHECK-NEXT: vpandd (%rdi){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xdb,0x07]
1668 ; CHECK-NEXT: retq ## encoding: [0xc3]
1669 %q = load i32, i32* %ptr_b
1670 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
1671 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
1672 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
1673 ret <8 x i32> %res
1674 }
1675
1676 define <8 x i32> @test_mask_and_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
1677 ; CHECK-LABEL: test_mask_and_epi32_rmbk_256:
1678 ; CHECK: ## BB#0:
1679 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1680 ; CHECK-NEXT: vpandd (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xdb,0x0f]
1681 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1682 ; CHECK-NEXT: retq ## encoding: [0xc3]
1683 %q = load i32, i32* %ptr_b
1684 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
1685 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
1686 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
1687 ret <8 x i32> %res
1688 }
1689
1690 define <8 x i32> @test_mask_and_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
1691 ; CHECK-LABEL: test_mask_and_epi32_rmbkz_256:
1692 ; CHECK: ## BB#0:
1693 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1694 ; CHECK-NEXT: vpandd (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xdb,0x07]
1695 ; CHECK-NEXT: retq ## encoding: [0xc3]
1696 %q = load i32, i32* %ptr_b
1697 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
1698 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
1699 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
1700 ret <8 x i32> %res
1701 }
1702
1703 declare <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
1704
1705 define <4 x i32> @test_mask_or_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
1706 ; CHECK-LABEL: test_mask_or_epi32_rr_128:
1707 ; CHECK: ## BB#0:
1708 ; CHECK-NEXT: vpord %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xeb,0xc1]
1709 ; CHECK-NEXT: retq ## encoding: [0xc3]
1710 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1711 ret <4 x i32> %res
1712 }
1713
1714 define <4 x i32> @test_mask_or_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
1715 ; CHECK-LABEL: test_mask_or_epi32_rrk_128:
1716 ; CHECK: ## BB#0:
1717 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1718 ; CHECK-NEXT: vpord %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xeb,0xd1]
1719 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
1720 ; CHECK-NEXT: retq ## encoding: [0xc3]
1721 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1722 ret <4 x i32> %res
1723 }
1724
1725 define <4 x i32> @test_mask_or_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
1726 ; CHECK-LABEL: test_mask_or_epi32_rrkz_128:
1727 ; CHECK: ## BB#0:
1728 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1729 ; CHECK-NEXT: vpord %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xeb,0xc1]
1730 ; CHECK-NEXT: retq ## encoding: [0xc3]
1731 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1732 ret <4 x i32> %res
1733 }
1734
1735 define <4 x i32> @test_mask_or_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
1736 ; CHECK-LABEL: test_mask_or_epi32_rm_128:
1737 ; CHECK: ## BB#0:
1738 ; CHECK-NEXT: vpord (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xeb,0x07]
1739 ; CHECK-NEXT: retq ## encoding: [0xc3]
1740 %b = load <4 x i32>, <4 x i32>* %ptr_b
1741 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1742 ret <4 x i32> %res
1743 }
1744
1745 define <4 x i32> @test_mask_or_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
1746 ; CHECK-LABEL: test_mask_or_epi32_rmk_128:
1747 ; CHECK: ## BB#0:
1748 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1749 ; CHECK-NEXT: vpord (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xeb,0x0f]
1750 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1751 ; CHECK-NEXT: retq ## encoding: [0xc3]
1752 %b = load <4 x i32>, <4 x i32>* %ptr_b
1753 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1754 ret <4 x i32> %res
1755 }
1756
1757 define <4 x i32> @test_mask_or_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
1758 ; CHECK-LABEL: test_mask_or_epi32_rmkz_128:
1759 ; CHECK: ## BB#0:
1760 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1761 ; CHECK-NEXT: vpord (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xeb,0x07]
1762 ; CHECK-NEXT: retq ## encoding: [0xc3]
1763 %b = load <4 x i32>, <4 x i32>* %ptr_b
1764 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1765 ret <4 x i32> %res
1766 }
1767
1768 define <4 x i32> @test_mask_or_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
1769 ; CHECK-LABEL: test_mask_or_epi32_rmb_128:
1770 ; CHECK: ## BB#0:
1771 ; CHECK-NEXT: vpord (%rdi){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xeb,0x07]
1772 ; CHECK-NEXT: retq ## encoding: [0xc3]
1773 %q = load i32, i32* %ptr_b
1774 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1775 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1776 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1777 ret <4 x i32> %res
1778 }
1779
1780 define <4 x i32> @test_mask_or_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
1781 ; CHECK-LABEL: test_mask_or_epi32_rmbk_128:
1782 ; CHECK: ## BB#0:
1783 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1784 ; CHECK-NEXT: vpord (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xeb,0x0f]
1785 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1786 ; CHECK-NEXT: retq ## encoding: [0xc3]
1787 %q = load i32, i32* %ptr_b
1788 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1789 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1790 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1791 ret <4 x i32> %res
1792 }
1793
1794 define <4 x i32> @test_mask_or_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
1795 ; CHECK-LABEL: test_mask_or_epi32_rmbkz_128:
1796 ; CHECK: ## BB#0:
1797 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1798 ; CHECK-NEXT: vpord (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xeb,0x07]
1799 ; CHECK-NEXT: retq ## encoding: [0xc3]
1800 %q = load i32, i32* %ptr_b
1801 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1802 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1803 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1804 ret <4 x i32> %res
1805 }
1806
1807 declare <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
1808
1809 define <8 x i32> @test_mask_or_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
1810 ; CHECK-LABEL: test_mask_or_epi32_rr_256:
1811 ; CHECK: ## BB#0:
1812 ; CHECK-NEXT: vpord %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xeb,0xc1]
1813 ; CHECK-NEXT: retq ## encoding: [0xc3]
1814 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
1815 ret <8 x i32> %res
1816 }
1817
1818 define <8 x i32> @test_mask_or_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
1819 ; CHECK-LABEL: test_mask_or_epi32_rrk_256:
1820 ; CHECK: ## BB#0:
1821 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1822 ; CHECK-NEXT: vpord %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xeb,0xd1]
1823 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
1824 ; CHECK-NEXT: retq ## encoding: [0xc3]
1825 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
1826 ret <8 x i32> %res
1827 }
1828
1829 define <8 x i32> @test_mask_or_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
1830 ; CHECK-LABEL: test_mask_or_epi32_rrkz_256:
1831 ; CHECK: ## BB#0:
1832 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1833 ; CHECK-NEXT: vpord %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xeb,0xc1]
1834 ; CHECK-NEXT: retq ## encoding: [0xc3]
1835 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
1836 ret <8 x i32> %res
1837 }
1838
1839 define <8 x i32> @test_mask_or_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
1840 ; CHECK-LABEL: test_mask_or_epi32_rm_256:
1841 ; CHECK: ## BB#0:
1842 ; CHECK-NEXT: vpord (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xeb,0x07]
1843 ; CHECK-NEXT: retq ## encoding: [0xc3]
1844 %b = load <8 x i32>, <8 x i32>* %ptr_b
1845 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
1846 ret <8 x i32> %res
1847 }
1848
1849 define <8 x i32> @test_mask_or_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
1850 ; CHECK-LABEL: test_mask_or_epi32_rmk_256:
1851 ; CHECK: ## BB#0:
1852 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1853 ; CHECK-NEXT: vpord (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xeb,0x0f]
1854 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1855 ; CHECK-NEXT: retq ## encoding: [0xc3]
1856 %b = load <8 x i32>, <8 x i32>* %ptr_b
1857 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
1858 ret <8 x i32> %res
1859 }
1860
1861 define <8 x i32> @test_mask_or_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
1862 ; CHECK-LABEL: test_mask_or_epi32_rmkz_256:
1863 ; CHECK: ## BB#0:
1864 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1865 ; CHECK-NEXT: vpord (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xeb,0x07]
1866 ; CHECK-NEXT: retq ## encoding: [0xc3]
1867 %b = load <8 x i32>, <8 x i32>* %ptr_b
1868 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
1869 ret <8 x i32> %res
1870 }
1871
1872 define <8 x i32> @test_mask_or_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
1873 ; CHECK-LABEL: test_mask_or_epi32_rmb_256:
1874 ; CHECK: ## BB#0:
1875 ; CHECK-NEXT: vpord (%rdi){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xeb,0x07]
1876 ; CHECK-NEXT: retq ## encoding: [0xc3]
1877 %q = load i32, i32* %ptr_b
1878 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
1879 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
1880 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
1881 ret <8 x i32> %res
1882 }
1883
1884 define <8 x i32> @test_mask_or_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
1885 ; CHECK-LABEL: test_mask_or_epi32_rmbk_256:
1886 ; CHECK: ## BB#0:
1887 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1888 ; CHECK-NEXT: vpord (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xeb,0x0f]
1889 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1890 ; CHECK-NEXT: retq ## encoding: [0xc3]
1891 %q = load i32, i32* %ptr_b
1892 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
1893 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
1894 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
1895 ret <8 x i32> %res
1896 }
1897
1898 define <8 x i32> @test_mask_or_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
1899 ; CHECK-LABEL: test_mask_or_epi32_rmbkz_256:
1900 ; CHECK: ## BB#0:
1901 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1902 ; CHECK-NEXT: vpord (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xeb,0x07]
1903 ; CHECK-NEXT: retq ## encoding: [0xc3]
1904 %q = load i32, i32* %ptr_b
1905 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
1906 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
1907 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
1908 ret <8 x i32> %res
1909 }
1910
1911 declare <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
1912
1913 define <4 x i32> @test_mask_xor_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
1914 ; CHECK-LABEL: test_mask_xor_epi32_rr_128:
1915 ; CHECK: ## BB#0:
1916 ; CHECK-NEXT: vpxord %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xef,0xc1]
1917 ; CHECK-NEXT: retq ## encoding: [0xc3]
1918 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1919 ret <4 x i32> %res
1920 }
1921
1922 define <4 x i32> @test_mask_xor_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
1923 ; CHECK-LABEL: test_mask_xor_epi32_rrk_128:
1924 ; CHECK: ## BB#0:
1925 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1926 ; CHECK-NEXT: vpxord %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xef,0xd1]
1927 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
1928 ; CHECK-NEXT: retq ## encoding: [0xc3]
1929 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1930 ret <4 x i32> %res
1931 }
1932
1933 define <4 x i32> @test_mask_xor_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
1934 ; CHECK-LABEL: test_mask_xor_epi32_rrkz_128:
1935 ; CHECK: ## BB#0:
1936 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1937 ; CHECK-NEXT: vpxord %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xef,0xc1]
1938 ; CHECK-NEXT: retq ## encoding: [0xc3]
1939 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1940 ret <4 x i32> %res
1941 }
1942
1943 define <4 x i32> @test_mask_xor_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
1944 ; CHECK-LABEL: test_mask_xor_epi32_rm_128:
1945 ; CHECK: ## BB#0:
1946 ; CHECK-NEXT: vpxord (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xef,0x07]
1947 ; CHECK-NEXT: retq ## encoding: [0xc3]
1948 %b = load <4 x i32>, <4 x i32>* %ptr_b
1949 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1950 ret <4 x i32> %res
1951 }
1952
1953 define <4 x i32> @test_mask_xor_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
1954 ; CHECK-LABEL: test_mask_xor_epi32_rmk_128:
1955 ; CHECK: ## BB#0:
1956 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1957 ; CHECK-NEXT: vpxord (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xef,0x0f]
1958 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1959 ; CHECK-NEXT: retq ## encoding: [0xc3]
1960 %b = load <4 x i32>, <4 x i32>* %ptr_b
1961 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1962 ret <4 x i32> %res
1963 }
1964
1965 define <4 x i32> @test_mask_xor_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
1966 ; CHECK-LABEL: test_mask_xor_epi32_rmkz_128:
1967 ; CHECK: ## BB#0:
1968 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1969 ; CHECK-NEXT: vpxord (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xef,0x07]
1970 ; CHECK-NEXT: retq ## encoding: [0xc3]
1971 %b = load <4 x i32>, <4 x i32>* %ptr_b
1972 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1973 ret <4 x i32> %res
1974 }
1975
1976 define <4 x i32> @test_mask_xor_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
1977 ; CHECK-LABEL: test_mask_xor_epi32_rmb_128:
1978 ; CHECK: ## BB#0:
1979 ; CHECK-NEXT: vpxord (%rdi){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xef,0x07]
1980 ; CHECK-NEXT: retq ## encoding: [0xc3]
1981 %q = load i32, i32* %ptr_b
1982 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1983 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1984 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1985 ret <4 x i32> %res
1986 }
1987
1988 define <4 x i32> @test_mask_xor_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
1989 ; CHECK-LABEL: test_mask_xor_epi32_rmbk_128:
1990 ; CHECK: ## BB#0:
1991 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1992 ; CHECK-NEXT: vpxord (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xef,0x0f]
1993 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1994 ; CHECK-NEXT: retq ## encoding: [0xc3]
1995 %q = load i32, i32* %ptr_b
1996 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1997 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1998 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1999 ret <4 x i32> %res
2000 }
2001
2002 define <4 x i32> @test_mask_xor_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
2003 ; CHECK-LABEL: test_mask_xor_epi32_rmbkz_128:
2004 ; CHECK: ## BB#0:
2005 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2006 ; CHECK-NEXT: vpxord (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xef,0x07]
2007 ; CHECK-NEXT: retq ## encoding: [0xc3]
2008 %q = load i32, i32* %ptr_b
2009 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2010 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2011 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2012 ret <4 x i32> %res
2013 }
2014
2015 declare <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
2016
2017 define <8 x i32> @test_mask_xor_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
2018 ; CHECK-LABEL: test_mask_xor_epi32_rr_256:
2019 ; CHECK: ## BB#0:
2020 ; CHECK-NEXT: vpxord %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xef,0xc1]
2021 ; CHECK-NEXT: retq ## encoding: [0xc3]
2022 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2023 ret <8 x i32> %res
2024 }
2025
2026 define <8 x i32> @test_mask_xor_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
2027 ; CHECK-LABEL: test_mask_xor_epi32_rrk_256:
2028 ; CHECK: ## BB#0:
2029 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2030 ; CHECK-NEXT: vpxord %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xef,0xd1]
2031 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2032 ; CHECK-NEXT: retq ## encoding: [0xc3]
2033 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2034 ret <8 x i32> %res
2035 }
2036
2037 define <8 x i32> @test_mask_xor_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
2038 ; CHECK-LABEL: test_mask_xor_epi32_rrkz_256:
2039 ; CHECK: ## BB#0:
2040 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2041 ; CHECK-NEXT: vpxord %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xef,0xc1]
2042 ; CHECK-NEXT: retq ## encoding: [0xc3]
2043 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2044 ret <8 x i32> %res
2045 }
2046
2047 define <8 x i32> @test_mask_xor_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
2048 ; CHECK-LABEL: test_mask_xor_epi32_rm_256:
2049 ; CHECK: ## BB#0:
2050 ; CHECK-NEXT: vpxord (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xef,0x07]
2051 ; CHECK-NEXT: retq ## encoding: [0xc3]
2052 %b = load <8 x i32>, <8 x i32>* %ptr_b
2053 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2054 ret <8 x i32> %res
2055 }
2056
2057 define <8 x i32> @test_mask_xor_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2058 ; CHECK-LABEL: test_mask_xor_epi32_rmk_256:
2059 ; CHECK: ## BB#0:
2060 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2061 ; CHECK-NEXT: vpxord (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xef,0x0f]
2062 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2063 ; CHECK-NEXT: retq ## encoding: [0xc3]
2064 %b = load <8 x i32>, <8 x i32>* %ptr_b
2065 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2066 ret <8 x i32> %res
2067 }
2068
2069 define <8 x i32> @test_mask_xor_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
2070 ; CHECK-LABEL: test_mask_xor_epi32_rmkz_256:
2071 ; CHECK: ## BB#0:
2072 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2073 ; CHECK-NEXT: vpxord (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xef,0x07]
2074 ; CHECK-NEXT: retq ## encoding: [0xc3]
2075 %b = load <8 x i32>, <8 x i32>* %ptr_b
2076 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2077 ret <8 x i32> %res
2078 }
2079
2080 define <8 x i32> @test_mask_xor_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
2081 ; CHECK-LABEL: test_mask_xor_epi32_rmb_256:
2082 ; CHECK: ## BB#0:
2083 ; CHECK-NEXT: vpxord (%rdi){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xef,0x07]
2084 ; CHECK-NEXT: retq ## encoding: [0xc3]
2085 %q = load i32, i32* %ptr_b
2086 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2087 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2088 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2089 ret <8 x i32> %res
2090 }
2091
2092 define <8 x i32> @test_mask_xor_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2093 ; CHECK-LABEL: test_mask_xor_epi32_rmbk_256:
2094 ; CHECK: ## BB#0:
2095 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2096 ; CHECK-NEXT: vpxord (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xef,0x0f]
2097 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2098 ; CHECK-NEXT: retq ## encoding: [0xc3]
2099 %q = load i32, i32* %ptr_b
2100 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2101 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2102 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2103 ret <8 x i32> %res
2104 }
2105
2106 define <8 x i32> @test_mask_xor_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
2107 ; CHECK-LABEL: test_mask_xor_epi32_rmbkz_256:
2108 ; CHECK: ## BB#0:
2109 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2110 ; CHECK-NEXT: vpxord (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xef,0x07]
2111 ; CHECK-NEXT: retq ## encoding: [0xc3]
2112 %q = load i32, i32* %ptr_b
2113 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2114 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2115 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2116 ret <8 x i32> %res
2117 }
2118
2119 declare <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
2120
2121 define <4 x i32> @test_mask_andnot_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
2122 ; CHECK-LABEL: test_mask_andnot_epi32_rr_128:
2123 ; CHECK: ## BB#0:
2124 ; CHECK-NEXT: vpandnd %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0xc1]
2125 ; CHECK-NEXT: retq ## encoding: [0xc3]
2126 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2127 ret <4 x i32> %res
2128 }
2129
2130 define <4 x i32> @test_mask_andnot_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
2131 ; CHECK-LABEL: test_mask_andnot_epi32_rrk_128:
2132 ; CHECK: ## BB#0:
2133 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2134 ; CHECK-NEXT: vpandnd %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdf,0xd1]
2135 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2136 ; CHECK-NEXT: retq ## encoding: [0xc3]
2137 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2138 ret <4 x i32> %res
2139 }
2140
2141 define <4 x i32> @test_mask_andnot_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
2142 ; CHECK-LABEL: test_mask_andnot_epi32_rrkz_128:
2143 ; CHECK: ## BB#0:
2144 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2145 ; CHECK-NEXT: vpandnd %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdf,0xc1]
2146 ; CHECK-NEXT: retq ## encoding: [0xc3]
2147 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2148 ret <4 x i32> %res
2149 }
2150
2151 define <4 x i32> @test_mask_andnot_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
2152 ; CHECK-LABEL: test_mask_andnot_epi32_rm_128:
2153 ; CHECK: ## BB#0:
2154 ; CHECK-NEXT: vpandnd (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0x07]
2155 ; CHECK-NEXT: retq ## encoding: [0xc3]
2156 %b = load <4 x i32>, <4 x i32>* %ptr_b
2157 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2158 ret <4 x i32> %res
2159 }
2160
2161 define <4 x i32> @test_mask_andnot_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
2162 ; CHECK-LABEL: test_mask_andnot_epi32_rmk_128:
2163 ; CHECK: ## BB#0:
2164 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2165 ; CHECK-NEXT: vpandnd (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdf,0x0f]
2166 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2167 ; CHECK-NEXT: retq ## encoding: [0xc3]
2168 %b = load <4 x i32>, <4 x i32>* %ptr_b
2169 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2170 ret <4 x i32> %res
2171 }
2172
2173 define <4 x i32> @test_mask_andnot_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
2174 ; CHECK-LABEL: test_mask_andnot_epi32_rmkz_128:
2175 ; CHECK: ## BB#0:
2176 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2177 ; CHECK-NEXT: vpandnd (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdf,0x07]
2178 ; CHECK-NEXT: retq ## encoding: [0xc3]
2179 %b = load <4 x i32>, <4 x i32>* %ptr_b
2180 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2181 ret <4 x i32> %res
2182 }
2183
2184 define <4 x i32> @test_mask_andnot_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
2185 ; CHECK-LABEL: test_mask_andnot_epi32_rmb_128:
2186 ; CHECK: ## BB#0:
2187 ; CHECK-NEXT: vpandnd (%rdi){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xdf,0x07]
2188 ; CHECK-NEXT: retq ## encoding: [0xc3]
2189 %q = load i32, i32* %ptr_b
2190 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2191 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2192 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2193 ret <4 x i32> %res
2194 }
2195
2196 define <4 x i32> @test_mask_andnot_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
2197 ; CHECK-LABEL: test_mask_andnot_epi32_rmbk_128:
2198 ; CHECK: ## BB#0:
2199 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2200 ; CHECK-NEXT: vpandnd (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xdf,0x0f]
2201 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2202 ; CHECK-NEXT: retq ## encoding: [0xc3]
2203 %q = load i32, i32* %ptr_b
2204 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2205 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2206 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2207 ret <4 x i32> %res
2208 }
2209
2210 define <4 x i32> @test_mask_andnot_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
2211 ; CHECK-LABEL: test_mask_andnot_epi32_rmbkz_128:
2212 ; CHECK: ## BB#0:
2213 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2214 ; CHECK-NEXT: vpandnd (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xdf,0x07]
2215 ; CHECK-NEXT: retq ## encoding: [0xc3]
2216 %q = load i32, i32* %ptr_b
2217 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2218 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2219 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2220 ret <4 x i32> %res
2221 }
2222
2223 declare <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
2224
2225 define <8 x i32> @test_mask_andnot_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
2226 ; CHECK-LABEL: test_mask_andnot_epi32_rr_256:
2227 ; CHECK: ## BB#0:
2228 ; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0xc1]
2229 ; CHECK-NEXT: retq ## encoding: [0xc3]
2230 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2231 ret <8 x i32> %res
2232 }
2233
2234 define <8 x i32> @test_mask_andnot_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
2235 ; CHECK-LABEL: test_mask_andnot_epi32_rrk_256:
2236 ; CHECK: ## BB#0:
2237 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2238 ; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdf,0xd1]
2239 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2240 ; CHECK-NEXT: retq ## encoding: [0xc3]
2241 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2242 ret <8 x i32> %res
2243 }
2244
2245 define <8 x i32> @test_mask_andnot_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
2246 ; CHECK-LABEL: test_mask_andnot_epi32_rrkz_256:
2247 ; CHECK: ## BB#0:
2248 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2249 ; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdf,0xc1]
2250 ; CHECK-NEXT: retq ## encoding: [0xc3]
2251 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2252 ret <8 x i32> %res
2253 }
2254
2255 define <8 x i32> @test_mask_andnot_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
2256 ; CHECK-LABEL: test_mask_andnot_epi32_rm_256:
2257 ; CHECK: ## BB#0:
2258 ; CHECK-NEXT: vpandnd (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0x07]
2259 ; CHECK-NEXT: retq ## encoding: [0xc3]
2260 %b = load <8 x i32>, <8 x i32>* %ptr_b
2261 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2262 ret <8 x i32> %res
2263 }
2264
2265 define <8 x i32> @test_mask_andnot_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2266 ; CHECK-LABEL: test_mask_andnot_epi32_rmk_256:
2267 ; CHECK: ## BB#0:
2268 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2269 ; CHECK-NEXT: vpandnd (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdf,0x0f]
2270 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2271 ; CHECK-NEXT: retq ## encoding: [0xc3]
2272 %b = load <8 x i32>, <8 x i32>* %ptr_b
2273 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2274 ret <8 x i32> %res
2275 }
2276
2277 define <8 x i32> @test_mask_andnot_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
2278 ; CHECK-LABEL: test_mask_andnot_epi32_rmkz_256:
2279 ; CHECK: ## BB#0:
2280 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2281 ; CHECK-NEXT: vpandnd (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdf,0x07]
2282 ; CHECK-NEXT: retq ## encoding: [0xc3]
2283 %b = load <8 x i32>, <8 x i32>* %ptr_b
2284 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2285 ret <8 x i32> %res
2286 }
2287
2288 define <8 x i32> @test_mask_andnot_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
2289 ; CHECK-LABEL: test_mask_andnot_epi32_rmb_256:
2290 ; CHECK: ## BB#0:
2291 ; CHECK-NEXT: vpandnd (%rdi){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xdf,0x07]
2292 ; CHECK-NEXT: retq ## encoding: [0xc3]
2293 %q = load i32, i32* %ptr_b
2294 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2295 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2296 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2297 ret <8 x i32> %res
2298 }
2299
2300 define <8 x i32> @test_mask_andnot_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2301 ; CHECK-LABEL: test_mask_andnot_epi32_rmbk_256:
2302 ; CHECK: ## BB#0:
2303 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2304 ; CHECK-NEXT: vpandnd (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xdf,0x0f]
2305 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2306 ; CHECK-NEXT: retq ## encoding: [0xc3]
2307 %q = load i32, i32* %ptr_b
2308 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2309 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2310 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2311 ret <8 x i32> %res
2312 }
2313
2314 define <8 x i32> @test_mask_andnot_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
2315 ; CHECK-LABEL: test_mask_andnot_epi32_rmbkz_256:
2316 ; CHECK: ## BB#0:
2317 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2318 ; CHECK-NEXT: vpandnd (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xdf,0x07]
2319 ; CHECK-NEXT: retq ## encoding: [0xc3]
2320 %q = load i32, i32* %ptr_b
2321 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2322 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2323 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2324 ret <8 x i32> %res
2325 }
2326
2327 declare <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
2328
2329 define <2 x i64> @test_mask_andnot_epi64_rr_128(<2 x i64> %a, <2 x i64> %b) {
2330 ; CHECK-LABEL: test_mask_andnot_epi64_rr_128:
2331 ; CHECK: ## BB#0:
2332 ; CHECK-NEXT: vpandnq %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0xc1]
2333 ; CHECK-NEXT: retq ## encoding: [0xc3]
2334 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
2335 ret <2 x i64> %res
2336 }
2337
2338 define <2 x i64> @test_mask_andnot_epi64_rrk_128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask) {
2339 ; CHECK-LABEL: test_mask_andnot_epi64_rrk_128:
2340 ; CHECK: ## BB#0:
2341 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2342 ; CHECK-NEXT: vpandnq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xdf,0xd1]
2343 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2344 ; CHECK-NEXT: retq ## encoding: [0xc3]
2345 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
2346 ret <2 x i64> %res
2347 }
2348
2349 define <2 x i64> @test_mask_andnot_epi64_rrkz_128(<2 x i64> %a, <2 x i64> %b, i8 %mask) {
2350 ; CHECK-LABEL: test_mask_andnot_epi64_rrkz_128:
2351 ; CHECK: ## BB#0:
2352 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2353 ; CHECK-NEXT: vpandnq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xdf,0xc1]
2354 ; CHECK-NEXT: retq ## encoding: [0xc3]
2355 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
2356 ret <2 x i64> %res
2357 }
2358
2359 define <2 x i64> @test_mask_andnot_epi64_rm_128(<2 x i64> %a, <2 x i64>* %ptr_b) {
2360 ; CHECK-LABEL: test_mask_andnot_epi64_rm_128:
2361 ; CHECK: ## BB#0:
2362 ; CHECK-NEXT: vpandnq (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0x07]
2363 ; CHECK-NEXT: retq ## encoding: [0xc3]
2364 %b = load <2 x i64>, <2 x i64>* %ptr_b
2365 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
2366 ret <2 x i64> %res
2367 }
2368
2369 define <2 x i64> @test_mask_andnot_epi64_rmk_128(<2 x i64> %a, <2 x i64>* %ptr_b, <2 x i64> %passThru, i8 %mask) {
2370 ; CHECK-LABEL: test_mask_andnot_epi64_rmk_128:
2371 ; CHECK: ## BB#0:
2372 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2373 ; CHECK-NEXT: vpandnq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xdf,0x0f]
2374 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2375 ; CHECK-NEXT: retq ## encoding: [0xc3]
2376 %b = load <2 x i64>, <2 x i64>* %ptr_b
2377 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
2378 ret <2 x i64> %res
2379 }
2380
2381 define <2 x i64> @test_mask_andnot_epi64_rmkz_128(<2 x i64> %a, <2 x i64>* %ptr_b, i8 %mask) {
2382 ; CHECK-LABEL: test_mask_andnot_epi64_rmkz_128:
2383 ; CHECK: ## BB#0:
2384 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2385 ; CHECK-NEXT: vpandnq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xdf,0x07]
2386 ; CHECK-NEXT: retq ## encoding: [0xc3]
2387 %b = load <2 x i64>, <2 x i64>* %ptr_b
2388 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
2389 ret <2 x i64> %res
2390 }
2391
2392 define <2 x i64> @test_mask_andnot_epi64_rmb_128(<2 x i64> %a, i64* %ptr_b) {
2393 ; CHECK-LABEL: test_mask_andnot_epi64_rmb_128:
2394 ; CHECK: ## BB#0:
2395 ; CHECK-NEXT: vpandnq (%rdi){1to2}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x18,0xdf,0x07]
2396 ; CHECK-NEXT: retq ## encoding: [0xc3]
2397 %q = load i64, i64* %ptr_b
2398 %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
2399 %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
2400 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
2401 ret <2 x i64> %res
2402 }
2403
2404 define <2 x i64> @test_mask_andnot_epi64_rmbk_128(<2 x i64> %a, i64* %ptr_b, <2 x i64> %passThru, i8 %mask) {
2405 ; CHECK-LABEL: test_mask_andnot_epi64_rmbk_128:
2406 ; CHECK: ## BB#0:
2407 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2408 ; CHECK-NEXT: vpandnq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x19,0xdf,0x0f]
2409 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2410 ; CHECK-NEXT: retq ## encoding: [0xc3]
2411 %q = load i64, i64* %ptr_b
2412 %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
2413 %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
2414 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
2415 ret <2 x i64> %res
2416 }
2417
2418 define <2 x i64> @test_mask_andnot_epi64_rmbkz_128(<2 x i64> %a, i64* %ptr_b, i8 %mask) {
2419 ; CHECK-LABEL: test_mask_andnot_epi64_rmbkz_128:
2420 ; CHECK: ## BB#0:
2421 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2422 ; CHECK-NEXT: vpandnq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x99,0xdf,0x07]
2423 ; CHECK-NEXT: retq ## encoding: [0xc3]
2424 %q = load i64, i64* %ptr_b
2425 %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
2426 %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
2427 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
2428 ret <2 x i64> %res
2429 }
2430
2431 declare <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
2432
2433 define <4 x i64> @test_mask_andnot_epi64_rr_256(<4 x i64> %a, <4 x i64> %b) {
2434 ; CHECK-LABEL: test_mask_andnot_epi64_rr_256:
2435 ; CHECK: ## BB#0:
2436 ; CHECK-NEXT: vpandnq %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0xc1]
2437 ; CHECK-NEXT: retq ## encoding: [0xc3]
2438 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
2439 ret <4 x i64> %res
2440 }
2441
2442 define <4 x i64> @test_mask_andnot_epi64_rrk_256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask) {
2443 ; CHECK-LABEL: test_mask_andnot_epi64_rrk_256:
2444 ; CHECK: ## BB#0:
2445 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2446 ; CHECK-NEXT: vpandnq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xdf,0xd1]
2447 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2448 ; CHECK-NEXT: retq ## encoding: [0xc3]
2449 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
2450 ret <4 x i64> %res
2451 }
2452
2453 define <4 x i64> @test_mask_andnot_epi64_rrkz_256(<4 x i64> %a, <4 x i64> %b, i8 %mask) {
2454 ; CHECK-LABEL: test_mask_andnot_epi64_rrkz_256:
2455 ; CHECK: ## BB#0:
2456 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2457 ; CHECK-NEXT: vpandnq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xdf,0xc1]
2458 ; CHECK-NEXT: retq ## encoding: [0xc3]
2459 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
2460 ret <4 x i64> %res
2461 }
2462
2463 define <4 x i64> @test_mask_andnot_epi64_rm_256(<4 x i64> %a, <4 x i64>* %ptr_b) {
2464 ; CHECK-LABEL: test_mask_andnot_epi64_rm_256:
2465 ; CHECK: ## BB#0:
2466 ; CHECK-NEXT: vpandnq (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0x07]
2467 ; CHECK-NEXT: retq ## encoding: [0xc3]
2468 %b = load <4 x i64>, <4 x i64>* %ptr_b
2469 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
2470 ret <4 x i64> %res
2471 }
2472
2473 define <4 x i64> @test_mask_andnot_epi64_rmk_256(<4 x i64> %a, <4 x i64>* %ptr_b, <4 x i64> %passThru, i8 %mask) {
2474 ; CHECK-LABEL: test_mask_andnot_epi64_rmk_256:
2475 ; CHECK: ## BB#0:
2476 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2477 ; CHECK-NEXT: vpandnq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xdf,0x0f]
2478 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2479 ; CHECK-NEXT: retq ## encoding: [0xc3]
2480 %b = load <4 x i64>, <4 x i64>* %ptr_b
2481 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
2482 ret <4 x i64> %res
2483 }
2484
2485 define <4 x i64> @test_mask_andnot_epi64_rmkz_256(<4 x i64> %a, <4 x i64>* %ptr_b, i8 %mask) {
2486 ; CHECK-LABEL: test_mask_andnot_epi64_rmkz_256:
2487 ; CHECK: ## BB#0:
2488 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2489 ; CHECK-NEXT: vpandnq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xdf,0x07]
2490 ; CHECK-NEXT: retq ## encoding: [0xc3]
2491 %b = load <4 x i64>, <4 x i64>* %ptr_b
2492 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
2493 ret <4 x i64> %res
2494 }
2495
2496 define <4 x i64> @test_mask_andnot_epi64_rmb_256(<4 x i64> %a, i64* %ptr_b) {
2497 ; CHECK-LABEL: test_mask_andnot_epi64_rmb_256:
2498 ; CHECK: ## BB#0:
2499 ; CHECK-NEXT: vpandnq (%rdi){1to4}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x38,0xdf,0x07]
2500 ; CHECK-NEXT: retq ## encoding: [0xc3]
2501 %q = load i64, i64* %ptr_b
2502 %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
2503 %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
2504 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
2505 ret <4 x i64> %res
2506 }
2507
2508 define <4 x i64> @test_mask_andnot_epi64_rmbk_256(<4 x i64> %a, i64* %ptr_b, <4 x i64> %passThru, i8 %mask) {
2509 ; CHECK-LABEL: test_mask_andnot_epi64_rmbk_256:
2510 ; CHECK: ## BB#0:
2511 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2512 ; CHECK-NEXT: vpandnq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x39,0xdf,0x0f]
2513 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2514 ; CHECK-NEXT: retq ## encoding: [0xc3]
2515 %q = load i64, i64* %ptr_b
2516 %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
2517 %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
2518 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
2519 ret <4 x i64> %res
2520 }
2521
2522 define <4 x i64> @test_mask_andnot_epi64_rmbkz_256(<4 x i64> %a, i64* %ptr_b, i8 %mask) {
2523 ; CHECK-LABEL: test_mask_andnot_epi64_rmbkz_256:
2524 ; CHECK: ## BB#0:
2525 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2526 ; CHECK-NEXT: vpandnq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xb9,0xdf,0x07]
2527 ; CHECK-NEXT: retq ## encoding: [0xc3]
2528 %q = load i64, i64* %ptr_b
2529 %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
2530 %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
2531 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
2532 ret <4 x i64> %res
2533 }
2534
2535 declare <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
18541854
18551855 declare <8 x i32> @llvm.x86.avx512.mask.padd.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
18561856
1857 define <4 x i32> @test_mask_and_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
1858 ; CHECK-LABEL: test_mask_and_epi32_rr_128:
1859 ; CHECK: ## BB#0:
1860 ; CHECK-NEXT: vpandd %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdb,0xc1]
1861 ; CHECK-NEXT: retq ## encoding: [0xc3]
1862 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1863 ret <4 x i32> %res
1864 }
1865
1866 define <4 x i32> @test_mask_and_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
1867 ; CHECK-LABEL: test_mask_and_epi32_rrk_128:
1868 ; CHECK: ## BB#0:
1869 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1870 ; CHECK-NEXT: vpandd %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdb,0xd1]
1871 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
1872 ; CHECK-NEXT: retq ## encoding: [0xc3]
1873 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1874 ret <4 x i32> %res
1875 }
1876
1877 define <4 x i32> @test_mask_and_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
1878 ; CHECK-LABEL: test_mask_and_epi32_rrkz_128:
1879 ; CHECK: ## BB#0:
1880 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1881 ; CHECK-NEXT: vpandd %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdb,0xc1]
1882 ; CHECK-NEXT: retq ## encoding: [0xc3]
1883 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1884 ret <4 x i32> %res
1885 }
1886
1887 define <4 x i32> @test_mask_and_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
1888 ; CHECK-LABEL: test_mask_and_epi32_rm_128:
1889 ; CHECK: ## BB#0:
1890 ; CHECK-NEXT: vpandd (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdb,0x07]
1891 ; CHECK-NEXT: retq ## encoding: [0xc3]
1892 %b = load <4 x i32>, <4 x i32>* %ptr_b
1893 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1894 ret <4 x i32> %res
1895 }
1896
1897 define <4 x i32> @test_mask_and_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
1898 ; CHECK-LABEL: test_mask_and_epi32_rmk_128:
1899 ; CHECK: ## BB#0:
1900 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1901 ; CHECK-NEXT: vpandd (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdb,0x0f]
1902 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1903 ; CHECK-NEXT: retq ## encoding: [0xc3]
1904 %b = load <4 x i32>, <4 x i32>* %ptr_b
1905 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1906 ret <4 x i32> %res
1907 }
1908
1909 define <4 x i32> @test_mask_and_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
1910 ; CHECK-LABEL: test_mask_and_epi32_rmkz_128:
1911 ; CHECK: ## BB#0:
1912 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1913 ; CHECK-NEXT: vpandd (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdb,0x07]
1914 ; CHECK-NEXT: retq ## encoding: [0xc3]
1915 %b = load <4 x i32>, <4 x i32>* %ptr_b
1916 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1917 ret <4 x i32> %res
1918 }
1919
1920 define <4 x i32> @test_mask_and_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
1921 ; CHECK-LABEL: test_mask_and_epi32_rmb_128:
1922 ; CHECK: ## BB#0:
1923 ; CHECK-NEXT: vpandd (%rdi){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xdb,0x07]
1924 ; CHECK-NEXT: retq ## encoding: [0xc3]
1925 %q = load i32, i32* %ptr_b
1926 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1927 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1928 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
1929 ret <4 x i32> %res
1930 }
1931
1932 define <4 x i32> @test_mask_and_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
1933 ; CHECK-LABEL: test_mask_and_epi32_rmbk_128:
1934 ; CHECK: ## BB#0:
1935 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1936 ; CHECK-NEXT: vpandd (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xdb,0x0f]
1937 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
1938 ; CHECK-NEXT: retq ## encoding: [0xc3]
1939 %q = load i32, i32* %ptr_b
1940 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1941 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1942 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
1943 ret <4 x i32> %res
1944 }
1945
1946 define <4 x i32> @test_mask_and_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
1947 ; CHECK-LABEL: test_mask_and_epi32_rmbkz_128:
1948 ; CHECK: ## BB#0:
1949 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
1950 ; CHECK-NEXT: vpandd (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xdb,0x07]
1951 ; CHECK-NEXT: retq ## encoding: [0xc3]
1952 %q = load i32, i32* %ptr_b
1953 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
1954 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
1955 %res = call <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
1956 ret <4 x i32> %res
1957 }
1958
1959 declare <4 x i32> @llvm.x86.avx512.mask.pand.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
1960
1961 define <8 x i32> @test_mask_and_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
1962 ; CHECK-LABEL: test_mask_and_epi32_rr_256:
1963 ; CHECK: ## BB#0:
1964 ; CHECK-NEXT: vpandd %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdb,0xc1]
1965 ; CHECK-NEXT: retq ## encoding: [0xc3]
1966 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
1967 ret <8 x i32> %res
1968 }
1969
1970 define <8 x i32> @test_mask_and_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
1971 ; CHECK-LABEL: test_mask_and_epi32_rrk_256:
1972 ; CHECK: ## BB#0:
1973 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1974 ; CHECK-NEXT: vpandd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdb,0xd1]
1975 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
1976 ; CHECK-NEXT: retq ## encoding: [0xc3]
1977 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
1978 ret <8 x i32> %res
1979 }
1980
1981 define <8 x i32> @test_mask_and_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
1982 ; CHECK-LABEL: test_mask_and_epi32_rrkz_256:
1983 ; CHECK: ## BB#0:
1984 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
1985 ; CHECK-NEXT: vpandd %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdb,0xc1]
1986 ; CHECK-NEXT: retq ## encoding: [0xc3]
1987 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
1988 ret <8 x i32> %res
1989 }
1990
1991 define <8 x i32> @test_mask_and_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
1992 ; CHECK-LABEL: test_mask_and_epi32_rm_256:
1993 ; CHECK: ## BB#0:
1994 ; CHECK-NEXT: vpandd (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdb,0x07]
1995 ; CHECK-NEXT: retq ## encoding: [0xc3]
1996 %b = load <8 x i32>, <8 x i32>* %ptr_b
1997 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
1998 ret <8 x i32> %res
1999 }
2000
2001 define <8 x i32> @test_mask_and_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2002 ; CHECK-LABEL: test_mask_and_epi32_rmk_256:
2003 ; CHECK: ## BB#0:
2004 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2005 ; CHECK-NEXT: vpandd (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdb,0x0f]
2006 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2007 ; CHECK-NEXT: retq ## encoding: [0xc3]
2008 %b = load <8 x i32>, <8 x i32>* %ptr_b
2009 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2010 ret <8 x i32> %res
2011 }
2012
2013 define <8 x i32> @test_mask_and_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
2014 ; CHECK-LABEL: test_mask_and_epi32_rmkz_256:
2015 ; CHECK: ## BB#0:
2016 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2017 ; CHECK-NEXT: vpandd (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdb,0x07]
2018 ; CHECK-NEXT: retq ## encoding: [0xc3]
2019 %b = load <8 x i32>, <8 x i32>* %ptr_b
2020 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2021 ret <8 x i32> %res
2022 }
2023
2024 define <8 x i32> @test_mask_and_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
2025 ; CHECK-LABEL: test_mask_and_epi32_rmb_256:
2026 ; CHECK: ## BB#0:
2027 ; CHECK-NEXT: vpandd (%rdi){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xdb,0x07]
2028 ; CHECK-NEXT: retq ## encoding: [0xc3]
2029 %q = load i32, i32* %ptr_b
2030 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2031 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2032 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2033 ret <8 x i32> %res
2034 }
2035
2036 define <8 x i32> @test_mask_and_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2037 ; CHECK-LABEL: test_mask_and_epi32_rmbk_256:
2038 ; CHECK: ## BB#0:
2039 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2040 ; CHECK-NEXT: vpandd (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xdb,0x0f]
2041 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2042 ; CHECK-NEXT: retq ## encoding: [0xc3]
2043 %q = load i32, i32* %ptr_b
2044 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2045 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2046 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2047 ret <8 x i32> %res
2048 }
2049
2050 define <8 x i32> @test_mask_and_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
2051 ; CHECK-LABEL: test_mask_and_epi32_rmbkz_256:
2052 ; CHECK: ## BB#0:
2053 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2054 ; CHECK-NEXT: vpandd (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xdb,0x07]
2055 ; CHECK-NEXT: retq ## encoding: [0xc3]
2056 %q = load i32, i32* %ptr_b
2057 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2058 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2059 %res = call <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2060 ret <8 x i32> %res
2061 }
2062
2063 declare <8 x i32> @llvm.x86.avx512.mask.pand.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
2064
2065 define <4 x i32> @test_mask_or_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
2066 ; CHECK-LABEL: test_mask_or_epi32_rr_128:
2067 ; CHECK: ## BB#0:
2068 ; CHECK-NEXT: vpord %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xeb,0xc1]
2069 ; CHECK-NEXT: retq ## encoding: [0xc3]
2070 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2071 ret <4 x i32> %res
2072 }
2073
2074 define <4 x i32> @test_mask_or_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
2075 ; CHECK-LABEL: test_mask_or_epi32_rrk_128:
2076 ; CHECK: ## BB#0:
2077 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2078 ; CHECK-NEXT: vpord %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xeb,0xd1]
2079 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2080 ; CHECK-NEXT: retq ## encoding: [0xc3]
2081 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2082 ret <4 x i32> %res
2083 }
2084
2085 define <4 x i32> @test_mask_or_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
2086 ; CHECK-LABEL: test_mask_or_epi32_rrkz_128:
2087 ; CHECK: ## BB#0:
2088 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2089 ; CHECK-NEXT: vpord %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xeb,0xc1]
2090 ; CHECK-NEXT: retq ## encoding: [0xc3]
2091 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2092 ret <4 x i32> %res
2093 }
2094
2095 define <4 x i32> @test_mask_or_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
2096 ; CHECK-LABEL: test_mask_or_epi32_rm_128:
2097 ; CHECK: ## BB#0:
2098 ; CHECK-NEXT: vpord (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xeb,0x07]
2099 ; CHECK-NEXT: retq ## encoding: [0xc3]
2100 %b = load <4 x i32>, <4 x i32>* %ptr_b
2101 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2102 ret <4 x i32> %res
2103 }
2104
2105 define <4 x i32> @test_mask_or_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
2106 ; CHECK-LABEL: test_mask_or_epi32_rmk_128:
2107 ; CHECK: ## BB#0:
2108 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2109 ; CHECK-NEXT: vpord (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xeb,0x0f]
2110 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2111 ; CHECK-NEXT: retq ## encoding: [0xc3]
2112 %b = load <4 x i32>, <4 x i32>* %ptr_b
2113 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2114 ret <4 x i32> %res
2115 }
2116
2117 define <4 x i32> @test_mask_or_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
2118 ; CHECK-LABEL: test_mask_or_epi32_rmkz_128:
2119 ; CHECK: ## BB#0:
2120 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2121 ; CHECK-NEXT: vpord (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xeb,0x07]
2122 ; CHECK-NEXT: retq ## encoding: [0xc3]
2123 %b = load <4 x i32>, <4 x i32>* %ptr_b
2124 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2125 ret <4 x i32> %res
2126 }
2127
2128 define <4 x i32> @test_mask_or_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
2129 ; CHECK-LABEL: test_mask_or_epi32_rmb_128:
2130 ; CHECK: ## BB#0:
2131 ; CHECK-NEXT: vpord (%rdi){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xeb,0x07]
2132 ; CHECK-NEXT: retq ## encoding: [0xc3]
2133 %q = load i32, i32* %ptr_b
2134 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2135 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2136 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2137 ret <4 x i32> %res
2138 }
2139
2140 define <4 x i32> @test_mask_or_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
2141 ; CHECK-LABEL: test_mask_or_epi32_rmbk_128:
2142 ; CHECK: ## BB#0:
2143 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2144 ; CHECK-NEXT: vpord (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xeb,0x0f]
2145 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2146 ; CHECK-NEXT: retq ## encoding: [0xc3]
2147 %q = load i32, i32* %ptr_b
2148 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2149 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2150 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2151 ret <4 x i32> %res
2152 }
2153
2154 define <4 x i32> @test_mask_or_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
2155 ; CHECK-LABEL: test_mask_or_epi32_rmbkz_128:
2156 ; CHECK: ## BB#0:
2157 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2158 ; CHECK-NEXT: vpord (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xeb,0x07]
2159 ; CHECK-NEXT: retq ## encoding: [0xc3]
2160 %q = load i32, i32* %ptr_b
2161 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2162 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2163 %res = call <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2164 ret <4 x i32> %res
2165 }
2166
2167 declare <4 x i32> @llvm.x86.avx512.mask.por.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
2168
2169 define <8 x i32> @test_mask_or_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
2170 ; CHECK-LABEL: test_mask_or_epi32_rr_256:
2171 ; CHECK: ## BB#0:
2172 ; CHECK-NEXT: vpord %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xeb,0xc1]
2173 ; CHECK-NEXT: retq ## encoding: [0xc3]
2174 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2175 ret <8 x i32> %res
2176 }
2177
2178 define <8 x i32> @test_mask_or_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
2179 ; CHECK-LABEL: test_mask_or_epi32_rrk_256:
2180 ; CHECK: ## BB#0:
2181 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2182 ; CHECK-NEXT: vpord %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xeb,0xd1]
2183 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2184 ; CHECK-NEXT: retq ## encoding: [0xc3]
2185 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2186 ret <8 x i32> %res
2187 }
2188
2189 define <8 x i32> @test_mask_or_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
2190 ; CHECK-LABEL: test_mask_or_epi32_rrkz_256:
2191 ; CHECK: ## BB#0:
2192 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2193 ; CHECK-NEXT: vpord %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xeb,0xc1]
2194 ; CHECK-NEXT: retq ## encoding: [0xc3]
2195 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2196 ret <8 x i32> %res
2197 }
2198
2199 define <8 x i32> @test_mask_or_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
2200 ; CHECK-LABEL: test_mask_or_epi32_rm_256:
2201 ; CHECK: ## BB#0:
2202 ; CHECK-NEXT: vpord (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xeb,0x07]
2203 ; CHECK-NEXT: retq ## encoding: [0xc3]
2204 %b = load <8 x i32>, <8 x i32>* %ptr_b
2205 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2206 ret <8 x i32> %res
2207 }
2208
2209 define <8 x i32> @test_mask_or_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2210 ; CHECK-LABEL: test_mask_or_epi32_rmk_256:
2211 ; CHECK: ## BB#0:
2212 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2213 ; CHECK-NEXT: vpord (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xeb,0x0f]
2214 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2215 ; CHECK-NEXT: retq ## encoding: [0xc3]
2216 %b = load <8 x i32>, <8 x i32>* %ptr_b
2217 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2218 ret <8 x i32> %res
2219 }
2220
2221 define <8 x i32> @test_mask_or_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
2222 ; CHECK-LABEL: test_mask_or_epi32_rmkz_256:
2223 ; CHECK: ## BB#0:
2224 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2225 ; CHECK-NEXT: vpord (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xeb,0x07]
2226 ; CHECK-NEXT: retq ## encoding: [0xc3]
2227 %b = load <8 x i32>, <8 x i32>* %ptr_b
2228 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2229 ret <8 x i32> %res
2230 }
2231
2232 define <8 x i32> @test_mask_or_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
2233 ; CHECK-LABEL: test_mask_or_epi32_rmb_256:
2234 ; CHECK: ## BB#0:
2235 ; CHECK-NEXT: vpord (%rdi){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xeb,0x07]
2236 ; CHECK-NEXT: retq ## encoding: [0xc3]
2237 %q = load i32, i32* %ptr_b
2238 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2239 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2240 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2241 ret <8 x i32> %res
2242 }
2243
2244 define <8 x i32> @test_mask_or_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2245 ; CHECK-LABEL: test_mask_or_epi32_rmbk_256:
2246 ; CHECK: ## BB#0:
2247 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2248 ; CHECK-NEXT: vpord (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xeb,0x0f]
2249 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2250 ; CHECK-NEXT: retq ## encoding: [0xc3]
2251 %q = load i32, i32* %ptr_b
2252 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2253 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2254 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2255 ret <8 x i32> %res
2256 }
2257
2258 define <8 x i32> @test_mask_or_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
2259 ; CHECK-LABEL: test_mask_or_epi32_rmbkz_256:
2260 ; CHECK: ## BB#0:
2261 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2262 ; CHECK-NEXT: vpord (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xeb,0x07]
2263 ; CHECK-NEXT: retq ## encoding: [0xc3]
2264 %q = load i32, i32* %ptr_b
2265 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2266 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2267 %res = call <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2268 ret <8 x i32> %res
2269 }
2270
2271 declare <8 x i32> @llvm.x86.avx512.mask.por.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
2272
2273 define <4 x i32> @test_mask_xor_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
2274 ; CHECK-LABEL: test_mask_xor_epi32_rr_128:
2275 ; CHECK: ## BB#0:
2276 ; CHECK-NEXT: vpxord %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xef,0xc1]
2277 ; CHECK-NEXT: retq ## encoding: [0xc3]
2278 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2279 ret <4 x i32> %res
2280 }
2281
2282 define <4 x i32> @test_mask_xor_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
2283 ; CHECK-LABEL: test_mask_xor_epi32_rrk_128:
2284 ; CHECK: ## BB#0:
2285 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2286 ; CHECK-NEXT: vpxord %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xef,0xd1]
2287 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2288 ; CHECK-NEXT: retq ## encoding: [0xc3]
2289 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2290 ret <4 x i32> %res
2291 }
2292
2293 define <4 x i32> @test_mask_xor_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
2294 ; CHECK-LABEL: test_mask_xor_epi32_rrkz_128:
2295 ; CHECK: ## BB#0:
2296 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2297 ; CHECK-NEXT: vpxord %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xef,0xc1]
2298 ; CHECK-NEXT: retq ## encoding: [0xc3]
2299 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2300 ret <4 x i32> %res
2301 }
2302
2303 define <4 x i32> @test_mask_xor_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
2304 ; CHECK-LABEL: test_mask_xor_epi32_rm_128:
2305 ; CHECK: ## BB#0:
2306 ; CHECK-NEXT: vpxord (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xef,0x07]
2307 ; CHECK-NEXT: retq ## encoding: [0xc3]
2308 %b = load <4 x i32>, <4 x i32>* %ptr_b
2309 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2310 ret <4 x i32> %res
2311 }
2312
2313 define <4 x i32> @test_mask_xor_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
2314 ; CHECK-LABEL: test_mask_xor_epi32_rmk_128:
2315 ; CHECK: ## BB#0:
2316 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2317 ; CHECK-NEXT: vpxord (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xef,0x0f]
2318 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2319 ; CHECK-NEXT: retq ## encoding: [0xc3]
2320 %b = load <4 x i32>, <4 x i32>* %ptr_b
2321 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2322 ret <4 x i32> %res
2323 }
2324
2325 define <4 x i32> @test_mask_xor_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
2326 ; CHECK-LABEL: test_mask_xor_epi32_rmkz_128:
2327 ; CHECK: ## BB#0:
2328 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2329 ; CHECK-NEXT: vpxord (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xef,0x07]
2330 ; CHECK-NEXT: retq ## encoding: [0xc3]
2331 %b = load <4 x i32>, <4 x i32>* %ptr_b
2332 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2333 ret <4 x i32> %res
2334 }
2335
2336 define <4 x i32> @test_mask_xor_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
2337 ; CHECK-LABEL: test_mask_xor_epi32_rmb_128:
2338 ; CHECK: ## BB#0:
2339 ; CHECK-NEXT: vpxord (%rdi){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xef,0x07]
2340 ; CHECK-NEXT: retq ## encoding: [0xc3]
2341 %q = load i32, i32* %ptr_b
2342 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2343 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2344 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2345 ret <4 x i32> %res
2346 }
2347
2348 define <4 x i32> @test_mask_xor_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
2349 ; CHECK-LABEL: test_mask_xor_epi32_rmbk_128:
2350 ; CHECK: ## BB#0:
2351 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2352 ; CHECK-NEXT: vpxord (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xef,0x0f]
2353 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2354 ; CHECK-NEXT: retq ## encoding: [0xc3]
2355 %q = load i32, i32* %ptr_b
2356 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2357 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2358 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2359 ret <4 x i32> %res
2360 }
2361
2362 define <4 x i32> @test_mask_xor_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
2363 ; CHECK-LABEL: test_mask_xor_epi32_rmbkz_128:
2364 ; CHECK: ## BB#0:
2365 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2366 ; CHECK-NEXT: vpxord (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xef,0x07]
2367 ; CHECK-NEXT: retq ## encoding: [0xc3]
2368 %q = load i32, i32* %ptr_b
2369 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2370 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2371 %res = call <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2372 ret <4 x i32> %res
2373 }
2374
2375 declare <4 x i32> @llvm.x86.avx512.mask.pxor.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
2376
2377 define <8 x i32> @test_mask_xor_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
2378 ; CHECK-LABEL: test_mask_xor_epi32_rr_256:
2379 ; CHECK: ## BB#0:
2380 ; CHECK-NEXT: vpxord %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xef,0xc1]
2381 ; CHECK-NEXT: retq ## encoding: [0xc3]
2382 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2383 ret <8 x i32> %res
2384 }
2385
2386 define <8 x i32> @test_mask_xor_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
2387 ; CHECK-LABEL: test_mask_xor_epi32_rrk_256:
2388 ; CHECK: ## BB#0:
2389 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2390 ; CHECK-NEXT: vpxord %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xef,0xd1]
2391 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2392 ; CHECK-NEXT: retq ## encoding: [0xc3]
2393 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2394 ret <8 x i32> %res
2395 }
2396
2397 define <8 x i32> @test_mask_xor_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
2398 ; CHECK-LABEL: test_mask_xor_epi32_rrkz_256:
2399 ; CHECK: ## BB#0:
2400 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2401 ; CHECK-NEXT: vpxord %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xef,0xc1]
2402 ; CHECK-NEXT: retq ## encoding: [0xc3]
2403 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2404 ret <8 x i32> %res
2405 }
2406
2407 define <8 x i32> @test_mask_xor_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
2408 ; CHECK-LABEL: test_mask_xor_epi32_rm_256:
2409 ; CHECK: ## BB#0:
2410 ; CHECK-NEXT: vpxord (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xef,0x07]
2411 ; CHECK-NEXT: retq ## encoding: [0xc3]
2412 %b = load <8 x i32>, <8 x i32>* %ptr_b
2413 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2414 ret <8 x i32> %res
2415 }
2416
2417 define <8 x i32> @test_mask_xor_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2418 ; CHECK-LABEL: test_mask_xor_epi32_rmk_256:
2419 ; CHECK: ## BB#0:
2420 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2421 ; CHECK-NEXT: vpxord (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xef,0x0f]
2422 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2423 ; CHECK-NEXT: retq ## encoding: [0xc3]
2424 %b = load <8 x i32>, <8 x i32>* %ptr_b
2425 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2426 ret <8 x i32> %res
2427 }
2428
2429 define <8 x i32> @test_mask_xor_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
2430 ; CHECK-LABEL: test_mask_xor_epi32_rmkz_256:
2431 ; CHECK: ## BB#0:
2432 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2433 ; CHECK-NEXT: vpxord (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xef,0x07]
2434 ; CHECK-NEXT: retq ## encoding: [0xc3]
2435 %b = load <8 x i32>, <8 x i32>* %ptr_b
2436 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2437 ret <8 x i32> %res
2438 }
2439
2440 define <8 x i32> @test_mask_xor_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
2441 ; CHECK-LABEL: test_mask_xor_epi32_rmb_256:
2442 ; CHECK: ## BB#0:
2443 ; CHECK-NEXT: vpxord (%rdi){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xef,0x07]
2444 ; CHECK-NEXT: retq ## encoding: [0xc3]
2445 %q = load i32, i32* %ptr_b
2446 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2447 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2448 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2449 ret <8 x i32> %res
2450 }
2451
2452 define <8 x i32> @test_mask_xor_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2453 ; CHECK-LABEL: test_mask_xor_epi32_rmbk_256:
2454 ; CHECK: ## BB#0:
2455 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2456 ; CHECK-NEXT: vpxord (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xef,0x0f]
2457 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2458 ; CHECK-NEXT: retq ## encoding: [0xc3]
2459 %q = load i32, i32* %ptr_b
2460 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2461 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2462 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2463 ret <8 x i32> %res
2464 }
2465
2466 define <8 x i32> @test_mask_xor_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
2467 ; CHECK-LABEL: test_mask_xor_epi32_rmbkz_256:
2468 ; CHECK: ## BB#0:
2469 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2470 ; CHECK-NEXT: vpxord (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xef,0x07]
2471 ; CHECK-NEXT: retq ## encoding: [0xc3]
2472 %q = load i32, i32* %ptr_b
2473 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2474 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2475 %res = call <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2476 ret <8 x i32> %res
2477 }
2478
2479 declare <8 x i32> @llvm.x86.avx512.mask.pxor.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
2480
2481 define <4 x i32> @test_mask_andnot_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
2482 ; CHECK-LABEL: test_mask_andnot_epi32_rr_128:
2483 ; CHECK: ## BB#0:
2484 ; CHECK-NEXT: vpandnd %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0xc1]
2485 ; CHECK-NEXT: retq ## encoding: [0xc3]
2486 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2487 ret <4 x i32> %res
2488 }
2489
2490 define <4 x i32> @test_mask_andnot_epi32_rrk_128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask) {
2491 ; CHECK-LABEL: test_mask_andnot_epi32_rrk_128:
2492 ; CHECK: ## BB#0:
2493 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2494 ; CHECK-NEXT: vpandnd %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdf,0xd1]
2495 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2496 ; CHECK-NEXT: retq ## encoding: [0xc3]
2497 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2498 ret <4 x i32> %res
2499 }
2500
2501 define <4 x i32> @test_mask_andnot_epi32_rrkz_128(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
2502 ; CHECK-LABEL: test_mask_andnot_epi32_rrkz_128:
2503 ; CHECK: ## BB#0:
2504 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2505 ; CHECK-NEXT: vpandnd %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdf,0xc1]
2506 ; CHECK-NEXT: retq ## encoding: [0xc3]
2507 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2508 ret <4 x i32> %res
2509 }
2510
2511 define <4 x i32> @test_mask_andnot_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
2512 ; CHECK-LABEL: test_mask_andnot_epi32_rm_128:
2513 ; CHECK: ## BB#0:
2514 ; CHECK-NEXT: vpandnd (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0x07]
2515 ; CHECK-NEXT: retq ## encoding: [0xc3]
2516 %b = load <4 x i32>, <4 x i32>* %ptr_b
2517 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2518 ret <4 x i32> %res
2519 }
2520
2521 define <4 x i32> @test_mask_andnot_epi32_rmk_128(<4 x i32> %a, <4 x i32>* %ptr_b, <4 x i32> %passThru, i8 %mask) {
2522 ; CHECK-LABEL: test_mask_andnot_epi32_rmk_128:
2523 ; CHECK: ## BB#0:
2524 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2525 ; CHECK-NEXT: vpandnd (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x09,0xdf,0x0f]
2526 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2527 ; CHECK-NEXT: retq ## encoding: [0xc3]
2528 %b = load <4 x i32>, <4 x i32>* %ptr_b
2529 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2530 ret <4 x i32> %res
2531 }
2532
2533 define <4 x i32> @test_mask_andnot_epi32_rmkz_128(<4 x i32> %a, <4 x i32>* %ptr_b, i8 %mask) {
2534 ; CHECK-LABEL: test_mask_andnot_epi32_rmkz_128:
2535 ; CHECK: ## BB#0:
2536 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2537 ; CHECK-NEXT: vpandnd (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x89,0xdf,0x07]
2538 ; CHECK-NEXT: retq ## encoding: [0xc3]
2539 %b = load <4 x i32>, <4 x i32>* %ptr_b
2540 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2541 ret <4 x i32> %res
2542 }
2543
2544 define <4 x i32> @test_mask_andnot_epi32_rmb_128(<4 x i32> %a, i32* %ptr_b) {
2545 ; CHECK-LABEL: test_mask_andnot_epi32_rmb_128:
2546 ; CHECK: ## BB#0:
2547 ; CHECK-NEXT: vpandnd (%rdi){1to4}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x18,0xdf,0x07]
2548 ; CHECK-NEXT: retq ## encoding: [0xc3]
2549 %q = load i32, i32* %ptr_b
2550 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2551 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2552 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
2553 ret <4 x i32> %res
2554 }
2555
2556 define <4 x i32> @test_mask_andnot_epi32_rmbk_128(<4 x i32> %a, i32* %ptr_b, <4 x i32> %passThru, i8 %mask) {
2557 ; CHECK-LABEL: test_mask_andnot_epi32_rmbk_128:
2558 ; CHECK: ## BB#0:
2559 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2560 ; CHECK-NEXT: vpandnd (%rdi){1to4}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x19,0xdf,0x0f]
2561 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2562 ; CHECK-NEXT: retq ## encoding: [0xc3]
2563 %q = load i32, i32* %ptr_b
2564 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2565 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2566 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passThru, i8 %mask)
2567 ret <4 x i32> %res
2568 }
2569
2570 define <4 x i32> @test_mask_andnot_epi32_rmbkz_128(<4 x i32> %a, i32* %ptr_b, i8 %mask) {
2571 ; CHECK-LABEL: test_mask_andnot_epi32_rmbkz_128:
2572 ; CHECK: ## BB#0:
2573 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2574 ; CHECK-NEXT: vpandnd (%rdi){1to4}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0x99,0xdf,0x07]
2575 ; CHECK-NEXT: retq ## encoding: [0xc3]
2576 %q = load i32, i32* %ptr_b
2577 %vecinit.i = insertelement <4 x i32> undef, i32 %q, i32 0
2578 %b = shufflevector <4 x i32> %vecinit.i, <4 x i32> undef, <4 x i32> zeroinitializer
2579 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 %mask)
2580 ret <4 x i32> %res
2581 }
2582
2583 declare <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)
2584
2585 define <8 x i32> @test_mask_andnot_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
2586 ; CHECK-LABEL: test_mask_andnot_epi32_rr_256:
2587 ; CHECK: ## BB#0:
2588 ; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0xc1]
2589 ; CHECK-NEXT: retq ## encoding: [0xc3]
2590 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2591 ret <8 x i32> %res
2592 }
2593
2594 define <8 x i32> @test_mask_andnot_epi32_rrk_256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask) {
2595 ; CHECK-LABEL: test_mask_andnot_epi32_rrk_256:
2596 ; CHECK: ## BB#0:
2597 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2598 ; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdf,0xd1]
2599 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2600 ; CHECK-NEXT: retq ## encoding: [0xc3]
2601 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2602 ret <8 x i32> %res
2603 }
2604
2605 define <8 x i32> @test_mask_andnot_epi32_rrkz_256(<8 x i32> %a, <8 x i32> %b, i8 %mask) {
2606 ; CHECK-LABEL: test_mask_andnot_epi32_rrkz_256:
2607 ; CHECK: ## BB#0:
2608 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2609 ; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdf,0xc1]
2610 ; CHECK-NEXT: retq ## encoding: [0xc3]
2611 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2612 ret <8 x i32> %res
2613 }
2614
2615 define <8 x i32> @test_mask_andnot_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
2616 ; CHECK-LABEL: test_mask_andnot_epi32_rm_256:
2617 ; CHECK: ## BB#0:
2618 ; CHECK-NEXT: vpandnd (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0x07]
2619 ; CHECK-NEXT: retq ## encoding: [0xc3]
2620 %b = load <8 x i32>, <8 x i32>* %ptr_b
2621 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2622 ret <8 x i32> %res
2623 }
2624
2625 define <8 x i32> @test_mask_andnot_epi32_rmk_256(<8 x i32> %a, <8 x i32>* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2626 ; CHECK-LABEL: test_mask_andnot_epi32_rmk_256:
2627 ; CHECK: ## BB#0:
2628 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2629 ; CHECK-NEXT: vpandnd (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x29,0xdf,0x0f]
2630 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2631 ; CHECK-NEXT: retq ## encoding: [0xc3]
2632 %b = load <8 x i32>, <8 x i32>* %ptr_b
2633 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2634 ret <8 x i32> %res
2635 }
2636
2637 define <8 x i32> @test_mask_andnot_epi32_rmkz_256(<8 x i32> %a, <8 x i32>* %ptr_b, i8 %mask) {
2638 ; CHECK-LABEL: test_mask_andnot_epi32_rmkz_256:
2639 ; CHECK: ## BB#0:
2640 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2641 ; CHECK-NEXT: vpandnd (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xa9,0xdf,0x07]
2642 ; CHECK-NEXT: retq ## encoding: [0xc3]
2643 %b = load <8 x i32>, <8 x i32>* %ptr_b
2644 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2645 ret <8 x i32> %res
2646 }
2647
2648 define <8 x i32> @test_mask_andnot_epi32_rmb_256(<8 x i32> %a, i32* %ptr_b) {
2649 ; CHECK-LABEL: test_mask_andnot_epi32_rmb_256:
2650 ; CHECK: ## BB#0:
2651 ; CHECK-NEXT: vpandnd (%rdi){1to8}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x38,0xdf,0x07]
2652 ; CHECK-NEXT: retq ## encoding: [0xc3]
2653 %q = load i32, i32* %ptr_b
2654 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2655 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2656 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
2657 ret <8 x i32> %res
2658 }
2659
2660 define <8 x i32> @test_mask_andnot_epi32_rmbk_256(<8 x i32> %a, i32* %ptr_b, <8 x i32> %passThru, i8 %mask) {
2661 ; CHECK-LABEL: test_mask_andnot_epi32_rmbk_256:
2662 ; CHECK: ## BB#0:
2663 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2664 ; CHECK-NEXT: vpandnd (%rdi){1to8}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0x7d,0x39,0xdf,0x0f]
2665 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2666 ; CHECK-NEXT: retq ## encoding: [0xc3]
2667 %q = load i32, i32* %ptr_b
2668 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2669 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2670 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> %passThru, i8 %mask)
2671 ret <8 x i32> %res
2672 }
2673
2674 define <8 x i32> @test_mask_andnot_epi32_rmbkz_256(<8 x i32> %a, i32* %ptr_b, i8 %mask) {
2675 ; CHECK-LABEL: test_mask_andnot_epi32_rmbkz_256:
2676 ; CHECK: ## BB#0:
2677 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2678 ; CHECK-NEXT: vpandnd (%rdi){1to8}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0x7d,0xb9,0xdf,0x07]
2679 ; CHECK-NEXT: retq ## encoding: [0xc3]
2680 %q = load i32, i32* %ptr_b
2681 %vecinit.i = insertelement <8 x i32> undef, i32 %q, i32 0
2682 %b = shufflevector <8 x i32> %vecinit.i, <8 x i32> undef, <8 x i32> zeroinitializer
2683 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 %mask)
2684 ret <8 x i32> %res
2685 }
2686
2687 declare <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)
2688
2689 define <2 x i64> @test_mask_andnot_epi64_rr_128(<2 x i64> %a, <2 x i64> %b) {
2690 ; CHECK-LABEL: test_mask_andnot_epi64_rr_128:
2691 ; CHECK: ## BB#0:
2692 ; CHECK-NEXT: vpandnq %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0xc1]
2693 ; CHECK-NEXT: retq ## encoding: [0xc3]
2694 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
2695 ret <2 x i64> %res
2696 }
2697
2698 define <2 x i64> @test_mask_andnot_epi64_rrk_128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask) {
2699 ; CHECK-LABEL: test_mask_andnot_epi64_rrk_128:
2700 ; CHECK: ## BB#0:
2701 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2702 ; CHECK-NEXT: vpandnq %xmm1, %xmm0, %xmm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xdf,0xd1]
2703 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2704 ; CHECK-NEXT: retq ## encoding: [0xc3]
2705 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
2706 ret <2 x i64> %res
2707 }
2708
2709 define <2 x i64> @test_mask_andnot_epi64_rrkz_128(<2 x i64> %a, <2 x i64> %b, i8 %mask) {
2710 ; CHECK-LABEL: test_mask_andnot_epi64_rrkz_128:
2711 ; CHECK: ## BB#0:
2712 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2713 ; CHECK-NEXT: vpandnq %xmm1, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xdf,0xc1]
2714 ; CHECK-NEXT: retq ## encoding: [0xc3]
2715 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
2716 ret <2 x i64> %res
2717 }
2718
2719 define <2 x i64> @test_mask_andnot_epi64_rm_128(<2 x i64> %a, <2 x i64>* %ptr_b) {
2720 ; CHECK-LABEL: test_mask_andnot_epi64_rm_128:
2721 ; CHECK: ## BB#0:
2722 ; CHECK-NEXT: vpandnq (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0x07]
2723 ; CHECK-NEXT: retq ## encoding: [0xc3]
2724 %b = load <2 x i64>, <2 x i64>* %ptr_b
2725 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
2726 ret <2 x i64> %res
2727 }
2728
2729 define <2 x i64> @test_mask_andnot_epi64_rmk_128(<2 x i64> %a, <2 x i64>* %ptr_b, <2 x i64> %passThru, i8 %mask) {
2730 ; CHECK-LABEL: test_mask_andnot_epi64_rmk_128:
2731 ; CHECK: ## BB#0:
2732 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2733 ; CHECK-NEXT: vpandnq (%rdi), %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x09,0xdf,0x0f]
2734 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2735 ; CHECK-NEXT: retq ## encoding: [0xc3]
2736 %b = load <2 x i64>, <2 x i64>* %ptr_b
2737 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
2738 ret <2 x i64> %res
2739 }
2740
2741 define <2 x i64> @test_mask_andnot_epi64_rmkz_128(<2 x i64> %a, <2 x i64>* %ptr_b, i8 %mask) {
2742 ; CHECK-LABEL: test_mask_andnot_epi64_rmkz_128:
2743 ; CHECK: ## BB#0:
2744 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2745 ; CHECK-NEXT: vpandnq (%rdi), %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x89,0xdf,0x07]
2746 ; CHECK-NEXT: retq ## encoding: [0xc3]
2747 %b = load <2 x i64>, <2 x i64>* %ptr_b
2748 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
2749 ret <2 x i64> %res
2750 }
2751
2752 define <2 x i64> @test_mask_andnot_epi64_rmb_128(<2 x i64> %a, i64* %ptr_b) {
2753 ; CHECK-LABEL: test_mask_andnot_epi64_rmb_128:
2754 ; CHECK: ## BB#0:
2755 ; CHECK-NEXT: vpandnq (%rdi){1to2}, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x18,0xdf,0x07]
2756 ; CHECK-NEXT: retq ## encoding: [0xc3]
2757 %q = load i64, i64* %ptr_b
2758 %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
2759 %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
2760 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
2761 ret <2 x i64> %res
2762 }
2763
2764 define <2 x i64> @test_mask_andnot_epi64_rmbk_128(<2 x i64> %a, i64* %ptr_b, <2 x i64> %passThru, i8 %mask) {
2765 ; CHECK-LABEL: test_mask_andnot_epi64_rmbk_128:
2766 ; CHECK: ## BB#0:
2767 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2768 ; CHECK-NEXT: vpandnq (%rdi){1to2}, %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x19,0xdf,0x0f]
2769 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2770 ; CHECK-NEXT: retq ## encoding: [0xc3]
2771 %q = load i64, i64* %ptr_b
2772 %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
2773 %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
2774 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> %passThru, i8 %mask)
2775 ret <2 x i64> %res
2776 }
2777
2778 define <2 x i64> @test_mask_andnot_epi64_rmbkz_128(<2 x i64> %a, i64* %ptr_b, i8 %mask) {
2779 ; CHECK-LABEL: test_mask_andnot_epi64_rmbkz_128:
2780 ; CHECK: ## BB#0:
2781 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2782 ; CHECK-NEXT: vpandnq (%rdi){1to2}, %xmm0, %xmm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0x99,0xdf,0x07]
2783 ; CHECK-NEXT: retq ## encoding: [0xc3]
2784 %q = load i64, i64* %ptr_b
2785 %vecinit.i = insertelement <2 x i64> undef, i64 %q, i32 0
2786 %b = shufflevector <2 x i64> %vecinit.i, <2 x i64> undef, <2 x i32> zeroinitializer
2787 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 %mask)
2788 ret <2 x i64> %res
2789 }
2790
2791 declare <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)
2792
2793 define <4 x i64> @test_mask_andnot_epi64_rr_256(<4 x i64> %a, <4 x i64> %b) {
2794 ; CHECK-LABEL: test_mask_andnot_epi64_rr_256:
2795 ; CHECK: ## BB#0:
2796 ; CHECK-NEXT: vpandnq %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0xc1]
2797 ; CHECK-NEXT: retq ## encoding: [0xc3]
2798 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
2799 ret <4 x i64> %res
2800 }
2801
2802 define <4 x i64> @test_mask_andnot_epi64_rrk_256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask) {
2803 ; CHECK-LABEL: test_mask_andnot_epi64_rrk_256:
2804 ; CHECK: ## BB#0:
2805 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2806 ; CHECK-NEXT: vpandnq %ymm1, %ymm0, %ymm2 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xdf,0xd1]
2807 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc2]
2808 ; CHECK-NEXT: retq ## encoding: [0xc3]
2809 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
2810 ret <4 x i64> %res
2811 }
2812
2813 define <4 x i64> @test_mask_andnot_epi64_rrkz_256(<4 x i64> %a, <4 x i64> %b, i8 %mask) {
2814 ; CHECK-LABEL: test_mask_andnot_epi64_rrkz_256:
2815 ; CHECK: ## BB#0:
2816 ; CHECK-NEXT: kmovw %edi, %k1 ## encoding: [0xc5,0xf8,0x92,0xcf]
2817 ; CHECK-NEXT: vpandnq %ymm1, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xdf,0xc1]
2818 ; CHECK-NEXT: retq ## encoding: [0xc3]
2819 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
2820 ret <4 x i64> %res
2821 }
2822
2823 define <4 x i64> @test_mask_andnot_epi64_rm_256(<4 x i64> %a, <4 x i64>* %ptr_b) {
2824 ; CHECK-LABEL: test_mask_andnot_epi64_rm_256:
2825 ; CHECK: ## BB#0:
2826 ; CHECK-NEXT: vpandnq (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0x07]
2827 ; CHECK-NEXT: retq ## encoding: [0xc3]
2828 %b = load <4 x i64>, <4 x i64>* %ptr_b
2829 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
2830 ret <4 x i64> %res
2831 }
2832
2833 define <4 x i64> @test_mask_andnot_epi64_rmk_256(<4 x i64> %a, <4 x i64>* %ptr_b, <4 x i64> %passThru, i8 %mask) {
2834 ; CHECK-LABEL: test_mask_andnot_epi64_rmk_256:
2835 ; CHECK: ## BB#0:
2836 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2837 ; CHECK-NEXT: vpandnq (%rdi), %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x29,0xdf,0x0f]
2838 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2839 ; CHECK-NEXT: retq ## encoding: [0xc3]
2840 %b = load <4 x i64>, <4 x i64>* %ptr_b
2841 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
2842 ret <4 x i64> %res
2843 }
2844
2845 define <4 x i64> @test_mask_andnot_epi64_rmkz_256(<4 x i64> %a, <4 x i64>* %ptr_b, i8 %mask) {
2846 ; CHECK-LABEL: test_mask_andnot_epi64_rmkz_256:
2847 ; CHECK: ## BB#0:
2848 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2849 ; CHECK-NEXT: vpandnq (%rdi), %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xa9,0xdf,0x07]
2850 ; CHECK-NEXT: retq ## encoding: [0xc3]
2851 %b = load <4 x i64>, <4 x i64>* %ptr_b
2852 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
2853 ret <4 x i64> %res
2854 }
2855
2856 define <4 x i64> @test_mask_andnot_epi64_rmb_256(<4 x i64> %a, i64* %ptr_b) {
2857 ; CHECK-LABEL: test_mask_andnot_epi64_rmb_256:
2858 ; CHECK: ## BB#0:
2859 ; CHECK-NEXT: vpandnq (%rdi){1to4}, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x38,0xdf,0x07]
2860 ; CHECK-NEXT: retq ## encoding: [0xc3]
2861 %q = load i64, i64* %ptr_b
2862 %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
2863 %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
2864 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
2865 ret <4 x i64> %res
2866 }
2867
2868 define <4 x i64> @test_mask_andnot_epi64_rmbk_256(<4 x i64> %a, i64* %ptr_b, <4 x i64> %passThru, i8 %mask) {
2869 ; CHECK-LABEL: test_mask_andnot_epi64_rmbk_256:
2870 ; CHECK: ## BB#0:
2871 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2872 ; CHECK-NEXT: vpandnq (%rdi){1to4}, %ymm0, %ymm1 {%k1} ## encoding: [0x62,0xf1,0xfd,0x39,0xdf,0x0f]
2873 ; CHECK-NEXT: vmovaps %zmm1, %zmm0 ## encoding: [0x62,0xf1,0x7c,0x48,0x28,0xc1]
2874 ; CHECK-NEXT: retq ## encoding: [0xc3]
2875 %q = load i64, i64* %ptr_b
2876 %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
2877 %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
2878 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> %passThru, i8 %mask)
2879 ret <4 x i64> %res
2880 }
2881
2882 define <4 x i64> @test_mask_andnot_epi64_rmbkz_256(<4 x i64> %a, i64* %ptr_b, i8 %mask) {
2883 ; CHECK-LABEL: test_mask_andnot_epi64_rmbkz_256:
2884 ; CHECK: ## BB#0:
2885 ; CHECK-NEXT: kmovw %esi, %k1 ## encoding: [0xc5,0xf8,0x92,0xce]
2886 ; CHECK-NEXT: vpandnq (%rdi){1to4}, %ymm0, %ymm0 {%k1} {z} ## encoding: [0x62,0xf1,0xfd,0xb9,0xdf,0x07]
2887 ; CHECK-NEXT: retq ## encoding: [0xc3]
2888 %q = load i64, i64* %ptr_b
2889 %vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
2890 %b = shufflevector <4 x i64> %vecinit.i, <4 x i64> undef, <4 x i32> zeroinitializer
2891 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 %mask)
2892 ret <4 x i64> %res
2893 }
2894
2895 declare <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
2896
28971857 define i8 @test_cmpps_256(<8 x float> %a, <8 x float> %b) {
28981858 ; CHECK-LABEL: test_cmpps_256:
28991859 ; CHECK: ## BB#0:
69915951 ; CHECK: ## BB#0:
69925952 ; CHECK-NEXT: vmovdqa32 {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
69935953 ; CHECK-NEXT: ## encoding: [0x62,0xf1,0x7d,0x28,0x6f,0x05,A,A,A,A]
6994 ; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI461_0-4, kind: reloc_riprel_4byte
5954 ; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI371_0-4, kind: reloc_riprel_4byte
69955955 ; CHECK-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 ## encoding: [0x62,0xf2,0x7d,0x28,0x46,0x05,A,A,A,A]
6996 ; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI461_1-4, kind: reloc_riprel_4byte
5956 ; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI371_1-4, kind: reloc_riprel_4byte
69975957 ; CHECK-NEXT: retq ## encoding: [0xc3]
69985958 %res = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> , <8 x i32> , <8 x i32> zeroinitializer, i8 -1)
69995959 ret <8 x i32> %res
70245984 ; CHECK: ## BB#0:
70255985 ; CHECK-NEXT: vmovdqa64 {{.*#+}} xmm0 = [2,18446744073709551607]
70265986 ; CHECK-NEXT: ## encoding: [0x62,0xf1,0xfd,0x08,0x6f,0x05,A,A,A,A]
7027 ; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI463_0-4, kind: reloc_riprel_4byte
5987 ; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI373_0-4, kind: reloc_riprel_4byte
70285988 ; CHECK-NEXT: vpsravq {{.*}}(%rip), %xmm0, %xmm0 ## encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A]
7029 ; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI463_1-4, kind: reloc_riprel_4byte
5989 ; CHECK-NEXT: ## fixup A - offset: 6, value: LCPI373_1-4, kind: reloc_riprel_4byte
70305990 ; CHECK-NEXT: retq ## encoding: [0xc3]
70315991 %res = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> , <2 x i64> , <2 x i64> zeroinitializer, i8 -1)
70325992 ret <2 x i64> %res