llvm.org GIT mirror llvm / afc945b
Misc. 1. Remove RA from list of allocatable registers 2. Enable d,y,r constraint inline assembly instructions Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163753 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 7 years ago
1 changed file(s) with 6 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
112112
113113 if (Subtarget->inMips16Mode()) {
114114 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
115 addRegisterClass(MVT::i32, &Mips::CPURARegRegClass);
116115 }
117116
118117 if (!TM.Options.UseSoftFloat) {
15701569 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
15711570 SDVTList VTs = DAG.getVTList(MVT::i32);
15721571
1573 const MipsTargetObjectFile &TLOF = (const MipsTargetObjectFile&)getObjFileLowering();
1572 const MipsTargetObjectFile &TLOF =
1573 (const MipsTargetObjectFile&)getObjFileLowering();
15741574
15751575 // %gp_rel relocation
15761576 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
33243324 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
33253325 case 'y': // Same as 'r'. Exists for compatibility.
33263326 case 'r':
3327 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
3327 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3328 if (Subtarget->inMips16Mode())
3329 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
33283330 return std::make_pair(0U, &Mips::CPURegsRegClass);
3331 }
33293332 if (VT == MVT::i64 && !HasMips64)
33303333 return std::make_pair(0U, &Mips::CPURegsRegClass);
33313334 if (VT == MVT::i64 && HasMips64)