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[TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints() Finally all targets are enabling multiple regalloc hints, so the hook to disable this can now be removed. NFC. Review: Simon Pilgrim https://reviews.llvm.org/D52316 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343851 91177308-0d34-0410-b5e6-96231b3b80d8 Jonas Paulsson 1 year, 10 months ago
13 changed file(s) with 5 addition(s) and 58 deletion(s). Raw diff Collapse all Expand all
822822 MachineFunction &MF) const {
823823 // Do nothing.
824824 }
825
826 /// The creation of multiple copy hints have been implemented in
827 /// weightCalcHelper(), but since this affects so many tests for many
828 /// targets, this is temporarily disabled per default. THIS SHOULD BE
829 /// "GENERAL GOODNESS" and hopefully all targets will update their tests
830 /// and enable this soon. This hook should then be removed.
831 virtual bool enableMultipleCopyHints() const { return false; }
832825
833826 /// Allow the target to reverse allocation order of local live ranges. This
834827 /// will generally allocate shorter local live ranges first. For targets with
6969 return sub == hsub ? hreg : 0;
7070
7171 const TargetRegisterClass *rc = mri.getRegClass(reg);
72 if (!tri.enableMultipleCopyHints()) {
73 // Only allow physreg hints in rc.
74 if (sub == 0)
75 return rc->contains(hreg) ? hreg : 0;
76
77 // reg:sub should match the physreg hreg.
78 return tri.getMatchingSuperReg(hreg, sub, rc);
79 }
80
8172 unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
8273 if (rc->contains(CopiedPReg))
8374 return CopiedPReg;
198189 unsigned Reg;
199190 float Weight;
200191 bool IsPhys;
201 unsigned HintOrder;
202 CopyHint(unsigned R, float W, bool P, unsigned HR) :
203 Reg(R), Weight(W), IsPhys(P), HintOrder(HR) {}
192 CopyHint(unsigned R, float W, bool P) :
193 Reg(R), Weight(W), IsPhys(P) {}
204194 bool operator<(const CopyHint &rhs) const {
205195 // Always prefer any physreg hint.
206196 if (IsPhys != rhs.IsPhys)
207197 return (IsPhys && !rhs.IsPhys);
208198 if (Weight != rhs.Weight)
209199 return (Weight > rhs.Weight);
210
211 // This is just a temporary way to achive NFC for targets that don't
212 // enable multiple copy hints. HintOrder should be removed when all
213 // targets return true in enableMultipleCopyHints().
214 return (HintOrder < rhs.HintOrder);
215
216 #if 0 // Should replace the HintOrder check, see above.
217 // (just for the purpose of maintaining the set)
218 return Reg < rhs.Reg;
219 #endif
200 return Reg < rhs.Reg; // Tie-breaker.
220201 }
221202 };
222203 std::set CopyHints;
223204
224 // Temporary: see comment for HintOrder above.
225 unsigned CopyHintOrder = 0;
226205 for (MachineRegisterInfo::reg_instr_iterator
227206 I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
228207 I != E; ) {
262241 }
263242
264243 // Get allocation hints from copies.
265 if (!mi->isCopy() ||
266 (TargetHint.first != 0 && !tri.enableMultipleCopyHints()))
244 if (!mi->isCopy())
267245 continue;
268246 unsigned hint = copyHint(mi, li.reg, tri, mri);
269247 if (!hint)
274252 // FIXME: we probably shouldn't use floats at all.
275253 volatile float hweight = Hint[hint] += weight;
276254 if (TargetRegisterInfo::isVirtualRegister(hint) || mri.isAllocatable(hint))
277 CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint),
278 (tri.enableMultipleCopyHints() ? hint : CopyHintOrder++)));
255 CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint)));
279256 }
280257
281258 Hint.clear();
293270 // Don't add the same reg twice or the target-type hint again.
294271 continue;
295272 mri.addRegAllocationHint(li.reg, Hint.Reg);
296 if (!tri.enableMultipleCopyHints())
297 break;
298273 }
299274
300275 // Weakly boost the spill weight of hinted registers.
8383 const TargetRegisterClass *
8484 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
8585
86 bool enableMultipleCopyHints() const override { return true; }
87
8886 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
8987 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
9088 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
2626 struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
2727 AMDGPURegisterInfo();
2828
29 bool enableMultipleCopyHints() const override { return true; }
30
3129 /// \returns the sub reg enum value for the given \p Channel
3230 /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
3331 static unsigned getSubRegFromChannel(unsigned Channel);
155155
156156 void updateRegAllocHint(unsigned Reg, unsigned NewReg,
157157 MachineFunction &MF) const override;
158 bool enableMultipleCopyHints() const override { return true; }
159158
160159 bool hasBasePointer(const MachineFunction &MF) const;
161160
2828
2929 BitVector getReservedRegs(const MachineFunction &MF) const override;
3030
31 bool enableMultipleCopyHints() const override { return true; }
32
3331 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
3432 unsigned FIOperandNum,
3533 RegScavenger *RS = nullptr) const override;
3737 CallingConv::ID) const override;
3838
3939 BitVector getReservedRegs(const MachineFunction &MF) const override;
40
41 bool enableMultipleCopyHints() const override { return true; }
4240
4341 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
4442 unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
5656
5757 BitVector getReservedRegs(const MachineFunction &MF) const override;
5858
59 bool enableMultipleCopyHints() const override { return true; }
60
6159 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
6260
6361 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
8484 BitVector getReservedRegs(const MachineFunction &MF) const override;
8585 bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
8686
87 bool enableMultipleCopyHints() const override { return true; }
88
8987 /// We require the register scavenger.
9088 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
9189 return true;
3434 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
3535 unsigned Kind) const override;
3636
37 bool enableMultipleCopyHints() const override { return true; }
38
3937 void eliminateFrameIndex(MachineBasicBlock::iterator II,
4038 int SPAdj, unsigned FIOperandNum,
4139 RegScavenger *RS = nullptr) const override;
5656 const VirtRegMap *VRM,
5757 const LiveRegMatrix *Matrix) const override;
5858
59 bool enableMultipleCopyHints() const override { return true; }
60
6159 // Override TargetRegisterInfo.h.
6260 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
6361 return true;
9494 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
9595 MachineFunction &MF) const override;
9696
97 bool enableMultipleCopyHints() const override { return true; }
98
9997 /// getCalleeSavedRegs - Return a null-terminated list of all of the
10098 /// callee-save registers on this target.
10199 const MCPhysReg *
3232
3333 BitVector getReservedRegs(const MachineFunction &MF) const override;
3434
35 bool enableMultipleCopyHints() const override { return true; }
36
3735 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
3836
3937 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;