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Doxygenify method comments. Try to improve method comments a little. Get rid of some excess whitespace; put braces on previous line when possible. Add stub for method to verify the work of saveState(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9385 91177308-0d34-0410-b5e6-96231b3b80d8 Brian Gaeke 15 years ago
2 changed file(s) with 316 addition(s) and 422 deletion(s). Raw diff Collapse all Expand all
7272 }
7373
7474
75
76 //----------------------------------------------------------------------------
77 // This method initially creates interference graphs (one in each reg class)
78 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
79 //----------------------------------------------------------------------------
75 /// Initialize interference graphs (one in each reg class) and IGNodeLists
76 /// (one in each IG). The actual nodes will be pushed later.
77 ///
8078 void PhyRegAlloc::createIGNodeListsAndIGs() {
8179 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
8280
83 // hash map iterator
8481 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
85
86 // hash map end
8782 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
8883
8984 for (; HMI != HMIEnd ; ++HMI ) {
113108 }
114109
115110
116 //----------------------------------------------------------------------------
117 // This method will add all interferences at for a given instruction.
118 // Interference occurs only if the LR of Def (Inst or Arg) is of the same reg
119 // class as that of live var. The live var passed to this function is the
120 // LVset AFTER the instruction
121 //----------------------------------------------------------------------------
122
123 void PhyRegAlloc::addInterference(const Value *Def,
124 const ValueSet *LVSet,
111 /// Add all interferences for a given instruction. Interference occurs only
112 /// if the LR of Def (Inst or Arg) is of the same reg class as that of live
113 /// var. The live var passed to this function is the LVset AFTER the
114 /// instruction.
115 ///
116 void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
125117 bool isCallInst) {
126118 ValueSet::const_iterator LIt = LVSet->begin();
127119
152144 }
153145
154146
155 //----------------------------------------------------------------------------
156 // For a call instruction, this method sets the CallInterference flag in
157 // the LR of each variable live int the Live Variable Set live after the
158 // call instruction (except the return value of the call instruction - since
159 // the return value does not interfere with that call itself).
160 //----------------------------------------------------------------------------
161
147 /// For a call instruction, this method sets the CallInterference flag in
148 /// the LR of each variable live in the Live Variable Set live after the
149 /// call instruction (except the return value of the call instruction - since
150 /// the return value does not interfere with that call itself).
151 ///
162152 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
163153 const ValueSet *LVSetAft) {
164154 if (DEBUG_RA >= RA_DEBUG_Interference)
210200 }
211201
212202
213 //----------------------------------------------------------------------------
214 // This method will walk thru code and create interferences in the IG of
215 // each RegClass. Also, this method calculates the spill cost of each
216 // Live Range (it is done in this method to save another pass over the code).
217 //----------------------------------------------------------------------------
218
219 void PhyRegAlloc::buildInterferenceGraphs()
220 {
203 /// Create interferences in the IG of each RegClass, and calculate the spill
204 /// cost of each Live Range (it is done in this method to save another pass
205 /// over the code).
206 ///
207 void PhyRegAlloc::buildInterferenceGraphs() {
221208 if (DEBUG_RA >= RA_DEBUG_Interference)
222209 std::cerr << "Creating interference graphs ...\n";
223210
241228 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
242229 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
243230
244 if (isCallInst ) {
231 if (isCallInst) {
245232 // set the isCallInterference flag of each live range which extends
246233 // across this call instruction. This information is used by graph
247234 // coloring algorithm to avoid allocating volatile colors to live ranges
260247 if (LR) LR->addSpillCost(BBLoopDepthCost);
261248 }
262249
263 // if there are multiple defs in this instruction e.g. in SETX
250 // Mark all operands of pseudo-instructions as interfering with one
251 // another. This must be done because pseudo-instructions may be
252 // expanded to multiple instructions by the assembler, so all the
253 // operands must get distinct registers.
264254 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
265255 addInterf4PseudoInstr(MInst);
266256
284274 }
285275
286276
287 //--------------------------------------------------------------------------
288 // Pseudo-instructions may be expanded to multiple instructions by the
289 // assembler. Consequently, all the operands must get distinct registers.
290 // Therefore, we mark all operands of a pseudo-instruction as interfering
291 // with one another.
292 //--------------------------------------------------------------------------
293
277 /// Mark all operands of the given MachineInstr as interfering with one
278 /// another.
279 ///
294280 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
295281 bool setInterf = false;
296282
324310 }
325311
326312
327 //----------------------------------------------------------------------------
328 // This method adds interferences for incoming arguments to a function.
329 //----------------------------------------------------------------------------
330
313 /// Add interferences for incoming arguments to a function.
314 ///
331315 void PhyRegAlloc::addInterferencesForArgs() {
332316 // get the InSet of root BB
333317 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
337321 addInterference(AI, &InSet, false);
338322
339323 if (DEBUG_RA >= RA_DEBUG_Interference)
340 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
341 }
342 }
343
344
345 //----------------------------------------------------------------------------
346 // This method is called after register allocation is complete to set the
347 // allocated registers in the machine code. This code will add register numbers
348 // to MachineOperands that contain a Value. Also it calls target specific
349 // methods to produce caller saving instructions. At the end, it adds all
350 // additional instructions produced by the register allocator to the
351 // instruction stream.
352 //----------------------------------------------------------------------------
353
354 //-----------------------------
355 // Utility functions used below
356 //-----------------------------
357 inline void
358 InsertBefore(MachineInstr* newMI,
359 MachineBasicBlock& MBB,
360 MachineBasicBlock::iterator& MII)
361 {
324 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
325 }
326 }
327
328
329 /// The following are utility functions used solely by updateMachineCode and
330 /// the functions that it calls. They should probably be folded back into
331 /// updateMachineCode at some point.
332 ///
333
334 // used by: updateMachineCode (1 time), PrependInstructions (1 time)
335 inline void InsertBefore(MachineInstr* newMI, MachineBasicBlock& MBB,
336 MachineBasicBlock::iterator& MII) {
362337 MII = MBB.insert(MII, newMI);
363338 ++MII;
364339 }
365340
366 inline void
367 InsertAfter(MachineInstr* newMI,
368 MachineBasicBlock& MBB,
369 MachineBasicBlock::iterator& MII)
370 {
341 // used by: AppendInstructions (1 time)
342 inline void InsertAfter(MachineInstr* newMI, MachineBasicBlock& MBB,
343 MachineBasicBlock::iterator& MII) {
371344 ++MII; // insert before the next instruction
372345 MII = MBB.insert(MII, newMI);
373346 }
374347
375 inline void
376 DeleteInstruction(MachineBasicBlock& MBB,
377 MachineBasicBlock::iterator& MII)
378 {
348 // used by: updateMachineCode (1 time)
349 inline void DeleteInstruction(MachineBasicBlock& MBB,
350 MachineBasicBlock::iterator& MII) {
379351 MII = MBB.erase(MII);
380352 }
381353
382 inline void
383 SubstituteInPlace(MachineInstr* newMI,
384 MachineBasicBlock& MBB,
385 MachineBasicBlock::iterator MII)
386 {
354 // used by: updateMachineCode (1 time)
355 inline void SubstituteInPlace(MachineInstr* newMI, MachineBasicBlock& MBB,
356 MachineBasicBlock::iterator MII) {
387357 *MII = newMI;
388358 }
389359
390 inline void
391 PrependInstructions(std::vector &IBef,
392 MachineBasicBlock& MBB,
393 MachineBasicBlock::iterator& MII,
394 const std::string& msg)
395 {
396 if (!IBef.empty())
397 {
360 // used by: updateMachineCode (2 times)
361 inline void PrependInstructions(std::vector &IBef,
362 MachineBasicBlock& MBB,
363 MachineBasicBlock::iterator& MII,
364 const std::string& msg) {
365 if (!IBef.empty()) {
398366 MachineInstr* OrigMI = *MII;
399367 std::vector::iterator AdIt;
400 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
401 {
368 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
402369 if (DEBUG_RA) {
403370 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
404371 std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
408375 }
409376 }
410377
411 inline void
412 AppendInstructions(std::vector &IAft,
413 MachineBasicBlock& MBB,
414 MachineBasicBlock::iterator& MII,
415 const std::string& msg)
416 {
417 if (!IAft.empty())
418 {
378 // used by: updateMachineCode (1 time)
379 inline void AppendInstructions(std::vector &IAft,
380 MachineBasicBlock& MBB,
381 MachineBasicBlock::iterator& MII,
382 const std::string& msg) {
383 if (!IAft.empty()) {
419384 MachineInstr* OrigMI = *MII;
420385 std::vector::iterator AdIt;
421 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
422 {
386 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
423387 if (DEBUG_RA) {
424388 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
425389 std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
429393 }
430394 }
431395
396 /// Set the registers for operands in the given MachineInstr, if a register was
397 /// successfully allocated. Return true if any of its operands has been marked
398 /// for spill.
399 ///
432400 bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
433401 {
434402 bool instrNeedsSpills = false;
436404 // First, set the registers for operands in the machine instruction
437405 // if a register was successfully allocated. Do this first because we
438406 // will need to know which registers are already used by this instr'n.
439 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
440 {
407 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
441408 MachineOperand& Op = MInst->getOperand(OpNum);
442409 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
443 Op.getType() == MachineOperand::MO_CCRegister)
444 {
410 Op.getType() == MachineOperand::MO_CCRegister) {
445411 const Value *const Val = Op.getVRegValue();
446412 if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
447413 // Remember if any operand needs spilling
459425 return instrNeedsSpills;
460426 }
461427
428 /// Mark allocated registers (using markAllocatedRegs()) on the instruction
429 /// that MII points to. Then, if it's a call instruction, insert caller-saving
430 /// code before and after it. Finally, insert spill code before and after it,
431 /// using insertCode4SpilledLR().
432 ///
462433 void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
463 MachineBasicBlock &MBB)
464 {
434 MachineBasicBlock &MBB) {
465435 MachineInstr* MInst = *MII;
466436 unsigned Opcode = MInst->getOpCode();
467437
492462 // registers. This must be done even for call return instructions
493463 // since those are not handled by the special code above.
494464 if (instrNeedsSpills)
495 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
496 {
465 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
497466 MachineOperand& Op = MInst->getOperand(OpNum);
498467 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
499 Op.getType() == MachineOperand::MO_CCRegister)
500 {
468 Op.getType() == MachineOperand::MO_CCRegister) {
501469 const Value* Val = Op.getVRegValue();
502470 if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
503471 if (LR->isMarkedForSpill())
506474 } // for each operand
507475 }
508476
477 /// Iterate over all the MachineBasicBlocks in the current function and set
478 /// the allocated registers for each instruction (using updateInstruction()),
479 /// after register allocation is complete. Then move code out of delay slots.
480 ///
509481 void PhyRegAlloc::updateMachineCode()
510482 {
511483 // Insert any instructions needed at method entry
518490
519491 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
520492 BBI != BBE; ++BBI) {
521
522493 MachineBasicBlock &MBB = *BBI;
523494
524495 // Iterate over all machine instructions in BB and mark operands with
545516 for (MachineBasicBlock::iterator MII = MBB.begin();
546517 MII != MBB.end(); ++MII)
547518 if (unsigned delaySlots =
548 TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode()))
549 {
519 TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode())) {
550520 MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
551521
552522 // Check the 2 conditions above:
561531 (AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
562532 AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
563533
564 if (cond1 || cond2)
565 {
534 if (cond1 || cond2) {
566535 assert((MInst->getOpCodeFlags() & AnnulFlag) == 0 &&
567536 "FIXME: Moving an annulled delay slot instruction!");
568537 assert(delaySlots==1 &&
645614 }
646615
647616
648 //----------------------------------------------------------------------------
649 // This method inserts spill code for AN operand whose LR was spilled.
650 // This method may be called several times for a single machine instruction
651 // if it contains many spilled operands. Each time it is called, it finds
652 // a register which is not live at that instruction and also which is not
653 // used by other spilled operands of the same instruction. Then it uses
654 // this register temporarily to accommodate the spilled value.
655 //----------------------------------------------------------------------------
656
617 /// Insert spill code for AN operand whose LR was spilled. May be called
618 /// repeatedly for a single MachineInstr if it has many spilled operands. On
619 /// each call, it finds a register which is not live at that instruction and
620 /// also which is not used by other spilled operands of the same
621 /// instruction. Then it uses this register temporarily to accommodate the
622 /// spilled value.
623 ///
657624 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
658625 MachineBasicBlock::iterator& MII,
659626 MachineBasicBlock &MBB,
689656 }
690657 #endif
691658
692 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
659 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
693660
694661 std::vector MIBef, MIAft;
695662 std::vector AdIMid;
715682 // for the copy and not used across MInst.
716683 int scratchRegType = -1;
717684 int scratchReg = -1;
718 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
719 {
685 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
720686 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
721687 MInst, MIBef, MIAft);
722688 assert(scratchReg != MRI.getInvalidRegNum());
760726 }
761727
762728
763 //----------------------------------------------------------------------------
764 // This method inserts caller saving/restoring instructions before/after
765 // a call machine instruction. The caller saving/restoring instructions are
766 // inserted like:
767 // ** caller saving instructions
768 // other instructions inserted for the call by ColorCallArg
769 // CALL instruction
770 // other instructions inserted for the call ColorCallArg
771 // ** caller restoring instructions
772 //----------------------------------------------------------------------------
773
729 /// Insert caller saving/restoring instructions before/after a call machine
730 /// instruction (before or after any other instructions that were inserted for
731 /// the call).
732 ///
774733 void
775734 PhyRegAlloc::insertCallerSavingCode(std::vector &instrnsBefore,
776735 std::vector &instrnsAfter,
777736 MachineInstr *CallMI,
778 const BasicBlock *BB)
779 {
737 const BasicBlock *BB) {
780738 assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
781739
782740 // hash set to record which registers were saved/restored
826784
827785 // LR can be null if it is a const since a const
828786 // doesn't have a dominating def - see Assumptions above
829 if( LR ) {
830 if(! LR->isMarkedForSpill()) {
787 if (LR) {
788 if (! LR->isMarkedForSpill()) {
831789 assert(LR->hasColor() && "LR is neither spilled nor colored?");
832790 unsigned RCID = LR->getRegClassID();
833791 unsigned Color = LR->getColor();
932890 }
933891
934892
935 //----------------------------------------------------------------------------
936 // We can use the following method to get a temporary register to be used
937 // BEFORE any given machine instruction. If there is a register available,
938 // this method will simply return that register and set MIBef = MIAft = NULL.
939 // Otherwise, it will return a register and MIAft and MIBef will contain
940 // two instructions used to free up this returned register.
941 // Returned register number is the UNIFIED register number
942 //----------------------------------------------------------------------------
943
893 /// Returns the unified register number of a temporary register to be used
894 /// BEFORE MInst. If no register is available, it will pick one and modify
895 /// MIBef and MIAft to contain instructions used to free up this returned
896 /// register.
897 ///
944898 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
945899 const ValueSet *LVSetBef,
946900 MachineInstr *MInst,
948902 std::vector& MIAft) {
949903 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
950904
951 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
905 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
952906
953907 if (RegU == -1) {
954908 // we couldn't find an unused register. Generate code to free up a reg by
960914
961915 // Check if we need a scratch register to copy this register to memory.
962916 int scratchRegType = -1;
963 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
964 {
917 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
965918 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
966919 MInst, MIBef, MIAft);
967920 assert(scratchReg != MRI.getInvalidRegNum());
973926 ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
974927 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
975928 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
976 }
977 else
978 { // the register can be copied directly to/from memory so do it.
929 } else { // the register can be copied directly to/from memory so do it.
979930 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
980931 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
981 }
932 }
982933 }
983934
984935 return RegU;
985936 }
986937
987938
988 //----------------------------------------------------------------------------
989 // This method is called to get a new unused register that can be used
990 // to accommodate a temporary value. This method may be called several times
991 // for a single machine instruction. Each time it is called, it finds a
992 // register which is not live at that instruction and also which is not used
993 // by other spilled operands of the same instruction. Return register number
994 // is relative to the register class, NOT the unified number.
995 //----------------------------------------------------------------------------
996
997 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
998 const int RegType,
939 /// Returns the register-class register number of a new unused register that
940 /// can be used to accommodate a temporary value. May be called repeatedly
941 /// for a single MachineInstr. On each call, it finds a register which is not
942 /// live at that instruction and which is not used by any spilled operands of
943 /// that instruction.
944 ///
945 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC, const int RegType,
999946 const MachineInstr *MInst,
1000947 const ValueSet* LVSetBef) {
1001948 RC->clearColorsUsed(); // Reset array
1032979 }
1033980
1034981
1035 //----------------------------------------------------------------------------
1036 // Get any other register in a register class, other than what is used
1037 // by operands of a machine instruction. Returns the unified reg number.
1038 //----------------------------------------------------------------------------
1039
982 /// Return the unified register number of a register in class RC which is not
983 /// used by any operands of MInst.
984 ///
1040985 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
1041986 const int RegType,
1042987 const MachineInstr *MInst) {
1053998 }
1054999
10551000
1056 //----------------------------------------------------------------------------
1057 // This method modifies the IsColorUsedArr of the register class passed to it.
1058 // It sets the bits corresponding to the registers used by this machine
1059 // instructions. Both explicit and implicit operands are set.
1060 //----------------------------------------------------------------------------
1061
1001 /// Modify the IsColorUsedArr of register class RC, by setting the bits
1002 /// corresponding to register RegNo. This is a helper method of
1003 /// setRelRegsUsedByThisInst().
1004 ///
10621005 static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
10631006 const TargetRegInfo &TRI) {
10641007 unsigned classId = 0;
10681011 }
10691012
10701013 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
1071 const MachineInstr *MI)
1072 {
1014 const MachineInstr *MI) {
10731015 assert(OperandsColoredMap[MI] == true &&
10741016 "Illegal to call setRelRegsUsedByThisInst() until colored operands "
10751017 "are marked for an instruction.");
10761018
1077 // Add the registers already marked as used by the instruction.
1019 // Add the registers already marked as used by the instruction. Both
1020 // explicit and implicit operands are set.
10781021 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
10791022 if (MI->getOperand(i).hasAllocatedReg())
10801023 markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
11021045 }
11031046
11041047
1105 //----------------------------------------------------------------------------
1106 // If there are delay slots for an instruction, the instructions
1107 // added after it must really go after the delayed instruction(s).
1108 // So, we move the InstrAfter of that instruction to the
1109 // corresponding delayed instruction using the following method.
1110 //----------------------------------------------------------------------------
1111
1048 /// If there are delay slots for an instruction, the instructions added after
1049 /// it must really go after the delayed instruction(s). So, we Move the
1050 /// InstrAfter of that instruction to the corresponding delayed instruction
1051 /// using the following method.
1052 ///
11121053 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
11131054 const MachineInstr *DelayedMI)
11141055 {
11401081 }
11411082
11421083
1143 //----------------------------------------------------------------------------
1144 // This method determines whether the suggested color of each live range
1145 // is really usable, and then calls its setSuggestedColorUsable() method to
1146 // record the answer. A suggested color is NOT usable when the suggested color
1147 // is volatile AND when there are call interferences.
1148 //----------------------------------------------------------------------------
1149
1084 /// Determine whether the suggested color of each live range is really usable,
1085 /// and then call its setSuggestedColorUsable() method to record the answer. A
1086 /// suggested color is NOT usable when the suggested color is volatile AND
1087 /// when there are call interferences.
1088 ///
11501089 void PhyRegAlloc::markUnusableSugColors()
11511090 {
11521091 LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
11641103 }
11651104
11661105
1167 //----------------------------------------------------------------------------
1168 // The following method will set the stack offsets of the live ranges that
1169 // are decided to be spilled. This must be called just after coloring the
1170 // LRs using the graph coloring algo. For each live range that is spilled,
1171 // this method allocate a new spill position on the stack.
1172 //----------------------------------------------------------------------------
1173
1106 /// For each live range that is spilled, allocates a new spill position on the
1107 /// stack, and set the stack offsets of the live range that will be spilled to
1108 /// that position. This must be called just after coloring the LRs.
1109 ///
11741110 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
11751111 if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
11761112
12341170 };
12351171 }
12361172
1237 void PhyRegAlloc::saveState ()
1238 {
1173 /// Save the global register allocation decisions made by the register
1174 /// allocator so that they can be accessed later (sort of like "poor man's
1175 /// debug info").
1176 ///
1177 void PhyRegAlloc::saveState () {
12391178 std::vector state;
12401179 unsigned Insn = 0;
12411180 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
12831222 FnAllocState[Fn] = S;
12841223 }
12851224
1225 /// Check the saved state filled in by saveState(), and abort if it looks
1226 /// wrong. Only used when debugging.
1227 ///
1228 void PhyRegAlloc::verifySavedState () {
1229 /// not yet implemented
1230 }
12861231
12871232 bool PhyRegAlloc::doFinalization (Module &M) {
12881233 if (!SaveRegAllocState)
13311276 }
13321277
13331278
1334 //----------------------------------------------------------------------------
1335 // The entry point to Register Allocation
1336 //----------------------------------------------------------------------------
1337
1279 /// Allocate registers for the machine code previously generated for F using
1280 /// the graph-coloring algorithm.
1281 ///
13381282 bool PhyRegAlloc::runOnFunction (Function &F) {
13391283 if (DEBUG_RA)
13401284 std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
14051349 // Save register allocation state for this function in a Constant.
14061350 if (SaveRegAllocState)
14071351 saveState();
1352 if (DEBUG_RA) { // Check our work.
1353 verifySavedState ();
1354 }
14081355
14091356 // Now update the machine code with register names and add any
14101357 // additional code inserted by the register allocator to the instruction
7272 }
7373
7474
75
76 //----------------------------------------------------------------------------
77 // This method initially creates interference graphs (one in each reg class)
78 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
79 //----------------------------------------------------------------------------
75 /// Initialize interference graphs (one in each reg class) and IGNodeLists
76 /// (one in each IG). The actual nodes will be pushed later.
77 ///
8078 void PhyRegAlloc::createIGNodeListsAndIGs() {
8179 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
8280
83 // hash map iterator
8481 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
85
86 // hash map end
8782 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
8883
8984 for (; HMI != HMIEnd ; ++HMI ) {
113108 }
114109
115110
116 //----------------------------------------------------------------------------
117 // This method will add all interferences at for a given instruction.
118 // Interference occurs only if the LR of Def (Inst or Arg) is of the same reg
119 // class as that of live var. The live var passed to this function is the
120 // LVset AFTER the instruction
121 //----------------------------------------------------------------------------
122
123 void PhyRegAlloc::addInterference(const Value *Def,
124 const ValueSet *LVSet,
111 /// Add all interferences for a given instruction. Interference occurs only
112 /// if the LR of Def (Inst or Arg) is of the same reg class as that of live
113 /// var. The live var passed to this function is the LVset AFTER the
114 /// instruction.
115 ///
116 void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
125117 bool isCallInst) {
126118 ValueSet::const_iterator LIt = LVSet->begin();
127119
152144 }
153145
154146
155 //----------------------------------------------------------------------------
156 // For a call instruction, this method sets the CallInterference flag in
157 // the LR of each variable live int the Live Variable Set live after the
158 // call instruction (except the return value of the call instruction - since
159 // the return value does not interfere with that call itself).
160 //----------------------------------------------------------------------------
161
147 /// For a call instruction, this method sets the CallInterference flag in
148 /// the LR of each variable live in the Live Variable Set live after the
149 /// call instruction (except the return value of the call instruction - since
150 /// the return value does not interfere with that call itself).
151 ///
162152 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
163153 const ValueSet *LVSetAft) {
164154 if (DEBUG_RA >= RA_DEBUG_Interference)
210200 }
211201
212202
213 //----------------------------------------------------------------------------
214 // This method will walk thru code and create interferences in the IG of
215 // each RegClass. Also, this method calculates the spill cost of each
216 // Live Range (it is done in this method to save another pass over the code).
217 //----------------------------------------------------------------------------
218
219 void PhyRegAlloc::buildInterferenceGraphs()
220 {
203 /// Create interferences in the IG of each RegClass, and calculate the spill
204 /// cost of each Live Range (it is done in this method to save another pass
205 /// over the code).
206 ///
207 void PhyRegAlloc::buildInterferenceGraphs() {
221208 if (DEBUG_RA >= RA_DEBUG_Interference)
222209 std::cerr << "Creating interference graphs ...\n";
223210
241228 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
242229 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
243230
244 if (isCallInst ) {
231 if (isCallInst) {
245232 // set the isCallInterference flag of each live range which extends
246233 // across this call instruction. This information is used by graph
247234 // coloring algorithm to avoid allocating volatile colors to live ranges
260247 if (LR) LR->addSpillCost(BBLoopDepthCost);
261248 }
262249
263 // if there are multiple defs in this instruction e.g. in SETX
250 // Mark all operands of pseudo-instructions as interfering with one
251 // another. This must be done because pseudo-instructions may be
252 // expanded to multiple instructions by the assembler, so all the
253 // operands must get distinct registers.
264254 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
265255 addInterf4PseudoInstr(MInst);
266256
284274 }
285275
286276
287 //--------------------------------------------------------------------------
288 // Pseudo-instructions may be expanded to multiple instructions by the
289 // assembler. Consequently, all the operands must get distinct registers.
290 // Therefore, we mark all operands of a pseudo-instruction as interfering
291 // with one another.
292 //--------------------------------------------------------------------------
293
277 /// Mark all operands of the given MachineInstr as interfering with one
278 /// another.
279 ///
294280 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
295281 bool setInterf = false;
296282
324310 }
325311
326312
327 //----------------------------------------------------------------------------
328 // This method adds interferences for incoming arguments to a function.
329 //----------------------------------------------------------------------------
330
313 /// Add interferences for incoming arguments to a function.
314 ///
331315 void PhyRegAlloc::addInterferencesForArgs() {
332316 // get the InSet of root BB
333317 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
337321 addInterference(AI, &InSet, false);
338322
339323 if (DEBUG_RA >= RA_DEBUG_Interference)
340 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
341 }
342 }
343
344
345 //----------------------------------------------------------------------------
346 // This method is called after register allocation is complete to set the
347 // allocated registers in the machine code. This code will add register numbers
348 // to MachineOperands that contain a Value. Also it calls target specific
349 // methods to produce caller saving instructions. At the end, it adds all
350 // additional instructions produced by the register allocator to the
351 // instruction stream.
352 //----------------------------------------------------------------------------
353
354 //-----------------------------
355 // Utility functions used below
356 //-----------------------------
357 inline void
358 InsertBefore(MachineInstr* newMI,
359 MachineBasicBlock& MBB,
360 MachineBasicBlock::iterator& MII)
361 {
324 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
325 }
326 }
327
328
329 /// The following are utility functions used solely by updateMachineCode and
330 /// the functions that it calls. They should probably be folded back into
331 /// updateMachineCode at some point.
332 ///
333
334 // used by: updateMachineCode (1 time), PrependInstructions (1 time)
335 inline void InsertBefore(MachineInstr* newMI, MachineBasicBlock& MBB,
336 MachineBasicBlock::iterator& MII) {
362337 MII = MBB.insert(MII, newMI);
363338 ++MII;
364339 }
365340
366 inline void
367 InsertAfter(MachineInstr* newMI,
368 MachineBasicBlock& MBB,
369 MachineBasicBlock::iterator& MII)
370 {
341 // used by: AppendInstructions (1 time)
342 inline void InsertAfter(MachineInstr* newMI, MachineBasicBlock& MBB,
343 MachineBasicBlock::iterator& MII) {
371344 ++MII; // insert before the next instruction
372345 MII = MBB.insert(MII, newMI);
373346 }
374347
375 inline void
376 DeleteInstruction(MachineBasicBlock& MBB,
377 MachineBasicBlock::iterator& MII)
378 {
348 // used by: updateMachineCode (1 time)
349 inline void DeleteInstruction(MachineBasicBlock& MBB,
350 MachineBasicBlock::iterator& MII) {
379351 MII = MBB.erase(MII);
380352 }
381353
382 inline void
383 SubstituteInPlace(MachineInstr* newMI,
384 MachineBasicBlock& MBB,
385 MachineBasicBlock::iterator MII)
386 {
354 // used by: updateMachineCode (1 time)
355 inline void SubstituteInPlace(MachineInstr* newMI, MachineBasicBlock& MBB,
356 MachineBasicBlock::iterator MII) {
387357 *MII = newMI;
388358 }
389359
390 inline void
391 PrependInstructions(std::vector &IBef,
392 MachineBasicBlock& MBB,
393 MachineBasicBlock::iterator& MII,
394 const std::string& msg)
395 {
396 if (!IBef.empty())
397 {
360 // used by: updateMachineCode (2 times)
361 inline void PrependInstructions(std::vector &IBef,
362 MachineBasicBlock& MBB,
363 MachineBasicBlock::iterator& MII,
364 const std::string& msg) {
365 if (!IBef.empty()) {
398366 MachineInstr* OrigMI = *MII;
399367 std::vector::iterator AdIt;
400 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
401 {
368 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
402369 if (DEBUG_RA) {
403370 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
404371 std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
408375 }
409376 }
410377
411 inline void
412 AppendInstructions(std::vector &IAft,
413 MachineBasicBlock& MBB,
414 MachineBasicBlock::iterator& MII,
415 const std::string& msg)
416 {
417 if (!IAft.empty())
418 {
378 // used by: updateMachineCode (1 time)
379 inline void AppendInstructions(std::vector &IAft,
380 MachineBasicBlock& MBB,
381 MachineBasicBlock::iterator& MII,
382 const std::string& msg) {
383 if (!IAft.empty()) {
419384 MachineInstr* OrigMI = *MII;
420385 std::vector::iterator AdIt;
421 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
422 {
386 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
423387 if (DEBUG_RA) {
424388 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
425389 std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
429393 }
430394 }
431395
396 /// Set the registers for operands in the given MachineInstr, if a register was
397 /// successfully allocated. Return true if any of its operands has been marked
398 /// for spill.
399 ///
432400 bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
433401 {
434402 bool instrNeedsSpills = false;
436404 // First, set the registers for operands in the machine instruction
437405 // if a register was successfully allocated. Do this first because we
438406 // will need to know which registers are already used by this instr'n.
439 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
440 {
407 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
441408 MachineOperand& Op = MInst->getOperand(OpNum);
442409 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
443 Op.getType() == MachineOperand::MO_CCRegister)
444 {
410 Op.getType() == MachineOperand::MO_CCRegister) {
445411 const Value *const Val = Op.getVRegValue();
446412 if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
447413 // Remember if any operand needs spilling
459425 return instrNeedsSpills;
460426 }
461427
428 /// Mark allocated registers (using markAllocatedRegs()) on the instruction
429 /// that MII points to. Then, if it's a call instruction, insert caller-saving
430 /// code before and after it. Finally, insert spill code before and after it,
431 /// using insertCode4SpilledLR().
432 ///
462433 void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
463 MachineBasicBlock &MBB)
464 {
434 MachineBasicBlock &MBB) {
465435 MachineInstr* MInst = *MII;
466436 unsigned Opcode = MInst->getOpCode();
467437
492462 // registers. This must be done even for call return instructions
493463 // since those are not handled by the special code above.
494464 if (instrNeedsSpills)
495 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
496 {
465 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
497466 MachineOperand& Op = MInst->getOperand(OpNum);
498467 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
499 Op.getType() == MachineOperand::MO_CCRegister)
500 {
468 Op.getType() == MachineOperand::MO_CCRegister) {
501469 const Value* Val = Op.getVRegValue();
502470 if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
503471 if (LR->isMarkedForSpill())
506474 } // for each operand
507475 }
508476
477 /// Iterate over all the MachineBasicBlocks in the current function and set
478 /// the allocated registers for each instruction (using updateInstruction()),
479 /// after register allocation is complete. Then move code out of delay slots.
480 ///
509481 void PhyRegAlloc::updateMachineCode()
510482 {
511483 // Insert any instructions needed at method entry
518490
519491 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
520492 BBI != BBE; ++BBI) {
521
522493 MachineBasicBlock &MBB = *BBI;
523494
524495 // Iterate over all machine instructions in BB and mark operands with
545516 for (MachineBasicBlock::iterator MII = MBB.begin();
546517 MII != MBB.end(); ++MII)
547518 if (unsigned delaySlots =
548 TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode()))
549 {
519 TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode())) {
550520 MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
551521
552522 // Check the 2 conditions above:
561531 (AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
562532 AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
563533
564 if (cond1 || cond2)
565 {
534 if (cond1 || cond2) {
566535 assert((MInst->getOpCodeFlags() & AnnulFlag) == 0 &&
567536 "FIXME: Moving an annulled delay slot instruction!");
568537 assert(delaySlots==1 &&
645614 }
646615
647616
648 //----------------------------------------------------------------------------
649 // This method inserts spill code for AN operand whose LR was spilled.
650 // This method may be called several times for a single machine instruction
651 // if it contains many spilled operands. Each time it is called, it finds
652 // a register which is not live at that instruction and also which is not
653 // used by other spilled operands of the same instruction. Then it uses
654 // this register temporarily to accommodate the spilled value.
655 //----------------------------------------------------------------------------
656
617 /// Insert spill code for AN operand whose LR was spilled. May be called
618 /// repeatedly for a single MachineInstr if it has many spilled operands. On
619 /// each call, it finds a register which is not live at that instruction and
620 /// also which is not used by other spilled operands of the same
621 /// instruction. Then it uses this register temporarily to accommodate the
622 /// spilled value.
623 ///
657624 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
658625 MachineBasicBlock::iterator& MII,
659626 MachineBasicBlock &MBB,
689656 }
690657 #endif
691658
692 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
659 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
693660
694661 std::vector MIBef, MIAft;
695662 std::vector AdIMid;
715682 // for the copy and not used across MInst.
716683 int scratchRegType = -1;
717684 int scratchReg = -1;
718 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
719 {
685 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
720686 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
721687 MInst, MIBef, MIAft);
722688 assert(scratchReg != MRI.getInvalidRegNum());
760726 }
761727
762728
763 //----------------------------------------------------------------------------
764 // This method inserts caller saving/restoring instructions before/after
765 // a call machine instruction. The caller saving/restoring instructions are
766 // inserted like:
767 // ** caller saving instructions
768 // other instructions inserted for the call by ColorCallArg
769 // CALL instruction
770 // other instructions inserted for the call ColorCallArg
771 // ** caller restoring instructions
772 //----------------------------------------------------------------------------
773
729 /// Insert caller saving/restoring instructions before/after a call machine
730 /// instruction (before or after any other instructions that were inserted for
731 /// the call).
732 ///
774733 void
775734 PhyRegAlloc::insertCallerSavingCode(std::vector &instrnsBefore,
776735 std::vector &instrnsAfter,
777736 MachineInstr *CallMI,
778 const BasicBlock *BB)
779 {
737 const BasicBlock *BB) {
780738 assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
781739
782740 // hash set to record which registers were saved/restored
826784
827785 // LR can be null if it is a const since a const
828786 // doesn't have a dominating def - see Assumptions above
829 if( LR ) {
830 if(! LR->isMarkedForSpill()) {
787 if (LR) {
788 if (! LR->isMarkedForSpill()) {
831789 assert(LR->hasColor() && "LR is neither spilled nor colored?");
832790 unsigned RCID = LR->getRegClassID();
833791 unsigned Color = LR->getColor();
932890 }
933891
934892
935 //----------------------------------------------------------------------------
936 // We can use the following method to get a temporary register to be used
937 // BEFORE any given machine instruction. If there is a register available,
938 // this method will simply return that register and set MIBef = MIAft = NULL.
939 // Otherwise, it will return a register and MIAft and MIBef will contain
940 // two instructions used to free up this returned register.
941 // Returned register number is the UNIFIED register number
942 //----------------------------------------------------------------------------
943
893 /// Returns the unified register number of a temporary register to be used
894 /// BEFORE MInst. If no register is available, it will pick one and modify
895 /// MIBef and MIAft to contain instructions used to free up this returned
896 /// register.
897 ///
944898 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
945899 const ValueSet *LVSetBef,
946900 MachineInstr *MInst,
948902 std::vector& MIAft) {
949903 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
950904
951 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
905 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
952906
953907 if (RegU == -1) {
954908 // we couldn't find an unused register. Generate code to free up a reg by
960914
961915 // Check if we need a scratch register to copy this register to memory.
962916 int scratchRegType = -1;
963 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
964 {
917 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
965918 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
966919 MInst, MIBef, MIAft);
967920 assert(scratchReg != MRI.getInvalidRegNum());
973926 ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
974927 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
975928 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
976 }
977 else
978 { // the register can be copied directly to/from memory so do it.
929 } else { // the register can be copied directly to/from memory so do it.
979930 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
980931 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
981 }
932 }
982933 }
983934
984935 return RegU;
985936 }
986937
987938
988 //----------------------------------------------------------------------------
989 // This method is called to get a new unused register that can be used
990 // to accommodate a temporary value. This method may be called several times
991 // for a single machine instruction. Each time it is called, it finds a
992 // register which is not live at that instruction and also which is not used
993 // by other spilled operands of the same instruction. Return register number
994 // is relative to the register class, NOT the unified number.
995 //----------------------------------------------------------------------------
996
997 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
998 const int RegType,
939 /// Returns the register-class register number of a new unused register that
940 /// can be used to accommodate a temporary value. May be called repeatedly
941 /// for a single MachineInstr. On each call, it finds a register which is not
942 /// live at that instruction and which is not used by any spilled operands of
943 /// that instruction.
944 ///
945 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC, const int RegType,
999946 const MachineInstr *MInst,
1000947 const ValueSet* LVSetBef) {
1001948 RC->clearColorsUsed(); // Reset array
1032979 }
1033980
1034981
1035 //----------------------------------------------------------------------------
1036 // Get any other register in a register class, other than what is used
1037 // by operands of a machine instruction. Returns the unified reg number.
1038 //----------------------------------------------------------------------------
1039
982 /// Return the unified register number of a register in class RC which is not
983 /// used by any operands of MInst.
984 ///
1040985 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
1041986 const int RegType,
1042987 const MachineInstr *MInst) {
1053998 }
1054999
10551000
1056 //----------------------------------------------------------------------------
1057 // This method modifies the IsColorUsedArr of the register class passed to it.
1058 // It sets the bits corresponding to the registers used by this machine
1059 // instructions. Both explicit and implicit operands are set.
1060 //----------------------------------------------------------------------------
1061
1001 /// Modify the IsColorUsedArr of register class RC, by setting the bits
1002 /// corresponding to register RegNo. This is a helper method of
1003 /// setRelRegsUsedByThisInst().
1004 ///
10621005 static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
10631006 const TargetRegInfo &TRI) {
10641007 unsigned classId = 0;
10681011 }
10691012
10701013 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
1071 const MachineInstr *MI)
1072 {
1014 const MachineInstr *MI) {
10731015 assert(OperandsColoredMap[MI] == true &&
10741016 "Illegal to call setRelRegsUsedByThisInst() until colored operands "
10751017 "are marked for an instruction.");
10761018
1077 // Add the registers already marked as used by the instruction.
1019 // Add the registers already marked as used by the instruction. Both
1020 // explicit and implicit operands are set.
10781021 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
10791022 if (MI->getOperand(i).hasAllocatedReg())
10801023 markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
11021045 }
11031046
11041047
1105 //----------------------------------------------------------------------------
1106 // If there are delay slots for an instruction, the instructions
1107 // added after it must really go after the delayed instruction(s).
1108 // So, we move the InstrAfter of that instruction to the
1109 // corresponding delayed instruction using the following method.
1110 //----------------------------------------------------------------------------
1111
1048 /// If there are delay slots for an instruction, the instructions added after
1049 /// it must really go after the delayed instruction(s). So, we Move the
1050 /// InstrAfter of that instruction to the corresponding delayed instruction
1051 /// using the following method.
1052 ///
11121053 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
11131054 const MachineInstr *DelayedMI)
11141055 {
11401081 }
11411082
11421083
1143 //----------------------------------------------------------------------------
1144 // This method determines whether the suggested color of each live range
1145 // is really usable, and then calls its setSuggestedColorUsable() method to
1146 // record the answer. A suggested color is NOT usable when the suggested color
1147 // is volatile AND when there are call interferences.
1148 //----------------------------------------------------------------------------
1149
1084 /// Determine whether the suggested color of each live range is really usable,
1085 /// and then call its setSuggestedColorUsable() method to record the answer. A
1086 /// suggested color is NOT usable when the suggested color is volatile AND
1087 /// when there are call interferences.
1088 ///
11501089 void PhyRegAlloc::markUnusableSugColors()
11511090 {
11521091 LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
11641103 }
11651104
11661105
1167 //----------------------------------------------------------------------------
1168 // The following method will set the stack offsets of the live ranges that
1169 // are decided to be spilled. This must be called just after coloring the
1170 // LRs using the graph coloring algo. For each live range that is spilled,
1171 // this method allocate a new spill position on the stack.
1172 //----------------------------------------------------------------------------
1173
1106 /// For each live range that is spilled, allocates a new spill position on the
1107 /// stack, and set the stack offsets of the live range that will be spilled to
1108 /// that position. This must be called just after coloring the LRs.
1109 ///
11741110 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
11751111 if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
11761112
12341170 };
12351171 }
12361172
1237 void PhyRegAlloc::saveState ()
1238 {
1173 /// Save the global register allocation decisions made by the register
1174 /// allocator so that they can be accessed later (sort of like "poor man's
1175 /// debug info").
1176 ///
1177 void PhyRegAlloc::saveState () {
12391178 std::vector state;
12401179 unsigned Insn = 0;
12411180 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
12831222 FnAllocState[Fn] = S;
12841223 }
12851224
1225 /// Check the saved state filled in by saveState(), and abort if it looks
1226 /// wrong. Only used when debugging.
1227 ///
1228 void PhyRegAlloc::verifySavedState () {
1229 /// not yet implemented
1230 }
12861231
12871232 bool PhyRegAlloc::doFinalization (Module &M) {
12881233 if (!SaveRegAllocState)
13311276 }
13321277
13331278
1334 //----------------------------------------------------------------------------
1335 // The entry point to Register Allocation
1336 //----------------------------------------------------------------------------
1337
1279 /// Allocate registers for the machine code previously generated for F using
1280 /// the graph-coloring algorithm.
1281 ///
13381282 bool PhyRegAlloc::runOnFunction (Function &F) {
13391283 if (DEBUG_RA)
13401284 std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
14051349 // Save register allocation state for this function in a Constant.
14061350 if (SaveRegAllocState)
14071351 saveState();
1352 if (DEBUG_RA) { // Check our work.
1353 verifySavedState ();
1354 }
14081355
14091356 // Now update the machine code with register names and add any
14101357 // additional code inserted by the register allocator to the instruction