llvm.org GIT mirror llvm / af30b24
Merge r329673, fixing test case to use %regname instead of $regname. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@332934 91177308-0d34-0410-b5e6-96231b3b80d8 Chandler Carruth 1 year, 4 months ago
8 changed file(s) with 78 addition(s) and 53 deletion(s). Raw diff Collapse all Expand all
264264 /// @param reg - The Reg to append.
265265 static void translateRegister(MCInst &mcInst, Reg reg) {
266266 #define ENTRY(x) X86::x,
267 uint8_t llvmRegnums[] = {
268 ALL_REGS
269 0
270 };
267 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
271268 #undef ENTRY
272269
273 uint8_t llvmRegnum = llvmRegnums[reg];
270 MCPhysReg llvmRegnum = llvmRegnums[reg];
274271 mcInst.addOperand(MCOperand::createReg(llvmRegnum));
275272 }
276273
2778027780 MI.getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 : X86::PUSHF64;
2778127781 unsigned Pop = MI.getOpcode() == X86::RDFLAGS32 ? X86::POP32r : X86::POP64r;
2778227782 MachineInstr *Push = BuildMI(*BB, MI, DL, TII->get(PushF));
27783 // Permit reads of the FLAGS register without it being defined.
27783 // Permit reads of the EFLAGS and DF registers without them being defined.
2778427784 // This intrinsic exists to read external processor state in flags, such as
2778527785 // the trap flag, interrupt flag, and direction flag, none of which are
2778627786 // modeled by the backend.
27787 assert(Push->getOperand(2).getReg() == X86::EFLAGS &&
27788 "Unexpected register in operand!");
2778727789 Push->getOperand(2).setIsUndef();
27790 assert(Push->getOperand(3).getReg() == X86::DF &&
27791 "Unexpected register in operand!");
27792 Push->getOperand(3).setIsUndef();
2778827793 BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());
2778927794
2779027795 MI.eraseFromParent(); // The pseudo is gone now.
472472 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
473473 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
474474 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
475 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
475 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
476476 usesCustomInserter = 1, Uses = [ESP, SSP] in {
477477 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
478478 "# TLS_addr32",
492492 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
493493 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
494494 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
495 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
495 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS, DF],
496496 usesCustomInserter = 1, Uses = [RSP, SSP] in {
497497 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
498498 "# TLS_addr64",
508508 // For i386, the address of the thunk is passed on the stack, on return the
509509 // address of the variable is in %eax. %ecx is trashed during the function
510510 // call. All other registers are preserved.
511 let Defs = [EAX, ECX, EFLAGS],
511 let Defs = [EAX, ECX, EFLAGS, DF],
512512 Uses = [ESP, SSP],
513513 usesCustomInserter = 1 in
514514 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
521521 // %rdi. The lowering will do the right thing with RDI.
522522 // On return the address of the variable is in %rax. All other
523523 // registers are preserved.
524 let Defs = [RAX, EFLAGS],
524 let Defs = [RAX, EFLAGS, DF],
525525 Uses = [RSP, SSP],
526526 usesCustomInserter = 1 in
527527 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
93229322 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
93239323 // FIXME: Return false for x87 stack register classes for now. We can't
93249324 // allow any loads of these registers before FpGet_ST0_80.
9325 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
9326 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
9325 return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
9326 RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
9327 RC == &X86::RFP80RegClass);
93279328 }
93289329
93299330 /// Return a virtual register initialized with the
12341234
12351235 let mayLoad = 1, mayStore = 1, usesCustomInserter = 1,
12361236 SchedRW = [WriteRMW] in {
1237 let Defs = [ESP, EFLAGS], Uses = [ESP] in
1237 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in
12381238 def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src),
12391239 [(int_x86_flags_write_u32 GR32:$src)]>,
12401240 Requires<[Not64BitMode]>;
12411241
1242 let Defs = [RSP, EFLAGS], Uses = [RSP] in
1242 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
12431243 def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src),
12441244 [(int_x86_flags_write_u64 GR64:$src)]>,
12451245 Requires<[In64BitMode]>;
12461246 }
12471247
1248 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1248 let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
12491249 SchedRW = [WriteLoad] in {
12501250 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
12511251 OpSize16;
12531253 OpSize32, Requires<[Not64BitMode]>;
12541254 }
12551255
1256 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1256 let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0,
12571257 SchedRW = [WriteStore] in {
12581258 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
12591259 OpSize16;
12931293 Requires<[In64BitMode]>;
12941294 }
12951295
1296 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1296 let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
12971297 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
12981298 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1299 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1299 let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in
13001300 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
13011301 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
13021302
13811381 } // Defs = [EFLAGS]
13821382
13831383 let SchedRW = [WriteMicrocoded] in {
1384 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1385 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1384 let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in {
13861385 def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
13871386 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
13881387 def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
13931392 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
13941393 }
13951394
1396 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1397 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1395 let Defs = [EDI], Uses = [AL,EDI,DF] in
13981396 def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst),
13991397 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1400 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1398 let Defs = [EDI], Uses = [AX,EDI,DF] in
14011399 def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst),
14021400 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1403 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1401 let Defs = [EDI], Uses = [EAX,EDI,DF] in
14041402 def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst),
14051403 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1406 let Defs = [RDI], Uses = [RAX,RDI,EFLAGS] in
1404 let Defs = [RDI], Uses = [RAX,RDI,DF] in
14071405 def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst),
14081406 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
14091407
1410 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1411 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1408 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in
14121409 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
14131410 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1414 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1411 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in
14151412 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
14161413 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1417 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1414 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in
14181415 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
14191416 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1420 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1417 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in
14211418 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
14221419 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
14231420
1424 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1425 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1421 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in {
14261422 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
14271423 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
14281424 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
20692065 } // SchedRW
20702066
20712067 // Repeat string operation instruction prefixes
2072 // These use the DF flag in the EFLAGS register to inc or dec ECX
2073 let Defs = [ECX], Uses = [ECX,EFLAGS], SchedRW = [WriteMicrocoded] in {
2068 let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in {
20742069 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
20752070 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
20762071 // Repeat while not equal (used with CMPS and SCAS)
20792074
20802075 // String manipulation instructions
20812076 let SchedRW = [WriteMicrocoded] in {
2082 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
2083 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
2077 let Defs = [AL,ESI], Uses = [ESI,DF] in
20842078 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
20852079 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
2086 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
2080 let Defs = [AX,ESI], Uses = [ESI,DF] in
20872081 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
20882082 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
2089 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
2083 let Defs = [EAX,ESI], Uses = [ESI,DF] in
20902084 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
20912085 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
2092 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
2086 let Defs = [RAX,ESI], Uses = [ESI,DF] in
20932087 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
20942088 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
20952089 }
20962090
20972091 let SchedRW = [WriteSystem] in {
2098 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
2099 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
2092 let Defs = [ESI], Uses = [DX,ESI,DF] in {
21002093 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
21012094 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
21022095 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
21052098 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
21062099 }
21072100
2108 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
2109 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
2101 let Defs = [EDI], Uses = [DX,EDI,DF] in {
21102102 def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst),
21112103 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
21122104 def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst),
21162108 }
21172109 }
21182110
2119 // Flag instructions
2120 let SchedRW = [WriteALU] in {
2111 // EFLAGS management instructions.
2112 let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in {
21212113 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC_CMC_STC>;
21222114 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_CLC_CMC_STC>;
2123 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
2124 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
2115 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CLC_CMC_STC>;
2116 }
2117
2118 // DF management instructions.
2119 // FIXME: These are a bit more expensive than CLC and STC. We should consider
2120 // adjusting their schedule bucket.
2121 let SchedRW = [WriteALU], Defs = [DF] in {
21252122 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
21262123 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
2127 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CLC_CMC_STC>;
2128
2129 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
2130 }
2124 }
2125
21312126
21322127 // Table lookup instructions
21332128 let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in
692692 } // SchedRW
693693
694694 //===----------------------------------------------------------------------===//
695 // TS flag control instruction.
696 let SchedRW = [WriteSystem] in {
697 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
698 }
699
700 //===----------------------------------------------------------------------===//
701 // IF (inside EFLAGS) management instructions.
702 let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
703 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
704 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
705 }
706
707 //===----------------------------------------------------------------------===//
695708 // RDPID Instruction
696709 let SchedRW = [WriteSystem] in {
697710 def RDPID32 : I<0xC7, MRM7r, (outs GR32:$src), (ins),
250250 // Floating-point status word
251251 def FPSW : X86Reg<"fpsw", 0>;
252252
253 // Status flags register
253 // Status flags register.
254 //
255 // Note that some flags that are commonly thought of as part of the status
256 // flags register are modeled separately. Typically this is due to instructions
257 // reading and updating those flags independently of all the others. We don't
258 // want to create false dependencies between these instructions and so we use
259 // a separate register to model them.
254260 def EFLAGS : X86Reg<"flags", 0>;
261
262 // The direction flag.
263 def DF : X86Reg<"DF", 0>;
264
255265
256266 // Segment registers
257267 def CS : X86Reg<"cs", 1>;
496506 let CopyCost = -1; // Don't allow copying of status registers.
497507 let isAllocatable = 0;
498508 }
509 def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> {
510 let CopyCost = -1; // Don't allow copying of status registers.
511 let isAllocatable = 0;
512 }
499513
500514 // AVX-512 vector/mask registers.
501515 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
22 target triple = "x86_64-unknown-unknown"
33 declare void @bar1()
44 define preserve_allcc void @foo()#0 {
5 ; CHECK: foo Clobbered Registers: %cs %ds %eflags %eip %eiz %es %fpsw %fs %gs %ip %rip %riz %ss %ssp %bnd0 %bnd1 %bnd2 %bnd3 %cr0 %cr1 %cr2 %cr3 %cr4 %cr5 %cr6 %cr7 %cr8 %cr9 %cr10 %cr11 %cr12 %cr13 %cr14 %cr15 %dr0 %dr1 %dr2 %dr3 %dr4 %dr5 %dr6 %dr7 %dr8 %dr9 %dr10 %dr11 %dr12 %dr13 %dr14 %dr15 %fp0 %fp1 %fp2 %fp3 %fp4 %fp5 %fp6 %fp7 %k0 %k1 %k2 %k3 %k4 %k5 %k6 %k7 %mm0 %mm1 %mm2 %mm3 %mm4 %mm5 %mm6 %mm7 %r11 %st0 %st1 %st2 %st3 %st4 %st5 %st6 %st7 %xmm16 %xmm17 %xmm18 %xmm19 %xmm20 %xmm21 %xmm22 %xmm23 %xmm24 %xmm25 %xmm26 %xmm27 %xmm28 %xmm29 %xmm30 %xmm31 %ymm0 %ymm1 %ymm2 %ymm3 %ymm4 %ymm5 %ymm6 %ymm7 %ymm8 %ymm9 %ymm10 %ymm11 %ymm12 %ymm13 %ymm14 %ymm15 %ymm16 %ymm17 %ymm18 %ymm19 %ymm20 %ymm21 %ymm22 %ymm23 %ymm24 %ymm25 %ymm26 %ymm27 %ymm28 %ymm29 %ymm30 %ymm31 %zmm0 %zmm1 %zmm2 %zmm3 %zmm4 %zmm5 %zmm6 %zmm7 %zmm8 %zmm9 %zmm10 %zmm11 %zmm12 %zmm13 %zmm14 %zmm15 %zmm16 %zmm17 %zmm18 %zmm19 %zmm20 %zmm21 %zmm22 %zmm23 %zmm24 %zmm25 %zmm26 %zmm27 %zmm28 %zmm29 %zmm30 %zmm31 %r11b %r11d %r11w
5 ; CHECK: foo Clobbered Registers: %cs %df %ds %eflags %eip %eiz %es %fpsw %fs %gs %ip %rip %riz %ss %ssp %bnd0 %bnd1 %bnd2 %bnd3 %cr0 %cr1 %cr2 %cr3 %cr4 %cr5 %cr6 %cr7 %cr8 %cr9 %cr10 %cr11 %cr12 %cr13 %cr14 %cr15 %dr0 %dr1 %dr2 %dr3 %dr4 %dr5 %dr6 %dr7 %dr8 %dr9 %dr10 %dr11 %dr12 %dr13 %dr14 %dr15 %fp0 %fp1 %fp2 %fp3 %fp4 %fp5 %fp6 %fp7 %k0 %k1 %k2 %k3 %k4 %k5 %k6 %k7 %mm0 %mm1 %mm2 %mm3 %mm4 %mm5 %mm6 %mm7 %r11 %st0 %st1 %st2 %st3 %st4 %st5 %st6 %st7 %xmm16 %xmm17 %xmm18 %xmm19 %xmm20 %xmm21 %xmm22 %xmm23 %xmm24 %xmm25 %xmm26 %xmm27 %xmm28 %xmm29 %xmm30 %xmm31 %ymm0 %ymm1 %ymm2 %ymm3 %ymm4 %ymm5 %ymm6 %ymm7 %ymm8 %ymm9 %ymm10 %ymm11 %ymm12 %ymm13 %ymm14 %ymm15 %ymm16 %ymm17 %ymm18 %ymm19 %ymm20 %ymm21 %ymm22 %ymm23 %ymm24 %ymm25 %ymm26 %ymm27 %ymm28 %ymm29 %ymm30 %ymm31 %zmm0 %zmm1 %zmm2 %zmm3 %zmm4 %zmm5 %zmm6 %zmm7 %zmm8 %zmm9 %zmm10 %zmm11 %zmm12 %zmm13 %zmm14 %zmm15 %zmm16 %zmm17 %zmm18 %zmm19 %zmm20 %zmm21 %zmm22 %zmm23 %zmm24 %zmm25 %zmm26 %zmm27 %zmm28 %zmm29 %zmm30 %zmm31 %r11b %r11d %r11w
66 call void @bar1()
77 call void @bar2()
88 ret void