llvm.org GIT mirror llvm / af18e01
Pass DebugLoc and SDLoc by const ref. This used to be free, copying and moving DebugLocs became expensive after the metadata rewrite. Passing by reference eliminates a ton of track/untrack operations. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272512 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 3 years ago
155 changed file(s) with 2179 addition(s) and 2431 deletion(s). Raw diff Collapse all Expand all
451451
452452 /// \brief Emit an unconditional branch to the given block, unless it is the
453453 /// immediate (fall-through) successor, and update the CFG.
454 void fastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
454 void fastEmitBranch(MachineBasicBlock *MBB, const DebugLoc &DL);
455455
456456 /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
457457 /// and adds TrueMBB and FalseMBB to the successor list.
120120 /// addSafePoint - Notes the existence of a safe point. Num is the ID of the
121121 /// label just prior to the safe point (if the code generator is using
122122 /// MachineModuleInfo).
123 void addSafePoint(GC::PointKind Kind, MCSymbol *Label, DebugLoc DL) {
123 void addSafePoint(GC::PointKind Kind, MCSymbol *Label, const DebugLoc &DL) {
124124 SafePoints.emplace_back(Kind, Label, DL);
125125 }
126126
501501 /// CreateMachineInstr - Allocate a new MachineInstr. Use this instead
502502 /// of `new MachineInstr'.
503503 ///
504 MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID,
505 DebugLoc DL,
504 MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL,
506505 bool NoImp = false);
507506
508507 /// CloneMachineInstr - Create a new MachineInstr which is a copy of the
236236 };
237237
238238 /// Builder interface. Specify how to create the initial instruction itself.
239 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
240 DebugLoc DL,
239 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
241240 const MCInstrDesc &MCID) {
242241 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
243242 }
244243
245244 /// This version of the builder sets up the first operand as a
246245 /// destination virtual register.
247 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
248 DebugLoc DL,
249 const MCInstrDesc &MCID,
250 unsigned DestReg) {
246 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
247 const MCInstrDesc &MCID, unsigned DestReg) {
251248 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
252249 .addReg(DestReg, RegState::Define);
253250 }
257254 /// operand as a destination virtual register.
258255 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
259256 MachineBasicBlock::iterator I,
260 DebugLoc DL,
261 const MCInstrDesc &MCID,
257 const DebugLoc &DL, const MCInstrDesc &MCID,
262258 unsigned DestReg) {
263259 MachineFunction &MF = *BB.getParent();
264260 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
268264
269265 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
270266 MachineBasicBlock::instr_iterator I,
271 DebugLoc DL,
272 const MCInstrDesc &MCID,
267 const DebugLoc &DL, const MCInstrDesc &MCID,
273268 unsigned DestReg) {
274269 MachineFunction &MF = *BB.getParent();
275270 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
277272 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
278273 }
279274
280 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
281 MachineInstr *I,
282 DebugLoc DL,
283 const MCInstrDesc &MCID,
275 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
276 const DebugLoc &DL, const MCInstrDesc &MCID,
284277 unsigned DestReg) {
285278 if (I->isInsideBundle()) {
286279 MachineBasicBlock::instr_iterator MII(I);
296289 /// destination register.
297290 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
298291 MachineBasicBlock::iterator I,
299 DebugLoc DL,
292 const DebugLoc &DL,
300293 const MCInstrDesc &MCID) {
301294 MachineFunction &MF = *BB.getParent();
302295 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
306299
307300 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
308301 MachineBasicBlock::instr_iterator I,
309 DebugLoc DL,
302 const DebugLoc &DL,
310303 const MCInstrDesc &MCID) {
311304 MachineFunction &MF = *BB.getParent();
312305 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
314307 return MachineInstrBuilder(MF, MI);
315308 }
316309
317 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
318 MachineInstr *I,
319 DebugLoc DL,
310 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
311 const DebugLoc &DL,
320312 const MCInstrDesc &MCID) {
321313 if (I->isInsideBundle()) {
322314 MachineBasicBlock::instr_iterator MII(I);
329321
330322 /// This version of the builder inserts the newly-built instruction at the end
331323 /// of the given MachineBasicBlock, and does NOT take a destination register.
332 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
333 DebugLoc DL,
324 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
334325 const MCInstrDesc &MCID) {
335326 return BuildMI(*BB, BB->end(), DL, MCID);
336327 }
338329 /// This version of the builder inserts the newly-built instruction at the
339330 /// end of the given MachineBasicBlock, and sets up the first operand as a
340331 /// destination virtual register.
341 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
342 DebugLoc DL,
343 const MCInstrDesc &MCID,
344 unsigned DestReg) {
332 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
333 const MCInstrDesc &MCID, unsigned DestReg) {
345334 return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
346335 }
347336
349338 /// for either a value in a register or a register-indirect+offset
350339 /// address. The convention is that a DBG_VALUE is indirect iff the
351340 /// second operand is an immediate.
352 MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL,
341 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
353342 const MCInstrDesc &MCID, bool IsIndirect,
354343 unsigned Reg, unsigned Offset,
355344 const MDNode *Variable, const MDNode *Expr);
358347 /// for either a value in a register or a register-indirect+offset
359348 /// address and inserts it at position I.
360349 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
361 MachineBasicBlock::iterator I, DebugLoc DL,
350 MachineBasicBlock::iterator I, const DebugLoc &DL,
362351 const MCInstrDesc &MCID, bool IsIndirect,
363352 unsigned Reg, unsigned Offset,
364353 const MDNode *Variable, const MDNode *Expr);
473473 /// If only legal types can be produced, this does the necessary
474474 /// transformations (e.g., if the vector element type is illegal).
475475 /// @{
476 SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget = false,
477 bool isOpaque = false);
478 SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget = false,
479 bool isOpaque = false);
480 SDValue getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
476 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
481477 bool isTarget = false, bool isOpaque = false);
482 SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget = false);
483 SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT,
478 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
479 bool isTarget = false, bool isOpaque = false);
480 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
481 bool isTarget = false, bool isOpaque = false);
482 SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,
483 bool isTarget = false);
484 SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT,
484485 bool isOpaque = false) {
485486 return getConstant(Val, DL, VT, true, isOpaque);
486487 }
487 SDValue getTargetConstant(const APInt &Val, SDLoc DL, EVT VT,
488 SDValue getTargetConstant(const APInt &Val, const SDLoc &DL, EVT VT,
488489 bool isOpaque = false) {
489490 return getConstant(Val, DL, VT, true, isOpaque);
490491 }
491 SDValue getTargetConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
492 SDValue getTargetConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
492493 bool isOpaque = false) {
493494 return getConstant(Val, DL, VT, true, isOpaque);
494495 }
502503 /// The forms that take a double should only be used for simple constants
503504 /// that can be exactly represented in VT. No checks are made.
504505 /// @{
505 SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget = false);
506 SDValue getConstantFP(const APFloat& Val, SDLoc DL, EVT VT,
506 SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT,
507507 bool isTarget = false);
508 SDValue getConstantFP(const ConstantFP &CF, SDLoc DL, EVT VT,
508 SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT,
509509 bool isTarget = false);
510 SDValue getTargetConstantFP(double Val, SDLoc DL, EVT VT) {
510 SDValue getConstantFP(const ConstantFP &CF, const SDLoc &DL, EVT VT,
511 bool isTarget = false);
512 SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) {
511513 return getConstantFP(Val, DL, VT, true);
512514 }
513 SDValue getTargetConstantFP(const APFloat& Val, SDLoc DL, EVT VT) {
515 SDValue getTargetConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT) {
514516 return getConstantFP(Val, DL, VT, true);
515517 }
516 SDValue getTargetConstantFP(const ConstantFP &Val, SDLoc DL, EVT VT) {
518 SDValue getTargetConstantFP(const ConstantFP &Val, const SDLoc &DL, EVT VT) {
517519 return getConstantFP(Val, DL, VT, true);
518520 }
519521 /// @}
520522
521 SDValue getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,
523 SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,
522524 int64_t offset = 0, bool isTargetGA = false,
523525 unsigned char TargetFlags = 0);
524 SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,
526 SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,
525527 int64_t offset = 0,
526528 unsigned char TargetFlags = 0) {
527529 return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags);
558560 SDValue getBasicBlock(MachineBasicBlock *MBB);
559561 SDValue getBasicBlock(MachineBasicBlock *MBB, SDLoc dl);
560562 SDValue getExternalSymbol(const char *Sym, EVT VT);
561 SDValue getExternalSymbol(const char *Sym, SDLoc dl, EVT VT);
563 SDValue getExternalSymbol(const char *Sym, const SDLoc &dl, EVT VT);
562564 SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
563565 unsigned char TargetFlags = 0);
564566 SDValue getMCSymbol(MCSymbol *Sym, EVT VT);
566568 SDValue getValueType(EVT);
567569 SDValue getRegister(unsigned Reg, EVT VT);
568570 SDValue getRegisterMask(const uint32_t *RegMask);
569 SDValue getEHLabel(SDLoc dl, SDValue Root, MCSymbol *Label);
571 SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label);
570572 SDValue getBlockAddress(const BlockAddress *BA, EVT VT,
571573 int64_t Offset = 0, bool isTarget = false,
572574 unsigned char TargetFlags = 0);
576578 return getBlockAddress(BA, VT, Offset, true, TargetFlags);
577579 }
578580
579 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N) {
581 SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg,
582 SDValue N) {
580583 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
581584 getRegister(Reg, N.getValueType()), N);
582585 }
584587 // This version of the getCopyToReg method takes an extra operand, which
585588 // indicates that there is potentially an incoming glue value (if Glue is not
586589 // null) and that there should be a glue result.
587 SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N,
590 SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N,
588591 SDValue Glue) {
589592 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
590593 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
593596 }
594597
595598 // Similar to last getCopyToReg() except parameter Reg is a SDValue
596 SDValue getCopyToReg(SDValue Chain, SDLoc dl, SDValue Reg, SDValue N,
597 SDValue Glue) {
599 SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N,
600 SDValue Glue) {
598601 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
599602 SDValue Ops[] = { Chain, Reg, N, Glue };
600603 return getNode(ISD::CopyToReg, dl, VTs,
601604 makeArrayRef(Ops, Glue.getNode() ? 4 : 3));
602605 }
603606
604 SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) {
607 SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) {
605608 SDVTList VTs = getVTList(VT, MVT::Other);
606609 SDValue Ops[] = { Chain, getRegister(Reg, VT) };
607610 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
610613 // This version of the getCopyFromReg method takes an extra operand, which
611614 // indicates that there is potentially an incoming glue value (if Glue is not
612615 // null) and that there should be a glue result.
613 SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT,
614 SDValue Glue) {
616 SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT,
617 SDValue Glue) {
615618 SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
616619 SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };
617620 return getNode(ISD::CopyFromReg, dl, VTs,
622625
623626 /// Returns the ConvertRndSat Note: Avoid using this node because it may
624627 /// disappear in the future and most targets don't support it.
625 SDValue getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy,
626 SDValue STy,
627 SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
628 SDValue getConvertRndSat(EVT VT, const SDLoc &dl, SDValue Val, SDValue DTy,
629 SDValue STy, SDValue Rnd, SDValue Sat,
630 ISD::CvtCode Code);
628631
629632 /// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT,
630633 /// which must be a vector type, must match the number of mask elements
631634 /// NumElts. An integer mask element equal to -1 is treated as undefined.
632 SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
635 SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
633636 const int *MaskElts);
634 SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
637 SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
635638 ArrayRef MaskElts) {
636639 assert(VT.getVectorNumElements() == MaskElts.size() &&
637640 "Must have the same number of vector elements as mask elements!");
642645 /// which must be a vector type, must match the number of operands in Ops.
643646 /// The operands must have the same type as (or, for integers, a type wider
644647 /// than) VT's element type.
645 SDValue getBuildVector(EVT VT, SDLoc DL, ArrayRef Ops) {
648 SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef Ops) {
646649 // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
647650 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
648651 }
650653 /// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all
651654 /// elements. VT must be a vector type. Op's type must be the same as (or,
652655 /// for integers, a type wider than) VT's element type.
653 SDValue getSplatBuildVector(EVT VT, SDLoc DL, SDValue Op) {
656 SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) {
654657 // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
655658 if (Op.getOpcode() == ISD::UNDEF) {
656659 assert((VT.getVectorElementType() == Op.getValueType() ||
678681
679682 /// Convert Op, which must be of integer type, to the
680683 /// integer type VT, by either any-extending or truncating it.
681 SDValue getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
684 SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
682685
683686 /// Convert Op, which must be of integer type, to the
684687 /// integer type VT, by either sign-extending or truncating it.
685 SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
688 SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
686689
687690 /// Convert Op, which must be of integer type, to the
688691 /// integer type VT, by either zero-extending or truncating it.
689 SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
692 SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
690693
691694 /// Return the expression required to zero extend the Op
692695 /// value assuming it was the smaller SrcTy value.
693 SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy);
696 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy);
694697
695698 /// Return an operation which will any-extend the low lanes of the operand
696699 /// into the specified vector type. For example,
697700 /// this can convert a v16i8 into a v4i32 by any-extending the low four
698701 /// lanes of the operand from i8 to i32.
699 SDValue getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);
702 SDValue getAnyExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
700703
701704 /// Return an operation which will sign extend the low lanes of the operand
702705 /// into the specified vector type. For example,
703706 /// this can convert a v16i8 into a v4i32 by sign extending the low four
704707 /// lanes of the operand from i8 to i32.
705 SDValue getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);
708 SDValue getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
706709
707710 /// Return an operation which will zero extend the low lanes of the operand
708711 /// into the specified vector type. For example,
709712 /// this can convert a v16i8 into a v4i32 by zero extending the low four
710713 /// lanes of the operand from i8 to i32.
711 SDValue getZeroExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);
714 SDValue getZeroExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
712715
713716 /// Convert Op, which must be of integer type, to the integer type VT,
714717 /// by using an extension appropriate for the target's
715718 /// BooleanContent for type OpVT or truncating it.
716 SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT);
719 SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT);
717720
718721 /// Create a bitwise NOT operation as (XOR Val, -1).
719 SDValue getNOT(SDLoc DL, SDValue Val, EVT VT);
722 SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);
720723
721724 /// \brief Create a logical NOT operation as (XOR Val, BooleanOne).
722 SDValue getLogicalNOT(SDLoc DL, SDValue Val, EVT VT);
725 SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);
723726
724727 /// Return a new CALLSEQ_START node, which always must have a glue result
725728 /// (to ensure it's not CSE'd). CALLSEQ_START does not have a useful SDLoc.
726 SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL) {
729 SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL) {
727730 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
728731 SDValue Ops[] = { Chain, Op };
729732 return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
733736 /// glue result (to ensure it's not CSE'd).
734737 /// CALLSEQ_END does not have a useful SDLoc.
735738 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
736 SDValue InGlue, SDLoc DL) {
739 SDValue InGlue, const SDLoc &DL) {
737740 SDVTList NodeTys = getVTList(MVT::Other, MVT::Glue);
738741 SmallVector Ops;
739742 Ops.push_back(Chain);
756759
757760 /// Gets or creates the specified node.
758761 ///
759 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
762 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
760763 ArrayRef Ops);
761 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
764 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
762765 ArrayRef Ops, const SDNodeFlags *Flags = nullptr);
763 SDValue getNode(unsigned Opcode, SDLoc DL, ArrayRef ResultTys,
766 SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef ResultTys,
764767 ArrayRef Ops);
765 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
768 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,
766769 ArrayRef Ops);
767770
768771 // Specialize based on number of operands.
769 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);
770 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);
771 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
772 const SDNodeFlags *Flags = nullptr);
773 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
774 SDValue N3);
775 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
776 SDValue N3, SDValue N4);
777 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
778 SDValue N3, SDValue N4, SDValue N5);
772 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
773 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N);
774 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
775 SDValue N2, const SDNodeFlags *Flags = nullptr);
776 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
777 SDValue N2, SDValue N3);
778 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
779 SDValue N2, SDValue N3, SDValue N4);
780 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
781 SDValue N2, SDValue N3, SDValue N4, SDValue N5);
779782
780783 // Specialize again based on number of operands for nodes with a VTList
781784 // rather than a single VT.
782 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs);
783 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N);
784 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
785 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs);
786 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N);
787 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
785788 SDValue N2);
786 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
789 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
787790 SDValue N2, SDValue N3);
788 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
791 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
789792 SDValue N2, SDValue N3, SDValue N4);
790 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
793 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
791794 SDValue N2, SDValue N3, SDValue N4, SDValue N5);
792795
793796 /// Compute a TokenFactor to force all the incoming stack arguments to be
795798 /// stack arguments from being clobbered.
796799 SDValue getStackArgumentTokenFactor(SDValue Chain);
797800
798 SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
801 SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
799802 SDValue Size, unsigned Align, bool isVol, bool AlwaysInline,
800803 bool isTailCall, MachinePointerInfo DstPtrInfo,
801804 MachinePointerInfo SrcPtrInfo);
802805
803 SDValue getMemmove(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
806 SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
804807 SDValue Size, unsigned Align, bool isVol, bool isTailCall,
805808 MachinePointerInfo DstPtrInfo,
806809 MachinePointerInfo SrcPtrInfo);
807810
808 SDValue getMemset(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
811 SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
809812 SDValue Size, unsigned Align, bool isVol, bool isTailCall,
810813 MachinePointerInfo DstPtrInfo);
811814
812815 /// Helper function to make it easier to build SetCC's if you just
813816 /// have an ISD::CondCode instead of an SDValue.
814817 ///
815 SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,
818 SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS,
816819 ISD::CondCode Cond) {
817820 assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&
818821 "Cannot compare scalars to vectors");
825828
826829 /// Helper function to make it easier to build Select's if you just
827830 /// have operands and don't want to check for vector.
828 SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond,
829 SDValue LHS, SDValue RHS) {
831 SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS,
832 SDValue RHS) {
830833 assert(LHS.getValueType() == RHS.getValueType() &&
831834 "Cannot use select on differing types");
832835 assert(VT.isVector() == LHS.getValueType().isVector() &&
838841 /// Helper function to make it easier to build SelectCC's if you
839842 /// just have an ISD::CondCode instead of an SDValue.
840843 ///
841 SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS,
842 SDValue True, SDValue False, ISD::CondCode Cond) {
844 SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True,
845 SDValue False, ISD::CondCode Cond) {
843846 return getNode(ISD::SELECT_CC, DL, True.getValueType(),
844847 LHS, RHS, True, False, getCondCode(Cond));
845848 }
846849
847850 /// VAArg produces a result and token chain, and takes a pointer
848851 /// and a source value as input.
849 SDValue getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
852 SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
850853 SDValue SV, unsigned Align);
851854
852855 /// Gets a node for an atomic cmpxchg op. There are two
853856 /// valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a
854857 /// chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded,
855858 /// a success flag (initially i1), and a chain.
856 SDValue getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs,
857 SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp,
858 MachinePointerInfo PtrInfo, unsigned Alignment,
859 SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
860 SDVTList VTs, SDValue Chain, SDValue Ptr,
861 SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo,
862 unsigned Alignment, AtomicOrdering SuccessOrdering,
863 AtomicOrdering FailureOrdering,
864 SynchronizationScope SynchScope);
865 SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
866 SDVTList VTs, SDValue Chain, SDValue Ptr,
867 SDValue Cmp, SDValue Swp, MachineMemOperand *MMO,
859868 AtomicOrdering SuccessOrdering,
860869 AtomicOrdering FailureOrdering,
861870 SynchronizationScope SynchScope);
862 SDValue getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs,
863 SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp,
864 MachineMemOperand *MMO,
865 AtomicOrdering SuccessOrdering,
866 AtomicOrdering FailureOrdering,
867 SynchronizationScope SynchScope);
868871
869872 /// Gets a node for an atomic op, produces result (if relevant)
870873 /// and chain and takes 2 operands.
871 SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,
874 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,
872875 SDValue Ptr, SDValue Val, const Value *PtrVal,
873876 unsigned Alignment, AtomicOrdering Ordering,
874877 SynchronizationScope SynchScope);
875 SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,
878 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,
876879 SDValue Ptr, SDValue Val, MachineMemOperand *MMO,
877 AtomicOrdering Ordering,
878 SynchronizationScope SynchScope);
880 AtomicOrdering Ordering, SynchronizationScope SynchScope);
879881
880882 /// Gets a node for an atomic op, produces result and chain and
881883 /// takes 1 operand.
882 SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT,
884 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT,
883885 SDValue Chain, SDValue Ptr, MachineMemOperand *MMO,
884 AtomicOrdering Ordering,
885 SynchronizationScope SynchScope);
886 AtomicOrdering Ordering, SynchronizationScope SynchScope);
886887
887888 /// Gets a node for an atomic op, produces result and chain and takes N
888889 /// operands.
889 SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList,
890 ArrayRef Ops, MachineMemOperand *MMO,
891 AtomicOrdering SuccessOrdering,
890 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
891 SDVTList VTList, ArrayRef Ops,
892 MachineMemOperand *MMO, AtomicOrdering SuccessOrdering,
892893 AtomicOrdering FailureOrdering,
893894 SynchronizationScope SynchScope);
894 SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList,
895 ArrayRef Ops, MachineMemOperand *MMO,
896 AtomicOrdering Ordering, SynchronizationScope SynchScope);
895 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
896 SDVTList VTList, ArrayRef Ops,
897 MachineMemOperand *MMO, AtomicOrdering Ordering,
898 SynchronizationScope SynchScope);
897899
898900 /// Creates a MemIntrinsicNode that may produce a
899901 /// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
900902 /// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
901903 /// less than FIRST_TARGET_MEMORY_OPCODE.
902 SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,
903 ArrayRef Ops,
904 EVT MemVT, MachinePointerInfo PtrInfo,
905 unsigned Align = 0, bool Vol = false,
906 bool ReadMem = true, bool WriteMem = true,
907 unsigned Size = 0);
908
909 SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,
910 ArrayRef Ops,
911 EVT MemVT, MachineMemOperand *MMO);
904 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
905 ArrayRef Ops, EVT MemVT,
906 MachinePointerInfo PtrInfo, unsigned Align = 0,
907 bool Vol = false, bool ReadMem = true,
908 bool WriteMem = true, unsigned Size = 0);
909
910 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
911 ArrayRef Ops, EVT MemVT,
912 MachineMemOperand *MMO);
912913
913914 /// Create a MERGE_VALUES node from the given operands.
914 SDValue getMergeValues(ArrayRef Ops, SDLoc dl);
915 SDValue getMergeValues(ArrayRef Ops, const SDLoc &dl);
915916
916917 /// Loads are not normal binary operators: their result type is not
917918 /// determined by their operands, and they produce a value AND a token chain.
918919 ///
919 SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
920 SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
920921 MachinePointerInfo PtrInfo, bool isVolatile,
921922 bool isNonTemporal, bool isInvariant, unsigned Alignment,
922923 const AAMDNodes &AAInfo = AAMDNodes(),
923924 const MDNode *Ranges = nullptr);
924 SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
925 SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
925926 MachineMemOperand *MMO);
926 SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
927 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
927928 SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo,
928 EVT MemVT, bool isVolatile,
929 bool isNonTemporal, bool isInvariant, unsigned Alignment,
929 EVT MemVT, bool isVolatile, bool isNonTemporal,
930 bool isInvariant, unsigned Alignment,
930931 const AAMDNodes &AAInfo = AAMDNodes());
931 SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
932 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
932933 SDValue Chain, SDValue Ptr, EVT MemVT,
933934 MachineMemOperand *MMO);
934 SDValue getIndexedLoad(SDValue OrigLoad, SDLoc dl, SDValue Base,
935 SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base,
935936 SDValue Offset, ISD::MemIndexedMode AM);
936 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
937 EVT VT, SDLoc dl,
938 SDValue Chain, SDValue Ptr, SDValue Offset,
939 MachinePointerInfo PtrInfo, EVT MemVT,
940 bool isVolatile, bool isNonTemporal, bool isInvariant,
941 unsigned Alignment, const AAMDNodes &AAInfo = AAMDNodes(),
937 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
938 const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,
939 MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile,
940 bool isNonTemporal, bool isInvariant, unsigned Alignment,
941 const AAMDNodes &AAInfo = AAMDNodes(),
942942 const MDNode *Ranges = nullptr);
943 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
944 EVT VT, SDLoc dl,
945 SDValue Chain, SDValue Ptr, SDValue Offset,
943 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
944 const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,
946945 EVT MemVT, MachineMemOperand *MMO);
947946
948947 /// Helper function to build ISD::STORE nodes.
949 SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
948 SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
950949 MachinePointerInfo PtrInfo, bool isVolatile,
951950 bool isNonTemporal, unsigned Alignment,
952951 const AAMDNodes &AAInfo = AAMDNodes());
953 SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
952 SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
954953 MachineMemOperand *MMO);
955 SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
956 MachinePointerInfo PtrInfo, EVT TVT,
957 bool isNonTemporal, bool isVolatile,
958 unsigned Alignment,
954 SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
955 SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT,
956 bool isNonTemporal, bool isVolatile, unsigned Alignment,
959957 const AAMDNodes &AAInfo = AAMDNodes());
960 SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
961 EVT TVT, MachineMemOperand *MMO);
962 SDValue getIndexedStore(SDValue OrigStoe, SDLoc dl, SDValue Base,
958 SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
959 SDValue Ptr, EVT TVT, MachineMemOperand *MMO);
960 SDValue getIndexedStore(SDValue OrigStoe, const SDLoc &dl, SDValue Base,
963961 SDValue Offset, ISD::MemIndexedMode AM);
964962
965963 /// Returns sum of the base pointer and offset.
966 SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SDLoc DL);
967
968 SDValue getMaskedLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
964 SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, const SDLoc &DL);
965
966 SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
969967 SDValue Mask, SDValue Src0, EVT MemVT,
970968 MachineMemOperand *MMO, ISD::LoadExtType);
971 SDValue getMaskedStore(SDValue Chain, SDLoc dl, SDValue Val,
969 SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val,
972970 SDValue Ptr, SDValue Mask, EVT MemVT,
973971 MachineMemOperand *MMO, bool IsTrunc);
974 SDValue getMaskedGather(SDVTList VTs, EVT VT, SDLoc dl,
972 SDValue getMaskedGather(SDVTList VTs, EVT VT, const SDLoc &dl,
975973 ArrayRef Ops, MachineMemOperand *MMO);
976 SDValue getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl,
974 SDValue getMaskedScatter(SDVTList VTs, EVT VT, const SDLoc &dl,
977975 ArrayRef Ops, MachineMemOperand *MMO);
978976 /// Construct a node to track a Value* through the backend.
979977 SDValue getSrcValue(const Value *v);
986984 SDValue getBitcast(EVT VT, SDValue V);
987985
988986 /// Return an AddrSpaceCastSDNode.
989 SDValue getAddrSpaceCast(SDLoc dl, EVT VT, SDValue Ptr,
990 unsigned SrcAS, unsigned DestAS);
987 SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS,
988 unsigned DestAS);
991989
992990 /// Return the specified value casted to
993991 /// the target's desired shift amount type.
10561054 /// Note that getMachineNode returns the resultant node. If there is already
10571055 /// a node of the specified opcode and operands, it returns that node instead
10581056 /// of the current one.
1059 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT);
1060 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
1057 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT);
1058 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
10611059 SDValue Op1);
1062 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
1060 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
10631061 SDValue Op1, SDValue Op2);
1064 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
1062 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
10651063 SDValue Op1, SDValue Op2, SDValue Op3);
1066 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
1064 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
10671065 ArrayRef Ops);
1068 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2);
1069 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,
1070 SDValue Op1);
1071 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,
1072 SDValue Op1, SDValue Op2);
1073 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,
1074 SDValue Op1, SDValue Op2, SDValue Op3);
1075 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,
1066 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1067 EVT VT2);
1068 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1069 EVT VT2, SDValue Op1);
1070 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1071 EVT VT2, SDValue Op1, SDValue Op2);
1072 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1073 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1074 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1075 EVT VT2, ArrayRef Ops);
1076 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1077 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2);
1078 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1079 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2,
1080 SDValue Op3);
1081 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1082 EVT VT2, EVT VT3, ArrayRef Ops);
1083 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1084 EVT VT2, EVT VT3, EVT VT4,
10761085 ArrayRef Ops);
1077 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,
1078 EVT VT3, SDValue Op1, SDValue Op2);
1079 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,
1080 EVT VT3, SDValue Op1, SDValue Op2,
1081 SDValue Op3);
1082 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,
1083 EVT VT3, ArrayRef Ops);
1084 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,
1085 EVT VT3, EVT VT4, ArrayRef Ops);
1086 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl,
1087 ArrayRef ResultTys,
1086 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl,
1087 ArrayRef ResultTys, ArrayRef Ops);
1088 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, SDVTList VTs,
10881089 ArrayRef Ops);
1089 MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, SDVTList VTs,
1090 ArrayRef Ops);
10911090
10921091 /// A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
1093 SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT,
1092 SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
10941093 SDValue Operand);
10951094
10961095 /// A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
1097 SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT,
1096 SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
10981097 SDValue Operand, SDValue Subreg);
10991098
11001099 /// Get the specified node if it's already available, or else return NULL.
11031102
11041103 /// Creates a SDDbgValue node.
11051104 SDDbgValue *getDbgValue(MDNode *Var, MDNode *Expr, SDNode *N, unsigned R,
1106 bool IsIndirect, uint64_t Off, DebugLoc DL,
1105 bool IsIndirect, uint64_t Off, const DebugLoc &DL,
11071106 unsigned O);
11081107
11091108 /// Constant
11101109 SDDbgValue *getConstantDbgValue(MDNode *Var, MDNode *Expr, const Value *C,
1111 uint64_t Off, DebugLoc DL, unsigned O);
1110 uint64_t Off, const DebugLoc &DL, unsigned O);
11121111
11131112 /// FrameIndex
11141113 SDDbgValue *getFrameIndexDbgValue(MDNode *Var, MDNode *Expr, unsigned FI,
1115 uint64_t Off, DebugLoc DL, unsigned O);
1114 uint64_t Off, const DebugLoc &DL,
1115 unsigned O);
11161116
11171117 /// Remove the specified node from the system. If any of its
11181118 /// operands then becomes dead, remove them as well. Inform UpdateListener
12511251 const GlobalAddressSDNode *GA,
12521252 const SDNode *N2);
12531253
1254 SDValue FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
1254 SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
12551255 SDNode *Cst1, SDNode *Cst2);
12561256
1257 SDValue FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
1257 SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
12581258 const ConstantSDNode *Cst1,
12591259 const ConstantSDNode *Cst2);
12601260
1261 SDValue FoldConstantVectorArithmetic(unsigned Opcode, SDLoc DL,
1262 EVT VT, ArrayRef Ops,
1261 SDValue FoldConstantVectorArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
1262 ArrayRef Ops,
12631263 const SDNodeFlags *Flags = nullptr);
12641264
12651265 /// Constant fold a setcc to true or false.
1266 SDValue FoldSetCC(EVT VT, SDValue N1,
1267 SDValue N2, ISD::CondCode Cond, SDLoc dl);
1266 SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond,
1267 const SDLoc &dl);
12681268
12691269 /// Return true if the sign bit of Op is known to be zero.
12701270 /// We use this predicate to simplify operations downstream.
13881388
13891389 void allnodes_clear();
13901390
1391 SDNode *GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
1392 SDValue N2, const SDNodeFlags *Flags = nullptr);
1391 SDNode *GetBinarySDNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,
1392 SDValue N1, SDValue N2,
1393 const SDNodeFlags *Flags = nullptr);
13931394
13941395 /// Look up the node specified by ID in CSEMap. If it exists, return it. If
13951396 /// not, return the insertion token that will make insertion faster. This
14001401 /// Look up the node specified by ID in CSEMap. If it exists, return it. If
14011402 /// not, return the insertion token that will make insertion faster. Performs
14021403 /// additional processing for constant nodes.
1403 SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, SDLoc DL,
1404 SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, const SDLoc &DL,
14041405 void *&InsertPos);
14051406
14061407 /// List of non-single value types.
209209
210210 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
211211 /// by tblgen. Others should not call it.
212 void SelectInlineAsmMemoryOperands(std::vector &Ops, SDLoc DL);
213
212 void SelectInlineAsmMemoryOperands(std::vector &Ops,
213 const SDLoc &DL);
214214
215215 public:
216216 // Calls to these predicates are generated by tblgen.
846846 if (I)
847847 DL = I->getDebugLoc();
848848 }
849 unsigned getIROrder() { return IROrder; }
850 DebugLoc getDebugLoc() { return DL; }
849 unsigned getIROrder() const { return IROrder; }
850 const DebugLoc &getDebugLoc() const { return DL; }
851851 };
852852
853853
951951 class BinaryWithFlagsSDNode : public SDNode {
952952 public:
953953 SDNodeFlags Flags;
954 BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
955 const SDNodeFlags &NodeFlags)
954 BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
955 SDVTList VTs, const SDNodeFlags &NodeFlags)
956956 : SDNode(Opc, Order, dl, VTs), Flags(NodeFlags) {}
957957 static bool classof(const SDNode *N) {
958958 return isBinOpWithFlags(N->getOpcode());
991991 unsigned DestAddrSpace;
992992
993993 public:
994 AddrSpaceCastSDNode(unsigned Order, DebugLoc dl, EVT VT, unsigned SrcAS,
995 unsigned DestAS);
994 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
995 unsigned SrcAS, unsigned DestAS);
996996
997997 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
998998 unsigned getDestAddressSpace() const { return DestAddrSpace; }
10131013 MachineMemOperand *MMO;
10141014
10151015 public:
1016 MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
1016 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
10171017 EVT MemoryVT, MachineMemOperand *MMO);
10181018
10191019 bool readMem() const { return MMO->isLoad(); }
11451145 }
11461146
11471147 public:
1148 AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL,
1148 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
11491149 EVT MemVT, MachineMemOperand *MMO,
11501150 AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering,
11511151 SynchronizationScope SynchScope)
11971197 /// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
11981198 class MemIntrinsicSDNode : public MemSDNode {
11991199 public:
1200 MemIntrinsicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
1201 EVT MemoryVT, MachineMemOperand *MMO)
1200 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1201 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
12021202 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
12031203 SubclassData |= 1u << 13;
12041204 }
12271227 const int *Mask;
12281228 protected:
12291229 friend class SelectionDAG;
1230 ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, const int *M)
1230 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
12311231 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
12321232
12331233 public:
12761276 const ConstantInt *Value;
12771277 friend class SelectionDAG;
12781278 ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val,
1279 DebugLoc DL, EVT VT)
1280 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
1281 0, DL, getSDVTList(VT)), Value(val) {
1279 const DebugLoc &DL, EVT VT)
1280 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DL,
1281 getSDVTList(VT)),
1282 Value(val) {
12821283 SubclassData |= (uint16_t)isOpaque;
12831284 }
12841285 public:
13031304 class ConstantFPSDNode : public SDNode {
13041305 const ConstantFP *Value;
13051306 friend class SelectionDAG;
1306 ConstantFPSDNode(bool isTarget, const ConstantFP *val, DebugLoc DL, EVT VT)
1307 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
1308 0, DL, getSDVTList(VT)), Value(val) {
1309 }
1307 ConstantFPSDNode(bool isTarget, const ConstantFP *val, const DebugLoc &DL,
1308 EVT VT)
1309 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0, DL,
1310 getSDVTList(VT)),
1311 Value(val) {}
1312
13101313 public:
13111314
13121315 const APFloat& getValueAPF() const { return Value->getValueAPF(); }
13661369 int64_t Offset;
13671370 unsigned char TargetFlags;
13681371 friend class SelectionDAG;
1369 GlobalAddressSDNode(unsigned Opc, unsigned Order, DebugLoc DL,
1372 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
13701373 const GlobalValue *GA, EVT VT, int64_t o,
13711374 unsigned char TargetFlags);
1375
13721376 public:
13731377
13741378 const GlobalValue *getGlobal() const { return TheGlobal; }
16661670 class EHLabelSDNode : public SDNode {
16671671 MCSymbol *Label;
16681672 friend class SelectionDAG;
1669 EHLabelSDNode(unsigned Order, DebugLoc dl, MCSymbol *L)
1673 EHLabelSDNode(unsigned Order, const DebugLoc &dl, MCSymbol *L)
16701674 : SDNode(ISD::EH_LABEL, Order, dl, getSDVTList(MVT::Other)), Label(L) {}
16711675
16721676 public:
17331737 class CvtRndSatSDNode : public SDNode {
17341738 ISD::CvtCode CvtCode;
17351739 friend class SelectionDAG;
1736 explicit CvtRndSatSDNode(EVT VT, unsigned Order, DebugLoc dl,
1740 explicit CvtRndSatSDNode(EVT VT, unsigned Order, const DebugLoc &dl,
17371741 ISD::CvtCode Code)
17381742 : SDNode(ISD::CONVERT_RNDSAT, Order, dl, getSDVTList(VT)), CvtCode(Code) {
17391743 }
17671771 /// Base class for LoadSDNode and StoreSDNode
17681772 class LSBaseSDNode : public MemSDNode {
17691773 public:
1770 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, DebugLoc dl,
1774 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
17711775 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
17721776 MachineMemOperand *MMO)
1773 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
1777 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
17741778 SubclassData |= AM << 2;
17751779 assert(getAddressingMode() == AM && "MemIndexedMode encoding error!");
17761780 }
18001804 /// This class is used to represent ISD::LOAD nodes.
18011805 class LoadSDNode : public LSBaseSDNode {
18021806 friend class SelectionDAG;
1803 LoadSDNode(unsigned Order, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM,
1804 ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO)
1807 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1808 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1809 MachineMemOperand *MMO)
18051810 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
18061811 SubclassData |= (unsigned short)ETy;
18071812 assert(getExtensionType() == ETy && "LoadExtType encoding error!");
18271832 /// This class is used to represent ISD::STORE nodes.
18281833 class StoreSDNode : public LSBaseSDNode {
18291834 friend class SelectionDAG;
1830 StoreSDNode(unsigned Order, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM,
1831 bool isTrunc, EVT MemVT, MachineMemOperand *MMO)
1835 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1836 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
1837 MachineMemOperand *MMO)
18321838 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
18331839 SubclassData |= (unsigned short)isTrunc;
18341840 assert(isTruncatingStore() == isTrunc && "isTrunc encoding error!");
18551861 class MaskedLoadStoreSDNode : public MemSDNode {
18561862 public:
18571863 friend class SelectionDAG;
1858 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order, DebugLoc dl,
1859 SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1864 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
1865 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1866 MachineMemOperand *MMO)
18601867 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {}
18611868
18621869 // In the both nodes address is Op1, mask is Op2:
18761883 class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
18771884 public:
18781885 friend class SelectionDAG;
1879 MaskedLoadSDNode(unsigned Order, DebugLoc dl, SDVTList VTs,
1886 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
18801887 ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO)
18811888 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, MemVT, MMO) {
18821889 SubclassData |= (unsigned short)ETy;
18961903
18971904 public:
18981905 friend class SelectionDAG;
1899 MaskedStoreSDNode(unsigned Order, DebugLoc dl, SDVTList VTs, bool isTrunc,
1900 EVT MemVT, MachineMemOperand *MMO)
1906 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1907 bool isTrunc, EVT MemVT, MachineMemOperand *MMO)
19011908 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, MemVT, MMO) {
19021909 SubclassData |= (unsigned short)isTrunc;
19031910 }
19191926 class MaskedGatherScatterSDNode : public MemSDNode {
19201927 public:
19211928 friend class SelectionDAG;
1922 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order, DebugLoc dl,
1923 SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1929 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
1930 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1931 MachineMemOperand *MMO)
19241932 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {}
19251933
19261934 // In the both nodes address is Op1, mask is Op2:
19431951 class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
19441952 public:
19451953 friend class SelectionDAG;
1946 MaskedGatherSDNode(unsigned Order, DebugLoc dl, SDVTList VTs, EVT MemVT,
1947 MachineMemOperand *MMO)
1954 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1955 EVT MemVT, MachineMemOperand *MMO)
19481956 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO) {}
19491957
19501958 static bool classof(const SDNode *N) {
19581966
19591967 public:
19601968 friend class SelectionDAG;
1961 MaskedScatterSDNode(unsigned Order, DebugLoc dl, SDVTList VTs, EVT MemVT,
1962 MachineMemOperand *MMO)
1969 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1970 EVT MemVT, MachineMemOperand *MMO)
19631971 : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO) {}
19641972
19651973 static bool classof(const SDNode *N) {
19761984
19771985 private:
19781986 friend class SelectionDAG;
1979 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc DL, SDVTList VTs)
1980 : SDNode(Opc, Order, DL, VTs), MemRefs(nullptr), MemRefsEnd(nullptr) {}
1987 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
1988 : SDNode(Opc, Order, DL, VTs), MemRefs(nullptr), MemRefsEnd(nullptr) {}
19811989
19821990 /// Memory reference descriptions for this instruction.
19831991 mmo_iterator MemRefs;
4545 /// expanded in a place where calls are not feasible (e.g. within the prologue
4646 /// for another call). If the target chooses to decline an AlwaysInline
4747 /// request here, legalize will resort to using simple loads and stores.
48 virtual SDValue EmitTargetCodeForMemcpy(
49 SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2,
50 SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline,
51 MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
48 virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
49 SDValue Chain, SDValue Op1,
50 SDValue Op2, SDValue Op3,
51 unsigned Align, bool isVolatile,
52 bool AlwaysInline,
53 MachinePointerInfo DstPtrInfo,
54 MachinePointerInfo SrcPtrInfo) const {
5255 return SDValue();
5356 }
5457
5962 /// SDValue if the target declines to use custom code and a different
6063 /// lowering strategy should be used.
6164 virtual SDValue EmitTargetCodeForMemmove(
62 SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2,
63 SDValue Op3, unsigned Align, bool isVolatile,
65 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1,
66 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile,
6467 MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
6568 return SDValue();
6669 }
7174 /// efficient than using a library call. This function can return a null
7275 /// SDValue if the target declines to use custom code and a different
7376 /// lowering strategy should be used.
74 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
77 virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
7578 SDValue Chain, SDValue Op1,
7679 SDValue Op2, SDValue Op3,
7780 unsigned Align, bool isVolatile,
8487 /// memcmp and the second is the chain. Both SDValues can be null if a normal
8588 /// libcall should be used.
8689 virtual std::pair
87 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl, SDValue Chain,
90 EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
8891 SDValue Op1, SDValue Op2, SDValue Op3,
8992 MachinePointerInfo Op1PtrInfo,
9093 MachinePointerInfo Op2PtrInfo) const {
9699 /// memchr and the second is the chain. Both SDValues can be null if a normal
97100 /// libcall should be used.
98101 virtual std::pair
99 EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc dl, SDValue Chain,
102 EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
100103 SDValue Src, SDValue Char, SDValue Length,
101104 MachinePointerInfo SrcPtrInfo) const {
102105 return std::make_pair(SDValue(), SDValue());
109112 /// for stpcpy) and the second is the chain. Both SDValues can be null
110113 /// if a normal libcall should be used.
111114 virtual std::pair
112 EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
115 EmitTargetCodeForStrcpy(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
113116 SDValue Dest, SDValue Src,
114117 MachinePointerInfo DestPtrInfo,
115118 MachinePointerInfo SrcPtrInfo, bool isStpcpy) const {
120123 /// faster than a libcall.
121124 /// The first returned SDValue is the result of the strcmp and the second is
122125 /// the chain. Both SDValues can be null if a normal libcall should be used.
123 virtual std::pair EmitTargetCodeForStrcmp(
124 SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2,
125 MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const {
126 virtual std::pair
127 EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain,
128 SDValue Op1, SDValue Op2,
129 MachinePointerInfo Op1PtrInfo,
130 MachinePointerInfo Op2PtrInfo) const {
126131 return std::make_pair(SDValue(), SDValue());
127132 }
128133
129134 virtual std::pair
130 EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
135 EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
131136 SDValue Src, MachinePointerInfo SrcPtrInfo) const {
132137 return std::make_pair(SDValue(), SDValue());
133138 }
134139
135140 virtual std::pair
136 EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
141 EmitTargetCodeForStrnlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain,
137142 SDValue Src, SDValue MaxLength,
138143 MachinePointerInfo SrcPtrInfo) const {
139144 return std::make_pair(SDValue(), SDValue());
541541 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
542542 MachineBasicBlock *FBB,
543543 ArrayRef Cond,
544 DebugLoc DL) const {
544 const DebugLoc &DL) const {
545545 llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
546546 }
547547
688688 /// @param TrueReg Virtual register to copy when Cond is true.
689689 /// @param FalseReg Virtual register to copy when Cons is false.
690690 virtual void insertSelect(MachineBasicBlock &MBB,
691 MachineBasicBlock::iterator I, DebugLoc DL,
691 MachineBasicBlock::iterator I, const DebugLoc &DL,
692692 unsigned DstReg, ArrayRef Cond,
693693 unsigned TrueReg, unsigned FalseReg) const {
694694 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
751751 /// careful implementation when multiple copy instructions are required for
752752 /// large registers. See for example the ARM target.
753753 virtual void copyPhysReg(MachineBasicBlock &MBB,
754 MachineBasicBlock::iterator MI, DebugLoc DL,
754 MachineBasicBlock::iterator MI, const DebugLoc &DL,
755755 unsigned DestReg, unsigned SrcReg,
756756 bool KillSrc) const {
757757 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
22062206 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
22072207 SDValue &Chain) const;
22082208
2209 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2210 SDValue &NewLHS, SDValue &NewRHS,
2211 ISD::CondCode &CCCode, SDLoc DL) const;
2209 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2210 SDValue &NewRHS, ISD::CondCode &CCCode,
2211 const SDLoc &DL) const;
22122212
22132213 /// Returns a pair of (return value, chain).
22142214 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
22152215 std::pair makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
22162216 EVT RetVT, ArrayRef Ops,
2217 bool isSigned, SDLoc dl,
2217 bool isSigned, const SDLoc &dl,
22182218 bool doesNotReturn = false,
22192219 bool isReturnValueUsed = true) const;
22202220
22632263 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
22642264 /// generalized for targets with other types of implicit widening casts.
22652265 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2266 SDLoc dl);
2266 const SDLoc &dl);
22672267 };
22682268
22692269 /// Look at Op. At this point, we know that only the DemandedMask bits of the
23312331
23322332 /// Try to simplify a setcc built with the specified operands and cc. If it is
23332333 /// unable to simplify it, return a null SDValue.
2334 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2335 ISD::CondCode Cond, bool foldBooleans,
2336 DAGCombinerInfo &DCI, SDLoc dl) const;
2334 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2335 bool foldBooleans, DAGCombinerInfo &DCI,
2336 const SDLoc &dl) const;
23372337
23382338 /// Returns true (and the GlobalValue and the offset) if the node is a
23392339 /// GlobalAddress + offset.
24332433 /// should fill in the InVals array with legal-type argument values, and
24342434 /// return the resulting token chain value.
24352435 ///
2436 virtual SDValue
2437 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2438 bool /*isVarArg*/,
2439 const SmallVectorImpl &/*Ins*/,
2440 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2441 SmallVectorImpl &/*InVals*/) const {
2436 virtual SDValue LowerFormalArguments(
2437 SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
2438 const SmallVectorImpl & /*Ins*/, const SDLoc & /*dl*/,
2439 SelectionDAG & /*DAG*/, SmallVectorImpl & /*InVals*/) const {
24422440 llvm_unreachable("Not Implemented");
24432441 }
24442442
25052503 CallConv(CallingConv::C), DAG(DAG), CS(nullptr), IsPatchPoint(false) {
25062504 }
25072505
2508 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2506 CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
25092507 DL = dl;
25102508 return *this;
25112509 }
26392637 /// This hook must be implemented to lower outgoing return values, described
26402638 /// by the Outs array, into the specified DAG. The implementation should
26412639 /// return the resulting token chain value.
2642 virtual SDValue
2643 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2644 bool /*isVarArg*/,
2645 const SmallVectorImpl &/*Outs*/,
2646 const SmallVectorImpl &/*OutVals*/,
2647 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2640 virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2641 bool /*isVarArg*/,
2642 const SmallVectorImpl & /*Outs*/,
2643 const SmallVectorImpl & /*OutVals*/,
2644 const SDLoc & /*dl*/,
2645 SelectionDAG & /*DAG*/) const {
26482646 llvm_unreachable("Not Implemented");
26492647 }
26502648
27122710 /// which allows a CPU to reuse the result of a previous load indefinitely,
27132711 /// even if a cache-coherent store is performed by another CPU. The default
27142712 /// implementation does nothing.
2715 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2713 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
27162714 SelectionDAG &DAG) const {
27172715 return Chain;
27182716 }
30393037 private:
30403038 SDValue simplifySetCCWithAnd(EVT VT, SDValue N0, SDValue N1,
30413039 ISD::CondCode Cond, DAGCombinerInfo &DCI,
3042 SDLoc DL) const;
3040 const SDLoc &DL) const;
30433041 };
30443042
30453043 /// Given an LLVM IR type and return type attributes, compute the return value
168168 Locs.push_back(Loc);
169169 }
170170
171 void CodeViewDebug::maybeRecordLocation(DebugLoc DL,
171 void CodeViewDebug::maybeRecordLocation(const DebugLoc &DL,
172172 const MachineFunction *MF) {
173173 // Skip this instruction if it has the same location as the previous one.
174174 if (DL == CurFn->LastLoc)
149149
150150 unsigned maybeRecordFile(const DIFile *F);
151151
152 void maybeRecordLocation(DebugLoc DL, const MachineFunction *MF);
152 void maybeRecordLocation(const DebugLoc &DL, const MachineFunction *MF);
153153
154154 void clear() {
155155 assert(CurFn == nullptr);
6363 void FindSafePoints(MachineFunction &MF);
6464 void VisitCallPoint(MachineBasicBlock::iterator MI);
6565 MCSymbol *InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
66 DebugLoc DL) const;
66 const DebugLoc &DL) const;
6767
6868 void FindStackOffsets(MachineFunction &MF);
6969
269269
270270 MCSymbol *GCMachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB,
271271 MachineBasicBlock::iterator MI,
272 DebugLoc DL) const {
272 const DebugLoc &DL) const {
273273 MCSymbol *Label = MBB.getParent()->getContext().createTempSymbol();
274274 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
275275 return Label;
304304
305305 /// getUserValue - Find or create a UserValue.
306306 UserValue *getUserValue(const MDNode *Var, const MDNode *Expr,
307 unsigned Offset, bool IsIndirect, DebugLoc DL);
307 unsigned Offset, bool IsIndirect, const DebugLoc &DL);
308308
309309 /// lookupVirtReg - Find the EC leader for VirtReg or null.
310310 UserValue *lookupVirtReg(unsigned VirtReg);
357357 };
358358 } // namespace
359359
360 static void printDebugLoc(DebugLoc DL, raw_ostream &CommentOS,
360 static void printDebugLoc(const DebugLoc &DL, raw_ostream &CommentOS,
361361 const LLVMContext &Ctx) {
362362 if (!DL)
363363 return;
458458
459459 UserValue *LDVImpl::getUserValue(const MDNode *Var, const MDNode *Expr,
460460 unsigned Offset, bool IsIndirect,
461 DebugLoc DL) {
461 const DebugLoc &DL) {
462462 UserValue *&Leader = userVarMap[Var];
463463 if (Leader) {
464464 UserValue *UV = Leader->getLeader();
246246 }
247247
248248 /// Allocate a new MachineInstr. Use this instead of `new MachineInstr'.
249 MachineInstr *
250 MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
251 DebugLoc DL, bool NoImp) {
249 MachineInstr *MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
250 const DebugLoc &DL,
251 bool NoImp) {
252252 return new (InstructionRecycler.Allocate(Allocator))
253253 MachineInstr(*this, MCID, DL, NoImp);
254254 }
21672167 report_fatal_error(Msg);
21682168 }
21692169
2170 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, DebugLoc DL,
2170 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
21712171 const MCInstrDesc &MCID, bool IsIndirect,
21722172 unsigned Reg, unsigned Offset,
21732173 const MDNode *Variable, const MDNode *Expr) {
21922192 }
21932193
21942194 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2195 MachineBasicBlock::iterator I, DebugLoc DL,
2196 const MCInstrDesc &MCID, bool IsIndirect,
2197 unsigned Reg, unsigned Offset,
2198 const MDNode *Variable, const MDNode *Expr) {
2195 MachineBasicBlock::iterator I,
2196 const DebugLoc &DL, const MCInstrDesc &MCID,
2197 bool IsIndirect, unsigned Reg,
2198 unsigned Offset, const MDNode *Variable,
2199 const MDNode *Expr) {
21992200 assert(isa(Variable) && "not a variable");
22002201 assert(cast(Expr)->isValid() && "not an expression");
22012202 MachineFunction &MF = *BB.getParent();
211211 SDValue PromoteExtend(SDValue Op);
212212 bool PromoteLoad(SDValue Op);
213213
214 void ExtendSetCCUses(const SmallVectorImpl &SetCCs,
215 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
214 void ExtendSetCCUses(const SmallVectorImpl &SetCCs, SDValue Trunc,
215 SDValue ExtLoad, const SDLoc &DL,
216216 ISD::NodeType ExtType);
217217
218218 /// Call the node-specific routine that knows how to fold each
328328 SDValue visitFMULForFMACombine(SDNode *N);
329329
330330 SDValue XformToShuffleWithZero(SDNode *N);
331 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
331 SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue LHS,
332 SDValue RHS);
332333
333334 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
334335
335336 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
336337 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
337 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
338 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
339 SDValue N3, ISD::CondCode CC,
338 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
339 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
340 SDValue N2, SDValue N3, ISD::CondCode CC,
340341 bool NotExtCompare = false);
341342 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
342 SDLoc DL, bool foldBooleans = true);
343 const SDLoc &DL, bool foldBooleans = true);
343344
344345 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
345346 SDValue &CC) const;
366367 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
367368 SDValue InnerPos, SDValue InnerNeg,
368369 unsigned PosOpcode, unsigned NegOpcode,
369 SDLoc DL);
370 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
370 const SDLoc &DL);
371 SDNode *MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
371372 SDValue ReduceLoadWidth(SDNode *N);
372373 SDValue ReduceLoadOpStoreWidth(SDNode *N);
373374 SDValue TransformFPLoadStorePair(SDNode *N);
419420
420421 /// This is a helper function for MergeStoresOfConstantsOrVecElts. Returns a
421422 /// constant build_vector of the stored constant values in Stores.
422 SDValue getMergedConstantVectorStore(SelectionDAG &DAG,
423 SDLoc SL,
423 SDValue getMergedConstantVectorStore(SelectionDAG &DAG, const SDLoc &SL,
424424 ArrayRef Stores,
425425 SmallVectorImpl &Chains,
426426 EVT Ty) const;
822822 return nullptr;
823823 }
824824
825 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
826 SDValue N0, SDValue N1) {
825 SDValue DAGCombiner::ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
826 SDValue N1) {
827827 EVT VT = N0.getValueType();
828828 if (N0.getOpcode() == Opc) {
829829 if (SDNode *L = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
18501850
18511851 // Since it may not be valid to emit a fold to zero for vector initializers
18521852 // check if we can before folding.
1853 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1854 SelectionDAG &DAG,
1855 bool LegalOperations, bool LegalTypes) {
1853 static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
1854 SelectionDAG &DAG, bool LegalOperations,
1855 bool LegalTypes) {
18561856 if (!VT.isVector())
18571857 return DAG.getConstant(0, DL, VT);
18581858 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
39993999 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
40004000 SDValue Neg, SDValue InnerPos,
40014001 SDValue InnerNeg, unsigned PosOpcode,
4002 unsigned NegOpcode, SDLoc DL) {
4002 unsigned NegOpcode, const SDLoc &DL) {
40034003 // fold (or (shl x, (*ext y)),
40044004 // (srl x, (*ext (sub 32, y)))) ->
40054005 // (rotl x, y) or (rotr x, (sub 32, y))
40204020 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
40214021 // idioms for rotate, and if the target supports rotation instructions, generate
40224022 // a rot[lr].
4023 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
4023 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
40244024 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
40254025 EVT VT = LHS.getValueType();
40264026 if (!TLI.isTypeLegal(VT)) return nullptr;
50365036
50375037
50385038 /// \brief Generate Min/Max node
5039 static SDValue combineMinNumMaxNum(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,
5040 SDValue True, SDValue False,
5039 static SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
5040 SDValue RHS, SDValue True, SDValue False,
50415041 ISD::CondCode CC, const TargetLowering &TLI,
50425042 SelectionDAG &DAG) {
50435043 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
58995899 }
59005900
59015901 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl &SetCCs,
5902 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
5903 ISD::NodeType ExtType) {
5902 SDValue Trunc, SDValue ExtLoad,
5903 const SDLoc &DL, ISD::NodeType ExtType) {
59045904 // Extend SetCC uses if necessary.
59055905 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
59065906 SDNode *SetCC = SetCCs[i];
1124011240 return false;
1124111241 }
1124211242
11243 SDValue DAGCombiner::getMergedConstantVectorStore(SelectionDAG &DAG,
11244 SDLoc SL,
11245 ArrayRef Stores,
11246 SmallVectorImpl &Chains,
11247 EVT Ty) const {
11243 SDValue DAGCombiner::getMergedConstantVectorStore(
11244 SelectionDAG &DAG, const SDLoc &SL, ArrayRef Stores,
11245 SmallVectorImpl &Chains, EVT Ty) const {
1124811246 SmallVector BuildVector;
1124911247
1125011248 for (unsigned I = 0, E = Ty.getVectorNumElements(); I != E; ++I) {
1400214000 return SDValue();
1400314001 }
1400414002
14005 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
14006 SDValue N1, SDValue N2){
14003 SDValue DAGCombiner::SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1,
14004 SDValue N2) {
1400714005 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
1400814006
1400914007 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
1418614184
1418714185 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
1418814186 /// where 'cond' is the comparison specified by CC.
14189 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
14190 SDValue N2, SDValue N3,
14191 ISD::CondCode CC, bool NotExtCompare) {
14187 SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
14188 SDValue N2, SDValue N3, ISD::CondCode CC,
14189 bool NotExtCompare) {
1419214190 // (x ? y : y) -> y.
1419314191 if (N2 == N3) return N2;
1419414192
1446814466 }
1446914467
1447014468 /// This is a stub for TargetLowering::SimplifySetCC.
14471 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
14472 SDValue N1, ISD::CondCode Cond,
14473 SDLoc DL, bool foldBooleans) {
14469 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
14470 ISD::CondCode Cond, const SDLoc &DL,
14471 bool foldBooleans) {
1447414472 TargetLowering::DAGCombinerInfo
1447514473 DagCombineInfo(DAG, Level, false, this);
1447614474 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
14341434
14351435 /// Emit an unconditional branch to the given block, unless it is the immediate
14361436 /// (fall-through) successor, and update the CFG.
1437 void FastISel::fastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
1437 void FastISel::fastEmitBranch(MachineBasicBlock *MSucc,
1438 const DebugLoc &DbgLoc) {
14381439 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
14391440 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
14401441 // For more accurate line information if this is the only instruction
440440 }
441441
442442 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
443 MVT VT, DebugLoc DL) {
443 MVT VT, const DebugLoc &DL) {
444444 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
445445 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
446446
8282 /// ConstrainForSubReg - Try to constrain VReg to a register class that
8383 /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
8484 /// Return the virtual register to use.
85 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
86 MVT VT, DebugLoc DL);
85 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, MVT VT,
86 const DebugLoc &DL);
8787
8888 /// EmitSubregNode - Generate machine code for subreg nodes.
8989 ///
9393 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
9494 /// is necessary to spill the vector being inserted into to memory, perform
9595 /// the insert there, and then read the result back.
96 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
97 SDValue Idx, SDLoc dl);
98 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
99 SDValue Idx, SDLoc dl);
96 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
97 const SDLoc &dl);
98 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
99 const SDLoc &dl);
100100
101101 /// Return a vector shuffle operation which
102102 /// performs the same shuffe in terms of order or result bytes, but on a type
103103 /// whose vector element type is narrower than the original shuffle type.
104104 /// e.g. <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
106106 SDValue N1, SDValue N2,
107107 ArrayRef Mask) const;
108108
109109 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
110 bool &NeedInvert, SDLoc dl);
110 bool &NeedInvert, const SDLoc &dl);
111111
112112 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
113113 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
114 unsigned NumOps, bool isSigned, SDLoc dl);
114 unsigned NumOps, bool isSigned, const SDLoc &dl);
115115
116116 std::pair ExpandChainLibCall(RTLIB::Libcall LC,
117117 SDNode *Node, bool isSigned);
128128 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl &Results);
129129 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl &Results);
130130
131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
132 const SDLoc &dl);
132133 SDValue ExpandBUILD_VECTOR(SDNode *Node);
133134 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
134135 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
135136 SmallVectorImpl &Results);
136 void getSignAsIntValue(FloatSignAsInt &State, SDLoc DL, SDValue Value) const;
137 SDValue modifySignAsInt(const FloatSignAsInt &State, SDLoc DL,
137 void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
138 SDValue Value) const;
139 SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
138140 SDValue NewIntValue) const;
139141 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
140142 SDValue ExpandFABS(SDNode *Node) const;
141143 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
142 SDLoc dl);
144 const SDLoc &dl);
143145 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
144 SDLoc dl);
146 const SDLoc &dl);
145147 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
146 SDLoc dl);
147
148 SDValue ExpandBITREVERSE(SDValue Op, SDLoc dl);
149 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
150 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
148 const SDLoc &dl);
149
150 SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
151 SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
152 SDValue ExpandBitCount(unsigned Opc, SDValue Op, const SDLoc &dl);
151153
152154 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
153155 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
213215 /// performs the same shuffe in terms of order or result bytes, but on a type
214216 /// whose vector element type is narrower than the original shuffle type.
215217 /// e.g. <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
216 SDValue
217 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
218 SDValue N1, SDValue N2,
219 ArrayRef Mask) const {
218 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
219 EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
220 ArrayRef Mask) const {
220221 unsigned NumMaskElts = VT.getVectorNumElements();
221222 unsigned NumDestElts = NVT.getVectorNumElements();
222223 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
313314 /// INSERT_VECTOR_ELT instruction. In this case, it
314315 /// is necessary to spill the vector being inserted into to memory, perform
315316 /// the insert there, and then read the result back.
316 SDValue SelectionDAGLegalize::
317 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
318 SDLoc dl) {
317 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
318 SDValue Val,
319 SDValue Idx,
320 const SDLoc &dl) {
319321 SDValue Tmp1 = Vec;
320322 SDValue Tmp2 = Val;
321323 SDValue Tmp3 = Idx;
356358 false, false, false, 0);
357359 }
358360
359
360 SDValue SelectionDAGLegalize::
361 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
361 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
362 SDValue Idx,
363 const SDLoc &dl) {
362364 if (ConstantSDNode *InsertPos = dyn_cast(Idx)) {
363365 // SCALAR_TO_VECTOR requires that the type of the value being inserted
364366 // match the element type of the vector being created, except for
13671369 /// containing the sign bit if the target has no integer value capable of
13681370 /// holding all bits of the floating-point value.
13691371 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1370 SDLoc DL, SDValue Value) const {
1372 const SDLoc &DL,
1373 SDValue Value) const {
13711374 EVT FloatVT = Value.getValueType();
13721375 unsigned NumBits = FloatVT.getSizeInBits();
13731376 State.FloatVT = FloatVT;
14191422 /// Replace the integer value produced by getSignAsIntValue() with a new value
14201423 /// and cast the result back to a floating-point type.
14211424 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1422 SDLoc DL, SDValue NewIntValue) const {
1425 const SDLoc &DL,
1426 SDValue NewIntValue) const {
14231427 if (!State.Chain)
14241428 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
14251429
15651569 /// of a true/false result.
15661570 ///
15671571 /// \returns true if the SetCC has been legalized, false if it hasn't.
1568 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1569 SDValue &LHS, SDValue &RHS,
1570 SDValue &CC,
1572 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1573 SDValue &RHS, SDValue &CC,
15711574 bool &NeedInvert,
1572 SDLoc dl) {
1575 const SDLoc &dl) {
15731576 MVT OpVT = LHS.getSimpleValueType();
15741577 ISD::CondCode CCCode = cast(CC)->get();
15751578 NeedInvert = false;
16661669 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
16671670 /// a load from the stack slot to DestVT, extending it if needed.
16681671 /// The resultant code need not be legal.
1669 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1670 EVT SlotVT,
1671 EVT DestVT,
1672 SDLoc dl) {
1672 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1673 EVT DestVT, const SDLoc &dl) {
16731674 // Create the stack frame object.
16741675 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
16751676 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
19921993 /// and returning a result of type RetVT.
19931994 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
19941995 const SDValue *Ops, unsigned NumOps,
1995 bool isSigned, SDLoc dl) {
1996 bool isSigned, const SDLoc &dl) {
19961997 TargetLowering::ArgListTy Args;
19971998 Args.reserve(NumOps);
19981999
22672268 /// INT_TO_FP operation of the specified operand when the target requests that
22682269 /// we expand it. At this point, we know that the result and operand types are
22692270 /// legal for the target.
2270 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2271 SDValue Op0,
2271 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
22722272 EVT DestVT,
2273 SDLoc dl) {
2273 const SDLoc &dl) {
22742274 // TODO: Should any fast-math-flags be set for the created nodes?
22752275
22762276 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
24782478 /// we promote it. At this point, we know that the result and operand types are
24792479 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
24802480 /// operation that takes a larger input.
2481 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2482 EVT DestVT,
2481 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
24832482 bool isSigned,
2484 SDLoc dl) {
2483 const SDLoc &dl) {
24852484 // First step, figure out the appropriate *INT_TO_FP operation to use.
24862485 EVT NewInTy = LegalOp.getValueType();
24872486
25202519 /// we promote it. At this point, we know that the result and operand types are
25212520 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
25222521 /// operation that returns a larger result.
2523 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2524 EVT DestVT,
2522 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
25252523 bool isSigned,
2526 SDLoc dl) {
2524 const SDLoc &dl) {
25272525 // First step, figure out the appropriate FP_TO*INT operation to use.
25282526 EVT NewOutTy = DestVT;
25292527
25602558 }
25612559
25622560 /// Open code the operations for BITREVERSE.
2563 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, SDLoc dl) {
2561 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
25642562 EVT VT = Op.getValueType();
25652563 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
25662564 unsigned Sz = VT.getScalarSizeInBits();
25852583 }
25862584
25872585 /// Open code the operations for BSWAP of the specified operation.
2588 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2586 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
25892587 EVT VT = Op.getValueType();
25902588 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
25912589 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
26392637
26402638 /// Expand the specified bitcount instruction into operations.
26412639 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2642 SDLoc dl) {
2640 const SDLoc &dl) {
26432641 switch (Opc) {
26442642 default: llvm_unreachable("Cannot expand this yet!");
26452643 case ISD::CTPOP: {
15151515 void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
15161516 SDValue &NewRHS,
15171517 ISD::CondCode &CCCode,
1518 SDLoc dl) {
1518 const SDLoc &dl) {
15191519 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
15201520 GetExpandedFloat(NewLHS, LHSLo, LHSHi);
15211521 GetExpandedFloat(NewRHS, RHSLo, RHSHi);
27852785 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
27862786 SDValue &NewRHS,
27872787 ISD::CondCode &CCCode,
2788 SDLoc dl) {
2788 const SDLoc &dl) {
27892789 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
27902790 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
27912791 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
388388 SDValue ExpandIntOp_ATOMIC_STORE(SDNode *N);
389389
390390 void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
391 ISD::CondCode &CCCode, SDLoc dl);
391 ISD::CondCode &CCCode, const SDLoc &dl);
392392
393393 //===--------------------------------------------------------------------===//
394394 // Float to Integer Conversion Support: LegalizeFloatTypes.cpp
542542 SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo);
543543
544544 void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,
545 ISD::CondCode &CCCode, SDLoc dl);
546
545 ISD::CondCode &CCCode, const SDLoc &dl);
547546
548547 //===--------------------------------------------------------------------===//
549548 // Float promotion support: LegalizeFloatTypes.cpp
923923 #endif
924924 }
925925
926 SDNode *SelectionDAG::GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
927 SDValue N1, SDValue N2,
926 SDNode *SelectionDAG::GetBinarySDNode(unsigned Opcode, const SDLoc &DL,
927 SDVTList VTs, SDValue N1, SDValue N2,
928928 const SDNodeFlags *Flags) {
929929 SDValue Ops[] = {N1, N2};
930930
962962 }
963963
964964 SDNode *SelectionDAG::FindNodeOrInsertPos(const FoldingSetNodeID &ID,
965 SDLoc DL, void *&InsertPos) {
965 const SDLoc &DL, void *&InsertPos) {
966966 SDNode *N = CSEMap.FindNodeOrInsertPos(ID, InsertPos);
967967 if (N) {
968968 switch (N->getOpcode()) {
10071007 DbgInfo->clear();
10081008 }
10091009
1010 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) {
1010 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
10111011 return VT.bitsGT(Op.getValueType()) ?
10121012 getNode(ISD::ANY_EXTEND, DL, VT, Op) :
10131013 getNode(ISD::TRUNCATE, DL, VT, Op);
10141014 }
10151015
1016 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) {
1016 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
10171017 return VT.bitsGT(Op.getValueType()) ?
10181018 getNode(ISD::SIGN_EXTEND, DL, VT, Op) :
10191019 getNode(ISD::TRUNCATE, DL, VT, Op);
10201020 }
10211021
1022 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) {
1022 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
10231023 return VT.bitsGT(Op.getValueType()) ?
10241024 getNode(ISD::ZERO_EXTEND, DL, VT, Op) :
10251025 getNode(ISD::TRUNCATE, DL, VT, Op);
10261026 }
10271027
1028 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT,
1028 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT,
10291029 EVT OpVT) {
10301030 if (VT.bitsLE(Op.getValueType()))
10311031 return getNode(ISD::TRUNCATE, SL, VT, Op);
10341034 return getNode(TLI->getExtendForContent(BType), SL, VT, Op);
10351035 }
10361036
1037 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) {
1037 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
10381038 assert(!VT.isVector() &&
10391039 "getZeroExtendInReg should use the vector element type instead of "
10401040 "the vector type!");
10461046 getConstant(Imm, DL, Op.getValueType()));
10471047 }
10481048
1049 SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) {
1049 SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, const SDLoc &DL,
1050 EVT VT) {
10501051 assert(VT.isVector() && "This DAG node is restricted to vector types.");
10511052 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() &&
10521053 "The sizes of the input and result must match in order to perform the "
10561057 return getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Op);
10571058 }
10581059
1059 SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) {
1060 SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, const SDLoc &DL,
1061 EVT VT) {
10601062 assert(VT.isVector() && "This DAG node is restricted to vector types.");
10611063 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() &&
10621064 "The sizes of the input and result must match in order to perform the "
10661068 return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op);
10671069 }
10681070
1069 SDValue SelectionDAG::getZeroExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) {
1071 SDValue SelectionDAG::getZeroExtendVectorInReg(SDValue Op, const SDLoc &DL,
1072 EVT VT) {
10701073 assert(VT.isVector() && "This DAG node is restricted to vector types.");
10711074 assert(VT.getSizeInBits() == Op.getValueType().getSizeInBits() &&
10721075 "The sizes of the input and result must match in order to perform the "
10781081
10791082 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
10801083 ///
1081 SDValue SelectionDAG::getNOT(SDLoc DL, SDValue Val, EVT VT) {
1084 SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) {
10821085 EVT EltVT = VT.getScalarType();
10831086 SDValue NegOne =
10841087 getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), DL, VT);
10851088 return getNode(ISD::XOR, DL, VT, Val, NegOne);
10861089 }
10871090
1088 SDValue SelectionDAG::getLogicalNOT(SDLoc DL, SDValue Val, EVT VT) {
1091 SDValue SelectionDAG::getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT) {
10891092 EVT EltVT = VT.getScalarType();
10901093 SDValue TrueValue;
10911094 switch (TLI->getBooleanContents(VT)) {
11011104 return getNode(ISD::XOR, DL, VT, Val, TrueValue);
11021105 }
11031106
1104 SDValue SelectionDAG::getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isT,
1105 bool isO) {
1107 SDValue SelectionDAG::getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
1108 bool isT, bool isO) {
11061109 EVT EltVT = VT.getScalarType();
11071110 assert((EltVT.getSizeInBits() >= 64 ||
11081111 (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
11101113 return getConstant(APInt(EltVT.getSizeInBits(), Val), DL, VT, isT, isO);
11111114 }
11121115
1113 SDValue SelectionDAG::getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isT,
1114 bool isO) {
1116 SDValue SelectionDAG::getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
1117 bool isT, bool isO) {
11151118 return getConstant(*ConstantInt::get(*Context, Val), DL, VT, isT, isO);
11161119 }
11171120
1118 SDValue SelectionDAG::getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
1119 bool isT, bool isO) {
1121 SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL,
1122 EVT VT, bool isT, bool isO) {
11201123 assert(VT.isInteger() && "Cannot create FP integer constant!");
11211124
11221125 EVT EltVT = VT.getScalarType();
12051208 return Result;
12061209 }
12071210
1208 SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget) {
1211 SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, const SDLoc &DL,
1212 bool isTarget) {
12091213 return getConstant(Val, DL, TLI->getPointerTy(getDataLayout()), isTarget);
12101214 }
12111215
1212 SDValue SelectionDAG::getConstantFP(const APFloat& V, SDLoc DL, EVT VT,
1216 SDValue SelectionDAG::getConstantFP(const APFloat &V, const SDLoc &DL, EVT VT,
12131217 bool isTarget) {
12141218 return getConstantFP(*ConstantFP::get(*getContext(), V), DL, VT, isTarget);
12151219 }
12161220
1217 SDValue SelectionDAG::getConstantFP(const ConstantFP& V, SDLoc DL, EVT VT,
1218 bool isTarget){
1221 SDValue SelectionDAG::getConstantFP(const ConstantFP &V, const SDLoc &DL,
1222 EVT VT, bool isTarget) {
12191223 assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
12201224
12211225 EVT EltVT = VT.getScalarType();
12451249 return Result;
12461250 }
12471251
1248 SDValue SelectionDAG::getConstantFP(double Val, SDLoc DL, EVT VT,
1252 SDValue SelectionDAG::getConstantFP(double Val, const SDLoc &DL, EVT VT,
12491253 bool isTarget) {
12501254 EVT EltVT = VT.getScalarType();
12511255 if (EltVT == MVT::f32)
12631267 llvm_unreachable("Unsupported type in getConstantFP");
12641268 }
12651269
1266 SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, SDLoc DL,
1267 EVT VT, int64_t Offset,
1268 bool isTargetGA,
1270 SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, const SDLoc &DL,
1271 EVT VT, int64_t Offset, bool isTargetGA,
12691272 unsigned char TargetFlags) {
12701273 assert((TargetFlags == 0 || isTargetGA) &&
12711274 "Cannot set target flags on target-independent globals");
14791482 ShuffleVectorSDNode::commuteMask(M);
14801483 }
14811484
1482 SDValue SelectionDAG::getVectorShuffle(EVT VT, SDLoc dl, SDValue N1,
1485 SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1,
14831486 SDValue N2, const int *Mask) {
14841487 assert(VT == N1.getValueType() && VT == N2.getValueType() &&
14851488 "Invalid VECTOR_SHUFFLE");
16551658 return getVectorShuffle(VT, SDLoc(&SV), Op1, Op0, &MaskVec[0]);
16561659 }
16571660
1658 SDValue SelectionDAG::getConvertRndSat(EVT VT, SDLoc dl,
1659 SDValue Val, SDValue DTy,
1660 SDValue STy, SDValue Rnd, SDValue Sat,
1661 ISD::CvtCode Code) {
1661 SDValue SelectionDAG::getConvertRndSat(EVT VT, const SDLoc &dl, SDValue Val,
1662 SDValue DTy, SDValue STy, SDValue Rnd,
1663 SDValue Sat, ISD::CvtCode Code) {
16621664 // If the src and dest types are the same and the conversion is between
16631665 // integer types of the same sign or two floats, no conversion is necessary.
16641666 if (DTy == STy &&
17091711 return SDValue(N, 0);
17101712 }
17111713
1712 SDValue SelectionDAG::getEHLabel(SDLoc dl, SDValue Root, MCSymbol *Label) {
1714 SDValue SelectionDAG::getEHLabel(const SDLoc &dl, SDValue Root,
1715 MCSymbol *Label) {
17131716 FoldingSetNodeID ID;
17141717 SDValue Ops[] = { Root };
17151718 AddNodeIDNode(ID, ISD::EH_LABEL, getVTList(MVT::Other), Ops);
17901793 }
17911794
17921795 /// getAddrSpaceCast - Return an AddrSpaceCastSDNode.
1793 SDValue SelectionDAG::getAddrSpaceCast(SDLoc dl, EVT VT, SDValue Ptr,
1796 SDValue SelectionDAG::getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr,
17941797 unsigned SrcAS, unsigned DestAS) {
17951798 SDValue Ops[] = {Ptr};
17961799 FoldingSetNodeID ID;
19001903 return getFrameIndex(FrameIdx, TLI->getPointerTy(getDataLayout()));
19011904 }
19021905
1903 SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1,
1904 SDValue N2, ISD::CondCode Cond, SDLoc dl) {
1906 SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
1907 ISD::CondCode Cond, const SDLoc &dl) {
19051908 // These setcc operations always fold.
19061909 switch (Cond) {
19071910 default: break;
28642867 return (AZero | BZero).isAllOnesValue();
28652868 }
28662869
2867 static SDValue FoldCONCAT_VECTORS(SDLoc DL, EVT VT, ArrayRef Ops,
2870 static SDValue FoldCONCAT_VECTORS(const SDLoc &DL, EVT VT,
2871 ArrayRef Ops,
28682872 llvm::SelectionDAG &DAG) {
28692873 if (Ops.size() == 1)
28702874 return Ops[0];
29042908
29052909 /// getNode - Gets or creates the specified node.
29062910 ///
2907 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT) {
2911 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT) {
29082912 FoldingSetNodeID ID;
29092913 AddNodeIDNode(ID, Opcode, getVTList(VT), None);
29102914 void *IP = nullptr;
29192923 return SDValue(N, 0);
29202924 }
29212925
2922 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
2923 EVT VT, SDValue Operand) {
2926 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
2927 SDValue Operand) {
29242928 // Constant fold unary operations with an integer constant operand. Even
29252929 // opaque constant will be folded, because the folding of unary operations
29262930 // doesn't create new constants with different values. Nevertheless, the
32873291 return std::make_pair(APInt(1, 0), false);
32883292 }
32893293
3290 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
3291 const ConstantSDNode *Cst1,
3294 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
3295 EVT VT, const ConstantSDNode *Cst1,
32923296 const ConstantSDNode *Cst2) {
32933297 if (Cst1->isOpaque() || Cst2->isOpaque())
32943298 return SDValue();
33203324 GA->getOffset() + uint64_t(Offset));
33213325 }
33223326
3323 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
3324 SDNode *Cst1, SDNode *Cst2) {
3327 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
3328 EVT VT, SDNode *Cst1,
3329 SDNode *Cst2) {
33253330 // If the opcode is a target-specific ISD node, there's nothing we can
33263331 // do here and the operand rules may not line up with the below, so
33273332 // bail early.
33883393 return getBuildVector(VT, SDLoc(), Outputs);
33893394 }
33903395
3391 SDValue SelectionDAG::FoldConstantVectorArithmetic(unsigned Opcode, SDLoc DL,
3392 EVT VT,
3396 SDValue SelectionDAG::FoldConstantVectorArithmetic(unsigned Opcode,
3397 const SDLoc &DL, EVT VT,
33933398 ArrayRef Ops,
33943399 const SDNodeFlags *Flags) {
33953400 // If the opcode is a target-specific ISD node, there's nothing we can
34793484 return getBuildVector(VT, DL, ScalarResults);
34803485 }
34813486
3482 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
3483 SDValue N2, const SDNodeFlags *Flags) {
3487 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
3488 SDValue N1, SDValue N2,
3489 const SDNodeFlags *Flags) {
34843490 ConstantSDNode *N1C = dyn_cast(N1);
34853491 ConstantSDNode *N2C = dyn_cast(N2);
34863492 ConstantFPSDNode *N1CFP = dyn_cast(N1);
39533959 return SDValue(N, 0);
39543960 }
39553961
3956 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
3962 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
39573963 SDValue N1, SDValue N2, SDValue N3) {
39583964 // Perform various simplifications.
39593965 switch (Opcode) {
40544060 return SDValue(N, 0);
40554061 }
40564062
4057 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
4058 SDValue N1, SDValue N2, SDValue N3,
4059 SDValue N4) {
4063 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
4064 SDValue N1, SDValue N2, SDValue N3, SDValue N4) {
40604065 SDValue Ops[] = { N1, N2, N3, N4 };
40614066 return getNode(Opcode, DL, VT, Ops);
40624067 }
40634068
4064 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
4065 SDValue N1, SDValue N2, SDValue N3,
4066 SDValue N4, SDValue N5) {
4069 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
4070 SDValue N1, SDValue N2, SDValue N3, SDValue N4,
4071 SDValue N5) {
40674072 SDValue Ops[] = { N1, N2, N3, N4, N5 };
40684073 return getNode(Opcode, DL, VT, Ops);
40694074 }
40934098 /// getMemsetValue - Vectorized representation of the memset value
40944099 /// operand.
40954100 static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
4096 SDLoc dl) {
4101 const SDLoc &dl) {
40974102 assert(!Value.isUndef());
40984103
40994104 unsigned NumBits = VT.getScalarType().getSizeInBits();
41314136 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
41324137 /// used when a memcpy is turned into a memset when the source is a constant
41334138 /// string ptr.
4134 static SDValue getMemsetStringVal(EVT VT, SDLoc dl, SelectionDAG &DAG,
4139 static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG,
41354140 const TargetLowering &TLI, StringRef Str) {
41364141 // Handle vector with all elements zero.
41374142 if (Str.empty()) {
41734178 }
41744179
41754180 SDValue SelectionDAG::getMemBasePlusOffset(SDValue Base, unsigned Offset,
4176 SDLoc DL) {
4181 const SDLoc &DL) {
41774182 EVT VT = Base.getValueType();
41784183 return getNode(ISD::ADD, DL, VT, Base, getConstant(Offset, DL, VT));
41794184 }
43124317 return MF.getFunction()->optForSize();
43134318 }
43144319
4315 static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
4316 SDValue Chain, SDValue Dst,
4317 SDValue Src, uint64_t Size,
4318 unsigned Align, bool isVol,
4319 bool AlwaysInline,
4320 static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
4321 SDValue Chain, SDValue Dst, SDValue Src,
4322 uint64_t Size, unsigned Align,
4323 bool isVol, bool AlwaysInline,
43204324 MachinePointerInfo DstPtrInfo,
43214325 MachinePointerInfo SrcPtrInfo) {
43224326 // Turn a memcpy of undef to nop.
44314435 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
44324436 }
44334437
4434 static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
4435 SDValue Chain, SDValue Dst,
4436 SDValue Src, uint64_t Size,
4437 unsigned Align, bool isVol,
4438 bool AlwaysInline,
4438 static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
4439 SDValue Chain, SDValue Dst, SDValue Src,
4440 uint64_t Size, unsigned Align,
4441 bool isVol, bool AlwaysInline,
44394442 MachinePointerInfo DstPtrInfo,
44404443 MachinePointerInfo SrcPtrInfo) {
44414444 // Turn a memmove of undef to nop.
45304533 /// The function tries to replace 'llvm.memset' intrinsic with several store
45314534 /// operations and value calculation code. This is usually profitable for small
45324535 /// memory size.
4533 static SDValue getMemsetStores(SelectionDAG &DAG, SDLoc dl,
4534 SDValue Chain, SDValue Dst,
4535 SDValue Src, uint64_t Size,
4536 unsigned Align, bool isVol,
4536 static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
4537 SDValue Chain, SDValue Dst, SDValue Src,
4538 uint64_t Size, unsigned Align, bool isVol,
45374539 MachinePointerInfo DstPtrInfo) {
45384540 // Turn a memset of undef to nop.
45394541 if (Src.isUndef())
46244626 }
46254627 }
46264628
4627 SDValue SelectionDAG::getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst,
4628 SDValue Src, SDValue Size,
4629 unsigned Align, bool isVol, bool AlwaysInline,
4630 bool isTailCall, MachinePointerInfo DstPtrInfo,
4629 SDValue SelectionDAG::getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst,
4630 SDValue Src, SDValue Size, unsigned Align,
4631 bool isVol, bool AlwaysInline, bool isTailCall,
4632 MachinePointerInfo DstPtrInfo,
46314633 MachinePointerInfo SrcPtrInfo) {
46324634 assert(Align && "The SDAG layer expects explicit alignment and reserves 0");
46334635
46974699 return CallResult.second;
46984700 }
46994701
4700 SDValue SelectionDAG::getMemmove(SDValue Chain, SDLoc dl, SDValue Dst,
4701 SDValue Src, SDValue Size,
4702 unsigned Align, bool isVol, bool isTailCall,
4702 SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
4703 SDValue Src, SDValue Size, unsigned Align,
4704 bool isVol, bool isTailCall,
47034705 MachinePointerInfo DstPtrInfo,
47044706 MachinePointerInfo SrcPtrInfo) {
47054707 assert(Align && "The SDAG layer expects explicit alignment and reserves 0");
47584760 return CallResult.second;
47594761 }
47604762
4761 SDValue SelectionDAG::getMemset(SDValue Chain, SDLoc dl, SDValue Dst,
4762 SDValue Src, SDValue Size,
4763 unsigned Align, bool isVol, bool isTailCall,
4763 SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
4764 SDValue Src, SDValue Size, unsigned Align,
4765 bool isVol, bool isTailCall,
47644766 MachinePointerInfo DstPtrInfo) {
47654767 assert(Align && "The SDAG layer expects explicit alignment and reserves 0");
47664768
48204822 return CallResult.second;
48214823 }
48224824
4823 SDValue SelectionDAG::getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT,
4825 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
48244826 SDVTList VTList, ArrayRef Ops,
48254827 MachineMemOperand *MMO,
48264828 AtomicOrdering SuccessOrdering,
48464848 return SDValue(N, 0);
48474849 }
48484850
4849 SDValue SelectionDAG::getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT,
4851 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
48504852 SDVTList VTList, ArrayRef Ops,
4851 MachineMemOperand *MMO,
4852 AtomicOrdering Ordering,
4853 MachineMemOperand *MMO, AtomicOrdering Ordering,
48534854 SynchronizationScope SynchScope) {
48544855 return getAtomic(Opcode, dl, MemVT, VTList, Ops, MMO, Ordering,
48554856 Ordering, SynchScope);
48564857 }
48574858
48584859 SDValue SelectionDAG::getAtomicCmpSwap(
4859 unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs, SDValue Chain,
4860 unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain,
48604861 SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo,
48614862 unsigned Alignment, AtomicOrdering SuccessOrdering,
48624863 AtomicOrdering FailureOrdering, SynchronizationScope SynchScope) {
48824883 SuccessOrdering, FailureOrdering, SynchScope);
48834884 }
48844885
4885 SDValue SelectionDAG::getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT,
4886 SDVTList VTs, SDValue Chain, SDValue Ptr,
4887 SDValue Cmp, SDValue Swp,
4886 SDValue SelectionDAG::getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl,
4887 EVT MemVT, SDVTList VTs, SDValue Chain,
4888 SDValue Ptr, SDValue Cmp, SDValue Swp,
48884889 MachineMemOperand *MMO,
48894890 AtomicOrdering SuccessOrdering,
48904891 AtomicOrdering FailureOrdering,
48984899 SuccessOrdering, FailureOrdering, SynchScope);
48994900 }
49004901
4901 SDValue SelectionDAG::getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT,
4902 SDValue Chain,
4903 SDValue Ptr, SDValue Val,
4904 const Value* PtrVal,
4905 unsigned Alignment,
4902 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
4903 SDValue Chain, SDValue Ptr, SDValue Val,
4904 const Value *PtrVal, unsigned Alignment,
49064905 AtomicOrdering Ordering,
49074906 SynchronizationScope SynchScope) {
49084907 if (Alignment == 0) // Ensure that codegen never sees alignment 0
49294928 Ordering, SynchScope);
49304929 }
49314930
4932 SDValue SelectionDAG::getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT,
4933 SDValue Chain,
4934 SDValue Ptr, SDValue Val,
4935 MachineMemOperand *MMO,
4936 AtomicOrdering Ordering,
4931 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
4932 SDValue Chain, SDValue Ptr, SDValue Val,
4933 MachineMemOperand *MMO, AtomicOrdering Ordering,
49374934 SynchronizationScope SynchScope) {
49384935 assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
49394936 Opcode == ISD::ATOMIC_LOAD_SUB ||
49574954 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO, Ordering, SynchScope);
49584955 }
49594956
4960 SDValue SelectionDAG::getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT,
4961 EVT VT, SDValue Chain,
4962 SDValue Ptr,
4963 MachineMemOperand *MMO,
4964 AtomicOrdering Ordering,
4957 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
4958 EVT VT, SDValue Chain, SDValue Ptr,
4959 MachineMemOperand *MMO, AtomicOrdering Ordering,
49654960 SynchronizationScope SynchScope) {
49664961 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
49674962
49714966 }
49724967
49734968 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
4974 SDValue SelectionDAG::getMergeValues(ArrayRef Ops, SDLoc dl) {
4969 SDValue SelectionDAG::getMergeValues(ArrayRef Ops, const SDLoc &dl) {
49754970 if (Ops.size() == 1)
49764971 return Ops[0];
49774972
49824977 return getNode(ISD::MERGE_VALUES, dl, getVTList(VTs), Ops);
49834978 }
49844979
4985 SDValue
4986 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,
4987 ArrayRef Ops,
4988 EVT MemVT, MachinePointerInfo PtrInfo,
4989 unsigned Align, bool Vol,
4990 bool ReadMem, bool WriteMem, unsigned Size) {
4980 SDValue SelectionDAG::getMemIntrinsicNode(
4981 unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef Ops,
4982 EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol,
4983 bool ReadMem, bool WriteMem, unsigned Size) {
49914984 if (Align == 0) // Ensure that codegen never sees alignment 0
49924985 Align = getEVTAlignment(MemVT);
49934986
50075000 return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, MMO);
50085001 }
50095002
5010 SDValue
5011 SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,
5012 ArrayRef Ops, EVT MemVT,
5013 MachineMemOperand *MMO) {
5003 SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl,
5004 SDVTList VTList,
5005 ArrayRef Ops, EVT MemVT,
5006 MachineMemOperand *MMO) {
50145007 assert((Opcode == ISD::INTRINSIC_VOID ||
50155008 Opcode == ISD::INTRINSIC_W_CHAIN ||
50165009 Opcode == ISD::PREFETCH ||
50835076 return MachinePointerInfo();
50845077 }
50855078
5086
5087 SDValue
5088 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
5089 EVT VT, SDLoc dl, SDValue Chain,
5090 SDValue Ptr, SDValue Offset,
5091 MachinePointerInfo PtrInfo, EVT MemVT,
5092 bool isVolatile, bool isNonTemporal, bool isInvariant,
5093 unsigned Alignment, const AAMDNodes &AAInfo,
5094 const MDNode *Ranges) {
5079 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
5080 EVT VT, const SDLoc &dl, SDValue Chain,
5081 SDValue Ptr, SDValue Offset,
5082 MachinePointerInfo PtrInfo, EVT MemVT,
5083 bool isVolatile, bool isNonTemporal,
5084 bool isInvariant, unsigned Alignment,
5085 const AAMDNodes &AAInfo, const MDNode *Ranges) {
50955086 assert(Chain.getValueType() == MVT::Other &&
50965087 "Invalid chain type");
50975088 if (Alignment == 0) // Ensure that codegen never sees alignment 0
51175108 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
51185109 }
51195110
5120 SDValue
5121 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
5122 EVT VT, SDLoc dl, SDValue Chain,
5123 SDValue Ptr, SDValue Offset, EVT MemVT,
5124 MachineMemOperand *MMO) {
5111 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
5112 EVT VT, const SDLoc &dl, SDValue Chain,
5113 SDValue Ptr, SDValue Offset, EVT MemVT,
5114 MachineMemOperand *MMO) {
51255115 if (VT == MemVT) {
51265116 ExtType = ISD::NON_EXTLOAD;
51275117 } else if (ExtType == ISD::NON_EXTLOAD) {
51665156 return SDValue(N, 0);
51675157 }
51685158
5169 SDValue SelectionDAG::getLoad(EVT VT, SDLoc dl,
5170 SDValue Chain, SDValue Ptr,
5171 MachinePointerInfo PtrInfo,
5159 SDValue SelectionDAG::getLoad(EVT VT, const SDLoc &dl, SDValue Chain,
5160 SDValue Ptr, MachinePointerInfo PtrInfo,
51725161 bool isVolatile, bool isNonTemporal,
51735162 bool isInvariant, unsigned Alignment,
5174 const AAMDNodes &AAInfo,
5175 const MDNode *Ranges) {
5163 const AAMDNodes &AAInfo, const MDNode *Ranges) {
51765164 SDValue Undef = getUNDEF(Ptr.getValueType());
51775165 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
51785166 PtrInfo, VT, isVolatile, isNonTemporal, isInvariant, Alignment,
51795167 AAInfo, Ranges);
51805168 }
51815169
5182 SDValue SelectionDAG::getLoad(EVT VT, SDLoc dl,
5183 SDValue Chain, SDValue Ptr,
5184 MachineMemOperand *MMO) {
5170 SDValue SelectionDAG::getLoad(EVT VT, const SDLoc &dl, SDValue Chain,
5171 SDValue Ptr, MachineMemOperand *MMO) {
51855172 SDValue Undef = getUNDEF(Ptr.getValueType());
51865173 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
51875174 VT, MMO);
51885175 }
51895176
5190 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
5191 SDValue Chain, SDValue Ptr,
5177 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl,
5178 EVT VT, SDValue Chain, SDValue Ptr,
51925179 MachinePointerInfo PtrInfo, EVT MemVT,
51935180 bool isVolatile, bool isNonTemporal,
51945181 bool isInvariant, unsigned Alignment,
51995186 Alignment, AAInfo);
52005187 }
52015188
5202
5203 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
5204 SDValue Chain, SDValue Ptr, EVT MemVT,
5189 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl,
5190 EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT,
52055191 MachineMemOperand *MMO) {
52065192 SDValue Undef = getUNDEF(Ptr.getValueType());
52075193 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
52085194 MemVT, MMO);
52095195 }
52105196
5211 SDValue
5212 SelectionDAG::getIndexedLoad(SDValue OrigLoad, SDLoc dl, SDValue Base,
5213 SDValue Offset, ISD::MemIndexedMode AM) {
5197 SDValue SelectionDAG::getIndexedLoad(SDValue OrigLoad, const SDLoc &dl,
5198 SDValue Base, SDValue Offset,
5199 ISD::MemIndexedMode AM) {
52145200 LoadSDNode *LD = cast(OrigLoad);
52155201 assert(LD->getOffset().isUndef() && "Load is already a indexed load!");
52165202 return getLoad(AM, LD->getExtensionType(), OrigLoad.getValueType(), dl,
52195205 false, LD->getAlignment());
52205206 }
52215207
5222 SDValue SelectionDAG::getStore(SDValue Chain, SDLoc dl, SDValue Val,
5208 SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val,
52235209 SDValue Ptr, MachinePointerInfo PtrInfo,
52245210 bool isVolatile, bool isNonTemporal,
52255211 unsigned Alignment, const AAMDNodes &AAInfo) {
52455231 return getStore(Chain, dl, Val, Ptr, MMO);
52465232 }
52475233
5248 SDValue SelectionDAG::getStore(SDValue Chain, SDLoc dl, SDValue Val,
5234 SDValue SelectionDAG::getStore(SDValue Chain, const SDLoc &dl, SDValue Val,
52495235 SDValue Ptr, MachineMemOperand *MMO) {
52505236 assert(Chain.getValueType() == MVT::Other &&
52515237 "Invalid chain type");
52735259 return SDValue(N, 0);
52745260 }
52755261
5276 SDValue SelectionDAG::getTruncStore(SDValue Chain, SDLoc dl, SDValue Val,
5262 SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
52775263 SDValue Ptr, MachinePointerInfo PtrInfo,
5278 EVT SVT,bool isVolatile, bool isNonTemporal,
5279 unsigned Alignment,
5264 EVT SVT, bool isVolatile,
5265 bool isNonTemporal, unsigned Alignment,
52805266 const AAMDNodes &AAInfo) {
52815267 assert(Chain.getValueType() == MVT::Other &&
52825268 "Invalid chain type");
53005286 return getTruncStore(Chain, dl, Val, Ptr, SVT, MMO);
53015287 }
53025288
5303 SDValue SelectionDAG::getTruncStore(SDValue Chain, SDLoc dl, SDValue Val,
5289 SDValue SelectionDAG::getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
53045290 SDValue Ptr, EVT SVT,
53055291 MachineMemOperand *MMO) {
53065292 EVT VT = Val.getValueType();
53435329 return SDValue(N, 0);
53445330 }
53455331
5346 SDValue
5347 SelectionDAG::getIndexedStore(SDValue OrigStore, SDLoc dl, SDValue Base,
5348 SDValue Offset, ISD::MemIndexedMode AM) {
5332 SDValue SelectionDAG::getIndexedStore(SDValue OrigStore, const SDLoc &dl,
5333 SDValue Base, SDValue Offset,
5334 ISD::MemIndexedMode AM) {
53495335 StoreSDNode *ST = cast(OrigStore);
53505336 assert(ST->getOffset().isUndef() && "Store is already a indexed store!");
53515337 SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
53695355 return SDValue(N, 0);
53705356 }
53715357
5372 SDValue
5373 SelectionDAG::getMaskedLoad(EVT VT, SDLoc dl, SDValue Chain,
5374 SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT,
5375 MachineMemOperand *MMO, ISD::LoadExtType ExtTy) {
5358 SDValue SelectionDAG::getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain,
5359 SDValue Ptr, SDValue Mask, SDValue Src0,
5360 EVT MemVT, MachineMemOperand *MMO,
5361 ISD::LoadExtType ExtTy) {
53765362
53775363 SDVTList VTs = getVTList(VT, MVT::Other);
53785364 SDValue Ops[] = { Chain, Ptr, Mask, Src0 };
53985384 return SDValue(N, 0);
53995385 }
54005386
5401 SDValue SelectionDAG::getMaskedStore(SDValue Chain, SDLoc dl, SDValue Val,
5402 SDValue Ptr, SDValue Mask, EVT MemVT,
5403 MachineMemOperand *MMO, bool isTrunc) {
5387 SDValue SelectionDAG::getMaskedStore(SDValue Chain, const SDLoc &dl,
5388 SDValue Val, SDValue Ptr, SDValue Mask,
5389 EVT MemVT, MachineMemOperand *MMO,
5390 bool isTrunc) {
54045391 assert(Chain.getValueType() == MVT::Other &&
54055392 "Invalid chain type");
54065393 EVT VT = Val.getValueType();
54265413 return SDValue(N, 0);
54275414 }
54285415
5429 SDValue
5430 SelectionDAG::getMaskedGather(SDVTList VTs, EVT VT, SDLoc dl,
5431 ArrayRef Ops,
5432 MachineMemOperand *MMO) {
5416 SDValue SelectionDAG::getMaskedGather(SDVTList VTs, EVT VT, const SDLoc &dl,
5417 ArrayRef Ops,
5418 MachineMemOperand *MMO) {
54335419 assert(Ops.size() == 5 && "Incompatible number of operands");
54345420
54355421 FoldingSetNodeID ID;
54645450 return SDValue(N, 0);
54655451 }
54665452
5467 SDValue SelectionDAG::getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl,
5453 SDValue SelectionDAG::getMaskedScatter(SDVTList VTs, EVT VT, const SDLoc &dl,
54685454 ArrayRef Ops,
54695455 MachineMemOperand *MMO) {
54705456 assert(Ops.size() == 5 && "Incompatible number of operands");
54975483 return SDValue(N, 0);
54985484 }
54995485
5500 SDValue SelectionDAG::getVAArg(EVT VT, SDLoc dl,
5501 SDValue Chain, SDValue Ptr,
5502 SDValue SV,
5503 unsigned Align) {
5486 SDValue SelectionDAG::getVAArg(EVT VT, const SDLoc &dl, SDValue Chain,
5487 SDValue Ptr, SDValue SV, unsigned Align) {
55045488 SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, dl, MVT::i32) };
55055489 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops);
55065490 }
55075491
5508 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
5492 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
55095493 ArrayRef Ops) {
55105494 switch (Ops.size()) {
55115495 case 0: return getNode(Opcode, DL, VT);
55215505 return getNode(Opcode, DL, VT, NewOps);
55225506 }
55235507
5524 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT,
5508 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
55255509 ArrayRef Ops, const SDNodeFlags *Flags) {
55265510 unsigned NumOps = Ops.size();
55275511 switch (NumOps) {
55835567 return SDValue(N, 0);
55845568 }
55855569
5586 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL,
5570 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL,
55875571 ArrayRef ResultTys, ArrayRef Ops) {
55885572 return getNode(Opcode, DL, getVTList(ResultTys), Ops);
55895573 }
55905574
5591 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
5575 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
55925576 ArrayRef Ops) {
55935577 if (VTList.NumVTs == 1)
55945578 return getNode(Opcode, DL, VTList.VTs[0], Ops);
56365620 return SDValue(N, 0);
56375621 }
56385622
5639 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList) {
5623 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL,
5624 SDVTList VTList) {
56405625 return getNode(Opcode, DL, VTList, None);
56415626 }
56425627
5643 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
5628 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
56445629 SDValue N1) {
56455630 SDValue Ops[] = { N1 };
56465631 return getNode(Opcode, DL, VTList, Ops);
56475632 }
56485633
5649 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
5634 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
56505635 SDValue N1, SDValue N2) {
56515636 SDValue Ops[] = { N1, N2 };
56525637 return getNode(Opcode, DL, VTList, Ops);
56535638 }
56545639
5655 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
5640 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
56565641 SDValue N1, SDValue N2, SDValue N3) {
56575642 SDValue Ops[] = { N1, N2, N3 };
56585643 return getNode(Opcode, DL, VTList, Ops);
56595644 }
56605645
5661 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
5662 SDValue N1, SDValue N2, SDValue N3,
5663 SDValue N4) {
5646 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
5647 SDValue N1, SDValue N2, SDValue N3, SDValue N4) {
56645648 SDValue Ops[] = { N1, N2, N3, N4 };
56655649 return getNode(Opcode, DL, VTList, Ops);
56665650 }
56675651
5668 SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, SDVTList VTList,
5669 SDValue N1, SDValue N2, SDValue N3,
5670 SDValue N4, SDValue N5) {
5652 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
5653 SDValue N1, SDValue N2, SDValue N3, SDValue N4,
5654 SDValue N5) {
56715655 SDValue Ops[] = { N1, N2, N3, N4, N5 };
56725656 return getNode(Opcode, DL, VTList, Ops);
56735657 }
60786062 /// Note that getMachineNode returns the resultant node. If there is already a
60796063 /// node of the specified opcode and operands, it returns that node instead of
60806064 /// the current one.
6081 MachineSDNode *
6082 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl, EVT VT) {
6065 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6066 EVT VT) {
60836067 SDVTList VTs = getVTList(VT);
60846068 return getMachineNode(Opcode, dl, VTs, None);
60856069 }
60866070
6087 MachineSDNode *
6088 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1) {
6071 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6072 EVT VT, SDValue Op1) {
60896073 SDVTList VTs = getVTList(VT);
60906074 SDValue Ops[] = { Op1 };
60916075 return getMachineNode(Opcode, dl, VTs, Ops);
60926076 }
60936077
6094 MachineSDNode *
6095 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
6096 SDValue Op1, SDValue Op2) {
6078 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6079 EVT VT, SDValue Op1, SDValue Op2) {
60976080 SDVTList VTs = getVTList(VT);
60986081 SDValue Ops[] = { Op1, Op2 };
60996082 return getMachineNode(Opcode, dl, VTs, Ops);
61006083 }
61016084
6102 MachineSDNode *
6103 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
6104 SDValue Op1, SDValue Op2, SDValue Op3) {
6085 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6086 EVT VT, SDValue Op1, SDValue Op2,
6087 SDValue Op3) {
61056088 SDVTList VTs = getVTList(VT);
61066089 SDValue Ops[] = { Op1, Op2, Op3 };
61076090 return getMachineNode(Opcode, dl, VTs, Ops);
61086091 }
61096092
6110 MachineSDNode *
6111 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
6112 ArrayRef Ops) {
6093 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6094 EVT VT, ArrayRef Ops) {
61136095 SDVTList VTs = getVTList(VT);
61146096 return getMachineNode(Opcode, dl, VTs, Ops);
61156097 }
61166098
6117 MachineSDNode *
6118 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2) {
6099 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6100 EVT VT1, EVT VT2) {
61196101 SDVTList VTs = getVTList(VT1, VT2);
61206102 return getMachineNode(Opcode, dl, VTs, None);
61216103 }
61226104
6123 MachineSDNode *
6124 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl,
6125 EVT VT1, EVT VT2, SDValue Op1) {
6105 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6106 EVT VT1, EVT VT2, SDValue Op1) {
61266107 SDVTList VTs = getVTList(VT1, VT2);
61276108 SDValue Ops[] = { Op1 };
61286109 return getMachineNode(Opcode, dl, VTs, Ops);
61296110 }
61306111
6131 MachineSDNode *
6132 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl,
6133 EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) {
6112 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6113 EVT VT1, EVT VT2, SDValue Op1,
6114 SDValue Op2) {
61346115 SDVTList VTs = getVTList(VT1, VT2);
61356116 SDValue Ops[] = { Op1, Op2 };
61366117 return getMachineNode(Opcode, dl, VTs, Ops);
61376118 }
61386119
6139 MachineSDNode *
6140 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl,
6141 EVT VT1, EVT VT2, SDValue Op1,
6142 SDValue Op2, SDValue Op3) {
6120 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6121 EVT VT1, EVT VT2, SDValue Op1,
6122 SDValue Op2, SDValue Op3) {
61436123 SDVTList VTs = getVTList(VT1, VT2);
61446124 SDValue Ops[] = { Op1, Op2, Op3 };
61456125 return getMachineNode(Opcode, dl, VTs, Ops);
61466126 }
61476127
6148 MachineSDNode *
6149 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl,
6150 EVT VT1, EVT VT2,
6151 ArrayRef Ops) {
6128 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6129 EVT VT1, EVT VT2,
6130 ArrayRef Ops) {
61526131 SDVTList VTs = getVTList(VT1, VT2);
61536132 return getMachineNode(Opcode, dl, VTs, Ops);
61546133 }
61556134
6156 MachineSDNode *
6157 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl,
6158 EVT VT1, EVT VT2, EVT VT3,
6159 SDValue Op1, SDValue Op2) {
6135 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6136 EVT VT1, EVT VT2, EVT VT3,
6137 SDValue Op1, SDValue Op2) {
61606138 SDVTList VTs = getVTList(VT1, VT2, VT3);
61616139 SDValue Ops[] = { Op1, Op2 };
61626140 return getMachineNode(Opcode, dl, VTs, Ops);
61636141 }
61646142
6165 MachineSDNode *
6166 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl,
6167 EVT VT1, EVT VT2, EVT VT3,
6168 SDValue Op1, SDValue Op2, SDValue Op3) {
6143 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6144 EVT VT1, EVT VT2, EVT VT3,
6145 SDValue Op1, SDValue Op2,
6146 SDValue Op3) {
61696147 SDVTList VTs = getVTList(VT1, VT2, VT3);
61706148 SDValue Ops[] = { Op1, Op2, Op3 };
61716149 return getMachineNode(Opcode, dl, VTs, Ops);
61726150 }
61736151
6174 MachineSDNode *
6175 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl,
6176 EVT VT1, EVT VT2, EVT VT3,
6177 ArrayRef Ops) {
6152 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6153 EVT VT1, EVT VT2, EVT VT3,
6154 ArrayRef Ops) {
61786155 SDVTList VTs = getVTList(VT1, VT2, VT3);
61796156 return getMachineNode(Opcode, dl, VTs, Ops);
61806157 }
61816158
6182 MachineSDNode *
6183 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1,
6184 EVT VT2, EVT VT3, EVT VT4,
6185 ArrayRef Ops) {
6159 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6160 EVT VT1, EVT VT2, EVT VT3, EVT VT4,
6161 ArrayRef Ops) {
61866162 SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
61876163 return getMachineNode(Opcode, dl, VTs, Ops);
61886164 }
61896165
6190 MachineSDNode *
6191 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc dl,
6192 ArrayRef ResultTys,
6193 ArrayRef Ops) {
6166 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &dl,
6167 ArrayRef ResultTys,
6168 ArrayRef Ops) {
61946169 SDVTList VTs = getVTList(ResultTys);
61956170 return getMachineNode(Opcode, dl, VTs, Ops);
61966171 }
61976172
6198 MachineSDNode *
6199 SelectionDAG::getMachineNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
6200 ArrayRef Ops) {
6173 MachineSDNode *SelectionDAG::getMachineNode(unsigned Opcode, const SDLoc &DL,
6174 SDVTList VTs,
6175 ArrayRef Ops) {
62016176 bool DoCSE = VTs.VTs[VTs.NumVTs-1] != MVT::Glue;
62026177 MachineSDNode *N;
62036178 void *IP = nullptr;
62246199
62256200 /// getTargetExtractSubreg - A convenience function for creating
62266201 /// TargetOpcode::EXTRACT_SUBREG nodes.
6227 SDValue
6228 SelectionDAG::getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT,
6229 SDValue Operand) {
6202 SDValue SelectionDAG::getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
6203 SDValue Operand) {
62306204 SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32);
62316205 SDNode *Subreg = getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
62326206 VT, Operand, SRIdxVal);
62356209
62366210 /// getTargetInsertSubreg - A convenience function for creating
62376211 /// TargetOpcode::INSERT_SUBREG nodes.
6238 SDValue
6239 SelectionDAG::getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT,
6240 SDValue Operand, SDValue Subreg) {
6212 SDValue SelectionDAG::getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
6213 SDValue Operand, SDValue Subreg) {
62416214 SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32);
62426215 SDNode *Result = getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
62436216 VT, Operand, Subreg, SRIdxVal);
62676240 /// SDNode
62686241 SDDbgValue *SelectionDAG::getDbgValue(MDNode *Var, MDNode *Expr, SDNode *N,
62696242 unsigned R, bool IsIndirect, uint64_t Off,
6270 DebugLoc DL, unsigned O) {
6243 const DebugLoc &DL, unsigned O) {
62716244 assert(cast(Var)->isValidLocationForIntrinsic(DL) &&
62726245 "Expected inlined-at fields to agree");
62736246 return new (DbgInfo->getAlloc())
62776250 /// Constant
62786251 SDDbgValue *SelectionDAG::getConstantDbgValue(MDNode *Var, MDNode *Expr,
62796252 const Value *C, uint64_t Off,
6280 DebugLoc DL, unsigned O) {
6253 const DebugLoc &DL, unsigned O) {
62816254 assert(cast(Var)->isValidLocationForIntrinsic(DL) &&
62826255 "Expected inlined-at fields to agree");
62836256 return new (DbgInfo->getAlloc()) SDDbgValue(Var, Expr, C, Off, DL, O);
62866259 /// FrameIndex
62876260 SDDbgValue *SelectionDAG::getFrameIndexDbgValue(MDNode *Var, MDNode *Expr,
62886261 unsigned FI, uint64_t Off,
6289 DebugLoc DL, unsigned O) {
6262 const DebugLoc &DL,
6263 unsigned O) {
62906264 assert(cast(Var)->isValidLocationForIntrinsic(DL) &&
62916265 "Expected inlined-at fields to agree");
62926266 return new (DbgInfo->getAlloc()) SDDbgValue(Var, Expr, FI, Off, DL, O);
67436717 }
67446718
67456719 GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, unsigned Order,
6746 DebugLoc DL, const GlobalValue *GA,
6747 EVT VT, int64_t o, unsigned char TF)
6748 : SDNode(Opc, Order, DL, getSDVTList(VT)), Offset(o), TargetFlags(TF) {
6720 const DebugLoc &DL,
6721 const GlobalValue *GA, EVT VT,
6722 int64_t o, unsigned char TF)
6723 : SDNode(Opc, Order, DL, getSDVTList(VT)), Offset(o), TargetFlags(TF) {
67496724 TheGlobal = GA;
67506725 }
67516726
6752 AddrSpaceCastSDNode::AddrSpaceCastSDNode(unsigned Order, DebugLoc dl, EVT VT,
6753 unsigned SrcAS, unsigned DestAS)
6727 AddrSpaceCastSDNode::AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl,
6728 EVT VT, unsigned SrcAS,
6729 unsigned DestAS)
67546730 : SDNode(ISD::ADDRSPACECAST, Order, dl, getSDVTList(VT)),
67556731 SrcAddrSpace(SrcAS), DestAddrSpace(DestAS) {}
67566732
6757 MemSDNode::MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
6758 EVT memvt, MachineMemOperand *mmo)
6759 : SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
6733 MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
6734 SDVTList VTs, EVT memvt, MachineMemOperand *mmo)
6735 : SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
67606736 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(),
67616737 MMO->isNonTemporal(), MMO->isInvariant());
67626738 assert(isVolatile() == MMO->isVolatile() && "Volatile encoding error!");
114114 // store [4096 x i8] %data, [4096 x i8]* %buffer
115115 static const unsigned MaxParallelChains = 64;
116116
117 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
117 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
118118 const SDValue *Parts, unsigned NumParts,
119119 MVT PartVT, EVT ValueVT, const Value *V);
120120
123123 /// larger than ValueVT then AssertOp can be used to specify whether the extra
124124 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
125125 /// (ISD::AssertSext).
126 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
127 const SDValue *Parts,
128 unsigned NumParts, MVT PartVT, EVT ValueVT,
129 const Value *V,
126 static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
127 const SDValue *Parts, unsigned NumParts,
128 MVT PartVT, EVT ValueVT, const Value *V,
130129 Optional AssertOp = None) {
131130 if (ValueVT.isVector())
132131 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
272271 /// type larger than ValueVT then AssertOp can be used to specify whether the
273272 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
274273 /// ValueVT (ISD::AssertSext).
275 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
274 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
276275 const SDValue *Parts, unsigned NumParts,
277276 MVT PartVT, EVT ValueVT, const Value *V) {
278277 assert(ValueVT.isVector() && "Not a vector value");
371370 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
372371 }
373372
374 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
373 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
375374 SDValue Val, SDValue *Parts, unsigned NumParts,
376375 MVT PartVT, const Value *V);
377376
378377 /// getCopyToParts - Create a series of nodes that contain the specified value
379378 /// split into legal parts. If the parts contain more bits than Val, then, for
380379 /// integers, ExtendKind can be used to specify how to generate the extra bits.
381 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
382 SDValue Val, SDValue *Parts, unsigned NumParts,
383 MVT PartVT, const Value *V,
380 static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
381 SDValue *Parts, unsigned NumParts, MVT PartVT,
382 const Value *V,
384383 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
385384 EVT ValueVT = Val.getValueType();
386385
507506
508507 /// getCopyToPartsVector - Create a series of nodes that contain the specified
509508 /// value split into legal parts.
510 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
509 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
511510 SDValue Val, SDValue *Parts, unsigned NumParts,
512511 MVT PartVT, const Value *V) {
513512 EVT ValueVT = Val.getValueType();
636635 /// If the Flag pointer is NULL, no flag is used.
637636 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
638637 FunctionLoweringInfo &FuncInfo,
639 SDLoc dl,
640 SDValue &Chain, SDValue *Flag,
641 const Value *V) const {
638 const SDLoc &dl, SDValue &Chain,
639 SDValue *Flag, const Value *V) const {
642640 // A Value with type {} or [0 x %t] needs no registers.
643641 if (ValueVTs.empty())
644642 return SDValue();
740738 /// specified value into the registers specified by this object. This uses
741739 /// Chain/Flag as the input and updates them for the output Chain/Flag.
742740 /// If the Flag pointer is NULL, no flag is used.
743 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,