llvm.org GIT mirror llvm / aeef83c
Switch TargetTransformInfo from an immutable analysis pass that requires a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8 Chandler Carruth 6 years ago
47 changed file(s) with 1120 addition(s) and 1205 deletion(s). Raw diff Collapse all Expand all
279279
280280 /// List of target independent CodeGen pass IDs.
281281 namespace llvm {
282 /// \brief Create a basic TargetTransformInfo analysis pass.
283 ///
284 /// This pass implements the target transform info analysis using the target
285 /// independent information available to the LLVM code generator.
286 ImmutablePass *createBasicTargetTransformInfoPass(const TargetLowering *TLI);
287
282288 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
283289 /// work well with unreachable basic blocks (what live ranges make sense for a
284290 /// block that cannot be reached?). As such, a code generator should either
6868 void initializeBarrierNoopPass(PassRegistry&);
6969 void initializeBasicAliasAnalysisPass(PassRegistry&);
7070 void initializeBasicCallGraphPass(PassRegistry&);
71 void initializeBasicTTIPass(PassRegistry&);
7172 void initializeBlockExtractorPassPass(PassRegistry&);
7273 void initializeBlockFrequencyInfoPass(PassRegistry&);
7374 void initializeBlockPlacementPass(PassRegistry&);
894894 }
895895
896896 //===--------------------------------------------------------------------===//
897 /// \name Helpers for TargetTransformInfo implementations
898 /// @{
899
900 /// Get the ISD node that corresponds to the Instruction class opcode.
901 int InstructionOpcodeToISD(unsigned Opcode) const;
902
903 /// Estimate the cost of type-legalization and the legalized type.
904 std::pair getTypeLegalizationCost(Type *Ty) const;
905
906 /// @}
907
908 //===--------------------------------------------------------------------===//
897909 // TargetLowering Optimization Methods
898910 //
899911
107107 virtual const TargetLowering *getTargetLowering() const { return 0; }
108108 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
109109 virtual const DataLayout *getDataLayout() const { return 0; }
110 virtual const ScalarTargetTransformInfo*
111 getScalarTargetTransformInfo() const { return 0; }
112 virtual const VectorTargetTransformInfo*
113 getVectorTargetTransformInfo() const { return 0; }
114110
115111 /// getMCAsmInfo - Return target specific asm information.
116112 ///
230226 /// setFunctionSections - Set if the functions are emit into separate
231227 /// sections.
232228 static void setFunctionSections(bool);
229
230 /// \brief Register analysis passes for this target with a pass manager.
231 virtual void addAnalysisPasses(PassManagerBase &) {}
233232
234233 /// CodeGenFileType - These enums are meant to be passed into
235234 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
289288 CodeGenOpt::Level OL);
290289
291290 public:
291 /// \brief Register analysis passes for this target with a pass manager.
292 ///
293 /// This registers target independent analysis passes.
294 virtual void addAnalysisPasses(PassManagerBase &PM);
295
292296 /// createPassConfig - Create a pass configuration object to be used by
293297 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
294298 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
+0
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include/llvm/Target/TargetTransformImpl.h less more
None //=- llvm/Target/TargetTransformImpl.h - Target Loop Trans Info----*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the target-specific implementations of the
10 // TargetTransform interfaces.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_TARGET_TARGET_TRANSFORMATION_IMPL_H
15 #define LLVM_TARGET_TARGET_TRANSFORMATION_IMPL_H
16
17 #include "llvm/CodeGen/ValueTypes.h"
18 #include "llvm/TargetTransformInfo.h"
19
20 namespace llvm {
21
22 class TargetLowering;
23
24 /// ScalarTargetTransformInfo - This is a default implementation for the
25 /// ScalarTargetTransformInfo interface. Different targets can implement
26 /// this interface differently.
27 class ScalarTargetTransformImpl : public ScalarTargetTransformInfo {
28 protected:
29 const TargetLowering *TLI;
30
31 public:
32 /// Ctor
33 explicit ScalarTargetTransformImpl(const TargetLowering *TL) : TLI(TL) {}
34
35 virtual bool isLegalAddImmediate(int64_t imm) const;
36
37 virtual bool isLegalICmpImmediate(int64_t imm) const;
38
39 virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
40 int64_t BaseOffset, bool HasBaseReg,
41 int64_t Scale) const;
42
43 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
44
45 virtual bool isTypeLegal(Type *Ty) const;
46
47 virtual unsigned getJumpBufAlignment() const;
48
49 virtual unsigned getJumpBufSize() const;
50
51 virtual bool shouldBuildLookupTables() const;
52 };
53
54 class VectorTargetTransformImpl : public VectorTargetTransformInfo {
55 protected:
56 const TargetLowering *TLI;
57
58 /// Estimate the cost of type-legalization and the legalized type.
59 std::pair getTypeLegalizationCost(Type *Ty) const;
60
61 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
62 /// are set if the result needs to be inserted and/or extracted from vectors.
63 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
64
65 // Get the ISD node that corresponds to the Instruction class opcode.
66 int InstructionOpcodeToISD(unsigned Opcode) const;
67
68 public:
69 explicit VectorTargetTransformImpl(const TargetLowering *TL) : TLI(TL) {}
70
71 virtual ~VectorTargetTransformImpl() {}
72
73 virtual unsigned getNumberOfRegisters(bool Vector) const;
74
75 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
76
77 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
78 int Index, Type *SubTp) const;
79
80 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
81 Type *Src) const;
82
83 virtual unsigned getCFInstrCost(unsigned Opcode) const;
84
85 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
86 Type *CondTy) const;
87
88 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
89 unsigned Index) const;
90
91 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
92 unsigned Alignment,
93 unsigned AddressSpace) const;
94
95 virtual unsigned getIntrinsicInstrCost(Intrinsic::ID, Type *RetTy,
96 ArrayRef Tys) const;
97
98 virtual unsigned getNumberOfParts(Type *Tp) const;
99 };
100
101 } // end llvm namespace
102
103 #endif
2828 #include "llvm/Support/DataTypes.h"
2929
3030 namespace llvm {
31
32 class ScalarTargetTransformInfo;
33 class VectorTargetTransformInfo;
3431
3532 /// TargetTransformInfo - This pass provides access to the codegen
3633 /// interfaces that are needed for IR-level transformations.
4138 /// This is used to implement the default behavior all of the methods which
4239 /// is to delegate up through the stack of TTIs until one can answer the
4340 /// query.
44 const TargetTransformInfo *PrevTTI;
45
46 /// Every subclass must initialize the base with the previous TTI in the
47 /// stack, or 0 if there is no previous TTI in the stack.
48 TargetTransformInfo(const TargetTransformInfo *PrevTTI) : PrevTTI(PrevTTI) {}
41 TargetTransformInfo *PrevTTI;
42
43 /// \brief The top of the stack of TTI analyses available.
44 ///
45 /// This is a convenience routine maintained as TTI analyses become available
46 /// that complements the PrevTTI delegation chain. When one part of an
47 /// analysis pass wants to query another part of the analysis pass it can use
48 /// this to start back at the top of the stack.
49 TargetTransformInfo *TopTTI;
50
51 /// All pass subclasses must in their initializePass routine call
52 /// pushTTIStack with themselves to update the pointers tracking the previous
53 /// TTI instance in the analysis group's stack, and the top of the analysis
54 /// group's stack.
55 void pushTTIStack(Pass *P);
56
57 /// All pass subclasses must in their finalizePass routine call popTTIStack
58 /// to update the pointers tracking the previous TTI instance in the analysis
59 /// group's stack, and the top of the analysis group's stack.
60 void popTTIStack();
4961
5062 /// All pass subclasses must call TargetTransformInfo::getAnalysisUsage.
5163 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
183195 /// This class provides the base case for the stack of TTI analyses. It doesn't
184196 /// delegate to anything and uses the STTI and VTTI objects passed in to
185197 /// satisfy the queries.
186 ImmutablePass *createNoTTIPass(const ScalarTargetTransformInfo *S,
187 const VectorTargetTransformInfo *V);
188
189
190 // ---------------------------------------------------------------------------//
191 // The classes below are inherited and implemented by target-specific classes
192 // in the codegen.
193 // ---------------------------------------------------------------------------//
194
195 /// ScalarTargetTransformInfo - This interface is used by IR-level passes
196 /// that need target-dependent information for generic scalar transformations.
197 /// LSR, and LowerInvoke use this interface.
198 class ScalarTargetTransformInfo {
199 public:
200 /// PopcntHwSupport - Hardware support for population count. Compared to the
201 /// SW implementation, HW support is supposed to significantly boost the
202 /// performance when the population is dense, and it may or may not degrade
203 /// performance if the population is sparse. A HW support is considered as
204 /// "Fast" if it can outperform, or is on a par with, SW implementaion when
205 /// the population is sparse; otherwise, it is considered as "Slow".
206 enum PopcntHwSupport {
207 None,
208 Fast,
209 Slow
210 };
211
212 virtual ~ScalarTargetTransformInfo() {}
213
214 /// isLegalAddImmediate - Return true if the specified immediate is legal
215 /// add immediate, that is the target has add instructions which can add
216 /// a register with the immediate without having to materialize the
217 /// immediate into a register.
218 virtual bool isLegalAddImmediate(int64_t) const {
219 return false;
220 }
221 /// isLegalICmpImmediate - Return true if the specified immediate is legal
222 /// icmp immediate, that is the target has icmp instructions which can compare
223 /// a register against the immediate without having to materialize the
224 /// immediate into a register.
225 virtual bool isLegalICmpImmediate(int64_t) const {
226 return false;
227 }
228 /// isLegalAddressingMode - Return true if the addressing mode represented by
229 /// AM is legal for this target, for a load/store of the specified type.
230 /// The type may be VoidTy, in which case only return true if the addressing
231 /// mode is legal for a load/store of any legal type.
232 /// TODO: Handle pre/postinc as well.
233 virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
234 int64_t BaseOffset, bool HasBaseReg,
235 int64_t Scale) const {
236 return false;
237 }
238 /// isTruncateFree - Return true if it's free to truncate a value of
239 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
240 /// register EAX to i16 by referencing its sub-register AX.
241 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const {
242 return false;
243 }
244 /// Is this type legal.
245 virtual bool isTypeLegal(Type *Ty) const {
246 return false;
247 }
248 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
249 virtual unsigned getJumpBufAlignment() const {
250 return 0;
251 }
252 /// getJumpBufSize - returns the target's jmp_buf size in bytes.
253 virtual unsigned getJumpBufSize() const {
254 return 0;
255 }
256 /// shouldBuildLookupTables - Return true if switches should be turned into
257 /// lookup tables for the target.
258 virtual bool shouldBuildLookupTables() const {
259 return true;
260 }
261 /// getPopcntHwSupport - Return hardware support for population count.
262 virtual PopcntHwSupport getPopcntHwSupport(unsigned IntTyWidthInBit) const {
263 return None;
264 }
265 /// getIntImmCost - Return the expected cost of materializing the given
266 /// integer immediate of the specified type.
267 virtual unsigned getIntImmCost(const APInt&, Type*) const {
268 // The default assumption is that the immediate is cheap.
269 return 1;
270 }
271 };
272
273 /// VectorTargetTransformInfo - This interface is used by the vectorizers
274 /// to estimate the profitability of vectorization for different instructions.
275 /// This interface provides the cost of different IR instructions. The cost
276 /// is unit-less and represents the estimated throughput of the instruction
277 /// (not the latency!) assuming that all branches are predicted, cache is hit,
278 /// etc.
279 class VectorTargetTransformInfo {
280 public:
281 virtual ~VectorTargetTransformInfo() {}
282
283 enum ShuffleKind {
284 Broadcast, // Broadcast element 0 to all other elements.
285 Reverse, // Reverse the order of the vector.
286 InsertSubvector, // InsertSubvector. Index indicates start offset.
287 ExtractSubvector // ExtractSubvector Index indicates start offset.
288 };
289
290 /// \return The number of scalar or vector registers that the target has.
291 /// If 'Vectors' is true, it returns the number of vector registers. If it is
292 /// set to false, it returns the number of scalar registers.
293 virtual unsigned getNumberOfRegisters(bool Vector) const {
294 return 8;
295 }
296
297 /// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
298 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const {
299 return 1;
300 }
301
302 /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
303 /// The index and subtype parameters are used by the subvector insertion and
304 /// extraction shuffle kinds.
305 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
306 int Index = 0, Type *SubTp = 0) const {
307 return 1;
308 }
309
310 /// \return The expected cost of cast instructions, such as bitcast, trunc,
311 /// zext, etc.
312 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
313 Type *Src) const {
314 return 1;
315 }
316
317 /// \return The expected cost of control-flow related instrutctions such as
318 /// Phi, Ret, Br.
319 virtual unsigned getCFInstrCost(unsigned Opcode) const {
320 return 1;
321 }
322
323 /// \returns The expected cost of compare and select instructions.
324 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
325 Type *CondTy = 0) const {
326 return 1;
327 }
328
329 /// \return The expected cost of vector Insert and Extract.
330 /// Use -1 to indicate that there is no information on the index value.
331 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
332 unsigned Index = -1) const {
333 return 1;
334 }
335
336 /// \return The cost of Load and Store instructions.
337 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
338 unsigned Alignment,
339 unsigned AddressSpace) const {
340 return 1;
341 }
342
343 /// \returns The cost of Intrinsic instructions.
344 virtual unsigned getIntrinsicInstrCost(Intrinsic::ID,
345 Type *RetTy,
346 ArrayRef Tys) const {
347 return 1;
348 }
349
350 /// \returns The number of pieces into which the provided type must be
351 /// split during legalization. Zero is returned when the answer is unknown.
352 virtual unsigned getNumberOfParts(Type *Tp) const {
353 return 0;
354 }
355 };
356
198 ImmutablePass *createNoTargetTransformInfoPass();
357199
358200 } // End llvm namespace
359201
0 //===- BasicTargetTransformInfo.cpp - Basic target-independent TTI impl ---===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file provides the implementation of a basic TargetTransformInfo pass
10 /// predicated on the target abstractions present in the target independent
11 /// code generator. It uses these (primarily TargetLowering) to model as much
12 /// of the TTI query interface as possible. It is included by most targets so
13 /// that they can specialize only a small subset of the query space.
14 ///
15 //===----------------------------------------------------------------------===//
16
17 #define DEBUG_TYPE "basictti"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/TargetTransformInfo.h"
21 #include
22
23 using namespace llvm;
24
25 namespace {
26
27 class BasicTTI : public ImmutablePass, public TargetTransformInfo {
28 const TargetLowering *TLI;
29
30 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
31 /// are set if the result needs to be inserted and/or extracted from vectors.
32 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
33
34 public:
35 BasicTTI() : ImmutablePass(ID), TLI(0) {
36 llvm_unreachable("This pass cannot be directly constructed");
37 }
38
39 BasicTTI(const TargetLowering *TLI) : ImmutablePass(ID), TLI(TLI) {
40 initializeBasicTTIPass(*PassRegistry::getPassRegistry());
41 }
42
43 virtual void initializePass() {
44 pushTTIStack(this);
45 }
46
47 virtual void finalizePass() {
48 popTTIStack();
49 }
50
51 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
52 TargetTransformInfo::getAnalysisUsage(AU);
53 }
54
55 /// Pass identification.
56 static char ID;
57
58 /// Provide necessary pointer adjustments for the two base classes.
59 virtual void *getAdjustedAnalysisPointer(const void *ID) {
60 if (ID == &TargetTransformInfo::ID)
61 return (TargetTransformInfo*)this;
62 return this;
63 }
64
65 /// \name Scalar TTI Implementations
66 /// @{
67
68 virtual bool isLegalAddImmediate(int64_t imm) const;
69 virtual bool isLegalICmpImmediate(int64_t imm) const;
70 virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
71 int64_t BaseOffset, bool HasBaseReg,
72 int64_t Scale) const;
73 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
74 virtual bool isTypeLegal(Type *Ty) const;
75 virtual unsigned getJumpBufAlignment() const;
76 virtual unsigned getJumpBufSize() const;
77 virtual bool shouldBuildLookupTables() const;
78
79 /// @}
80
81 /// \name Vector TTI Implementations
82 /// @{
83
84 virtual unsigned getNumberOfRegisters(bool Vector) const;
85 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
86 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
87 int Index, Type *SubTp) const;
88 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
89 Type *Src) const;
90 virtual unsigned getCFInstrCost(unsigned Opcode) const;
91 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
92 Type *CondTy) const;
93 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
94 unsigned Index) const;
95 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
96 unsigned Alignment,
97 unsigned AddressSpace) const;
98 virtual unsigned getIntrinsicInstrCost(Intrinsic::ID, Type *RetTy,
99 ArrayRef Tys) const;
100 virtual unsigned getNumberOfParts(Type *Tp) const;
101
102 /// @}
103 };
104
105 }
106
107 INITIALIZE_AG_PASS(BasicTTI, TargetTransformInfo, "basictti",
108 "Target independent code generator's TTI", true, true, false)
109 char BasicTTI::ID = 0;
110
111 ImmutablePass *
112 llvm::createBasicTargetTransformInfoPass(const TargetLowering *TLI) {
113 return new BasicTTI(TLI);
114 }
115
116
117 bool BasicTTI::isLegalAddImmediate(int64_t imm) const {
118 return TLI->isLegalAddImmediate(imm);
119 }
120
121 bool BasicTTI::isLegalICmpImmediate(int64_t imm) const {
122 return TLI->isLegalICmpImmediate(imm);
123 }
124
125 bool BasicTTI::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
126 int64_t BaseOffset, bool HasBaseReg,
127 int64_t Scale) const {
128 AddrMode AM;
129 AM.BaseGV = BaseGV;
130 AM.BaseOffs = BaseOffset;
131 AM.HasBaseReg = HasBaseReg;
132 AM.Scale = Scale;
133 return TLI->isLegalAddressingMode(AM, Ty);
134 }
135
136 bool BasicTTI::isTruncateFree(Type *Ty1, Type *Ty2) const {
137 return TLI->isTruncateFree(Ty1, Ty2);
138 }
139
140 bool BasicTTI::isTypeLegal(Type *Ty) const {
141 EVT T = TLI->getValueType(Ty);
142 return TLI->isTypeLegal(T);
143 }
144
145 unsigned BasicTTI::getJumpBufAlignment() const {
146 return TLI->getJumpBufAlignment();
147 }
148
149 unsigned BasicTTI::getJumpBufSize() const {
150 return TLI->getJumpBufSize();
151 }
152
153 bool BasicTTI::shouldBuildLookupTables() const {
154 return TLI->supportJumpTables() &&
155 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
156 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
157 }
158
159 //===----------------------------------------------------------------------===//
160 //
161 // Calls used by the vectorizers.
162 //
163 //===----------------------------------------------------------------------===//
164
165 unsigned BasicTTI::getScalarizationOverhead(Type *Ty, bool Insert,
166 bool Extract) const {
167 assert (Ty->isVectorTy() && "Can only scalarize vectors");
168 unsigned Cost = 0;
169
170 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
171 if (Insert)
172 Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i);
173 if (Extract)
174 Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i);
175 }
176
177 return Cost;
178 }
179
180 unsigned BasicTTI::getNumberOfRegisters(bool Vector) const {
181 return 1;
182 }
183
184 unsigned BasicTTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty) const {
185 // Check if any of the operands are vector operands.
186 int ISD = TLI->InstructionOpcodeToISD(Opcode);
187 assert(ISD && "Invalid opcode");
188
189 std::pair LT = TLI->getTypeLegalizationCost(Ty);
190
191 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
192 // The operation is legal. Assume it costs 1.
193 // If the type is split to multiple registers, assume that thre is some
194 // overhead to this.
195 // TODO: Once we have extract/insert subvector cost we need to use them.
196 if (LT.first > 1)
197 return LT.first * 2;
198 return LT.first * 1;
199 }
200
201 if (!TLI->isOperationExpand(ISD, LT.second)) {
202 // If the operation is custom lowered then assume
203 // thare the code is twice as expensive.
204 return LT.first * 2;
205 }
206
207 // Else, assume that we need to scalarize this op.
208 if (Ty->isVectorTy()) {
209 unsigned Num = Ty->getVectorNumElements();
210 unsigned Cost = TopTTI->getArithmeticInstrCost(Opcode, Ty->getScalarType());
211 // return the cost of multiple scalar invocation plus the cost of inserting
212 // and extracting the values.
213 return getScalarizationOverhead(Ty, true, true) + Num * Cost;
214 }
215
216 // We don't know anything about this scalar instruction.
217 return 1;
218 }
219
220 unsigned BasicTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
221 Type *SubTp) const {
222 return 1;
223 }
224
225 unsigned BasicTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
226 Type *Src) const {
227 int ISD = TLI->InstructionOpcodeToISD(Opcode);
228 assert(ISD && "Invalid opcode");
229
230 std::pair SrcLT = TLI->getTypeLegalizationCost(Src);
231 std::pair DstLT = TLI->getTypeLegalizationCost(Dst);
232
233 // Handle scalar conversions.
234 if (!Src->isVectorTy() && !Dst->isVectorTy()) {
235
236 // Scalar bitcasts are usually free.
237 if (Opcode == Instruction::BitCast)
238 return 0;
239
240 if (Opcode == Instruction::Trunc &&
241 TLI->isTruncateFree(SrcLT.second, DstLT.second))
242 return 0;
243
244 if (Opcode == Instruction::ZExt &&
245 TLI->isZExtFree(SrcLT.second, DstLT.second))
246 return 0;
247
248 // Just check the op cost. If the operation is legal then assume it costs 1.
249 if (!TLI->isOperationExpand(ISD, DstLT.second))
250 return 1;
251
252 // Assume that illegal scalar instruction are expensive.
253 return 4;
254 }
255
256 // Check vector-to-vector casts.
257 if (Dst->isVectorTy() && Src->isVectorTy()) {
258
259 // If the cast is between same-sized registers, then the check is simple.
260 if (SrcLT.first == DstLT.first &&
261 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
262
263 // Bitcast between types that are legalized to the same type are free.
264 if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
265 return 0;
266
267 // Assume that Zext is done using AND.
268 if (Opcode == Instruction::ZExt)
269 return 1;
270
271 // Assume that sext is done using SHL and SRA.
272 if (Opcode == Instruction::SExt)
273 return 2;
274
275 // Just check the op cost. If the operation is legal then assume it costs
276 // 1 and multiply by the type-legalization overhead.
277 if (!TLI->isOperationExpand(ISD, DstLT.second))
278 return SrcLT.first * 1;
279 }
280
281 // If we are converting vectors and the operation is illegal, or
282 // if the vectors are legalized to different types, estimate the
283 // scalarization costs.
284 unsigned Num = Dst->getVectorNumElements();
285 unsigned Cost = TopTTI->getCastInstrCost(Opcode, Dst->getScalarType(),
286 Src->getScalarType());
287
288 // Return the cost of multiple scalar invocation plus the cost of
289 // inserting and extracting the values.
290 return getScalarizationOverhead(Dst, true, true) + Num * Cost;
291 }
292
293 // We already handled vector-to-vector and scalar-to-scalar conversions. This
294 // is where we handle bitcast between vectors and scalars. We need to assume
295 // that the conversion is scalarized in one way or another.
296 if (Opcode == Instruction::BitCast)
297 // Illegal bitcasts are done by storing and loading from a stack slot.
298 return (Src->isVectorTy()? getScalarizationOverhead(Src, false, true):0) +
299 (Dst->isVectorTy()? getScalarizationOverhead(Dst, true, false):0);
300
301 llvm_unreachable("Unhandled cast");
302 }
303
304 unsigned BasicTTI::getCFInstrCost(unsigned Opcode) const {
305 // Branches are assumed to be predicted.
306 return 0;
307 }
308
309 unsigned BasicTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
310 Type *CondTy) const {
311 int ISD = TLI->InstructionOpcodeToISD(Opcode);
312 assert(ISD && "Invalid opcode");
313
314 // Selects on vectors are actually vector selects.
315 if (ISD == ISD::SELECT) {
316 assert(CondTy && "CondTy must exist");
317 if (CondTy->isVectorTy())
318 ISD = ISD::VSELECT;
319 }
320
321 std::pair LT = TLI->getTypeLegalizationCost(ValTy);
322
323 if (!TLI->isOperationExpand(ISD, LT.second)) {
324 // The operation is legal. Assume it costs 1. Multiply
325 // by the type-legalization overhead.
326 return LT.first * 1;
327 }
328
329 // Otherwise, assume that the cast is scalarized.
330 if (ValTy->isVectorTy()) {
331 unsigned Num = ValTy->getVectorNumElements();
332 if (CondTy)
333 CondTy = CondTy->getScalarType();
334 unsigned Cost = TopTTI->getCmpSelInstrCost(Opcode, ValTy->getScalarType(),
335 CondTy);
336
337 // Return the cost of multiple scalar invocation plus the cost of inserting
338 // and extracting the values.
339 return getScalarizationOverhead(ValTy, true, false) + Num * Cost;
340 }
341
342 // Unknown scalar opcode.
343 return 1;
344 }
345
346 unsigned BasicTTI::getVectorInstrCost(unsigned Opcode, Type *Val,
347 unsigned Index) const {
348 return 1;
349 }
350
351 unsigned BasicTTI::getMemoryOpCost(unsigned Opcode, Type *Src,
352 unsigned Alignment,
353 unsigned AddressSpace) const {
354 assert(!Src->isVoidTy() && "Invalid type");
355 std::pair LT = TLI->getTypeLegalizationCost(Src);
356
357 // Assume that all loads of legal types cost 1.
358 return LT.first;
359 }
360
361 unsigned BasicTTI::getIntrinsicInstrCost(Intrinsic::ID, Type *RetTy,
362 ArrayRef Tys) const {
363 // assume that we need to scalarize this intrinsic.
364 unsigned ScalarizationCost = 0;
365 unsigned ScalarCalls = 1;
366 if (RetTy->isVectorTy()) {
367 ScalarizationCost = getScalarizationOverhead(RetTy, true, false);
368 ScalarCalls = std::max(ScalarCalls, RetTy->getVectorNumElements());
369 }
370 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
371 if (Tys[i]->isVectorTy()) {
372 ScalarizationCost += getScalarizationOverhead(Tys[i], false, true);
373 ScalarCalls = std::max(ScalarCalls, RetTy->getVectorNumElements());
374 }
375 }
376 return ScalarCalls + ScalarizationCost;
377 }
378
379 unsigned BasicTTI::getNumberOfParts(Type *Tp) const {
380 std::pair LT = TLI->getTypeLegalizationCost(Tp);
381 return LT.first;
382 }
11 AggressiveAntiDepBreaker.cpp
22 AllocationOrder.cpp
33 Analysis.cpp
4 BasicTargetTransformInfo.cpp
45 BranchFolding.cpp
56 CalcSpillWeights.cpp
67 CallingConvLower.cpp
1818
1919 /// initializeCodeGen - Initialize all passes linked into the CodeGen library.
2020 void llvm::initializeCodeGen(PassRegistry &Registry) {
21 initializeBasicTTIPass(Registry);
2122 initializeBranchFolderPassPass(Registry);
2223 initializeCalculateSpillWeightsPass(Registry);
2324 initializeCodePlacementOptPass(Registry);
7878 "and that InitializeAllTargetMCs() is being invoked!");
7979 }
8080
81 void LLVMTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
82 PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
83 }
84
8185 /// addPassesToX helper drives creation and initialization of TargetPassConfig.
8286 static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
8387 PassManagerBase &PM,
10981098 }
10991099
11001100 //===----------------------------------------------------------------------===//
1101 // TargetTransformInfo Helpers
1102 //===----------------------------------------------------------------------===//
1103
1104 int TargetLowering::InstructionOpcodeToISD(unsigned Opcode) const {
1105 enum InstructionOpcodes {
1106 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1107 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1108 #include "llvm/IR/Instruction.def"
1109 };
1110 switch (static_cast(Opcode)) {
1111 case Ret: return 0;
1112 case Br: return 0;
1113 case Switch: return 0;
1114 case IndirectBr: return 0;
1115 case Invoke: return 0;
1116 case Resume: return 0;
1117 case Unreachable: return 0;
1118 case Add: return ISD::ADD;
1119 case FAdd: return ISD::FADD;
1120 case Sub: return ISD::SUB;
1121 case FSub: return ISD::FSUB;
1122 case Mul: return ISD::MUL;
1123 case FMul: return ISD::FMUL;
1124 case UDiv: return ISD::UDIV;
1125 case SDiv: return ISD::UDIV;
1126 case FDiv: return ISD::FDIV;
1127 case URem: return ISD::UREM;
1128 case SRem: return ISD::SREM;
1129 case FRem: return ISD::FREM;
1130 case Shl: return ISD::SHL;
1131 case LShr: return ISD::SRL;
1132 case AShr: return ISD::SRA;
1133 case And: return ISD::AND;
1134 case Or: return ISD::OR;
1135 case Xor: return ISD::XOR;
1136 case Alloca: return 0;
1137 case Load: return ISD::LOAD;
1138 case Store: return ISD::STORE;
1139 case GetElementPtr: return 0;
1140 case Fence: return 0;
1141 case AtomicCmpXchg: return 0;
1142 case AtomicRMW: return 0;
1143 case Trunc: return ISD::TRUNCATE;
1144 case ZExt: return ISD::ZERO_EXTEND;
1145 case SExt: return ISD::SIGN_EXTEND;
1146 case FPToUI: return ISD::FP_TO_UINT;
1147 case FPToSI: return ISD::FP_TO_SINT;
1148 case UIToFP: return ISD::UINT_TO_FP;
1149 case SIToFP: return ISD::SINT_TO_FP;
1150 case FPTrunc: return ISD::FP_ROUND;
1151 case FPExt: return ISD::FP_EXTEND;
1152 case PtrToInt: return ISD::BITCAST;
1153 case IntToPtr: return ISD::BITCAST;
1154 case BitCast: return ISD::BITCAST;
1155 case ICmp: return ISD::SETCC;
1156 case FCmp: return ISD::SETCC;
1157 case PHI: return 0;
1158 case Call: return 0;
1159 case Select: return ISD::SELECT;
1160 case UserOp1: return 0;
1161 case UserOp2: return 0;
1162 case VAArg: return 0;
1163 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1164 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1165 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1166 case ExtractValue: return ISD::MERGE_VALUES;
1167 case InsertValue: return ISD::MERGE_VALUES;
1168 case LandingPad: return 0;
1169 }
1170
1171 llvm_unreachable("Unknown instruction type encountered!");
1172 }
1173
1174 std::pair
1175 TargetLowering::getTypeLegalizationCost(Type *Ty) const {
1176 LLVMContext &C = Ty->getContext();
1177 EVT MTy = getValueType(Ty);
1178
1179 unsigned Cost = 1;
1180 // We keep legalizing the type until we find a legal kind. We assume that
1181 // the only operation that costs anything is the split. After splitting
1182 // we need to handle two types.
1183 while (true) {
1184 LegalizeKind LK = getTypeConversion(C, MTy);
1185
1186 if (LK.first == TypeLegal)
1187 return std::make_pair(Cost, MTy.getSimpleVT());
1188
1189 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1190 Cost *= 2;
1191
1192 // Keep legalizing the type.
1193 MTy = LK.second;
1194 }
1195 }
1196
1197 //===----------------------------------------------------------------------===//
11011198 // Optimization Methods
11021199 //===----------------------------------------------------------------------===//
11031200
66 //
77 //===----------------------------------------------------------------------===//
88
9 #define DEBUG_TYPE "tti"
910 #include "llvm/TargetTransformInfo.h"
1011 #include "llvm/Support/ErrorHandling.h"
1112
1617 char TargetTransformInfo::ID = 0;
1718
1819 TargetTransformInfo::~TargetTransformInfo() {
20 }
21
22 void TargetTransformInfo::pushTTIStack(Pass *P) {
23 TopTTI = this;
24 PrevTTI = &P->getAnalysis();
25
26 // Walk up the chain and update the top TTI pointer.
27 for (TargetTransformInfo *PTTI = PrevTTI; PTTI; PTTI = PTTI->PrevTTI)
28 PTTI->TopTTI = this;
29 }
30
31 void TargetTransformInfo::popTTIStack() {
32 TopTTI = 0;
33
34 // Walk up the chain and update the top TTI pointer.
35 for (TargetTransformInfo *PTTI = PrevTTI; PTTI; PTTI = PTTI->PrevTTI)
36 PTTI->TopTTI = PrevTTI;
37
38 PrevTTI = 0;
1939 }
2040
2141 void TargetTransformInfo::getAnalysisUsage(AnalysisUsage &AU) const {
121141
122142 namespace {
123143
124 class NoTTI : public ImmutablePass, public TargetTransformInfo {
125 const ScalarTargetTransformInfo *STTI;
126 const VectorTargetTransformInfo *VTTI;
127
128 public:
129 // FIXME: This constructor doesn't work which breaks the use of NoTTI on the
130 // commandline. This has to be fixed for NoTTI to be fully usable as an
131 // analysis pass.
132 NoTTI() : ImmutablePass(ID), TargetTransformInfo(0) {
133 llvm_unreachable("Unsupported code path!");
134 }
135
136 NoTTI(const ScalarTargetTransformInfo *S, const VectorTargetTransformInfo *V)
137 : ImmutablePass(ID),
138 TargetTransformInfo(0), // NoTTI is special and doesn't delegate here.
139 STTI(S), VTTI(V) {
144 struct NoTTI : ImmutablePass, TargetTransformInfo {
145 NoTTI() : ImmutablePass(ID) {
140146 initializeNoTTIPass(*PassRegistry::getPassRegistry());
141147 }
142148
143 void getAnalysisUsage(AnalysisUsage &AU) const {
149 virtual void initializePass() {
150 // Note that this subclass is special, and must *not* call initializeTTI as
151 // it does not chain.
152 PrevTTI = 0;
153 }
154
155 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
144156 // Note that this subclass is special, and must *not* call
145157 // TTI::getAnalysisUsage as it breaks the recursion.
146158 }
156168 }
157169
158170
159 // Delegate all predicates through the STTI or VTTI interface.
160
161171 bool isLegalAddImmediate(int64_t Imm) const {
162 return STTI->isLegalAddImmediate(Imm);
172 return false;
163173 }
164174
165175 bool isLegalICmpImmediate(int64_t Imm) const {
166 return STTI->isLegalICmpImmediate(Imm);
176 return false;
167177 }
168178
169179 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
170180 bool HasBaseReg, int64_t Scale) const {
171 return STTI->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
172 Scale);
181 return false;
173182 }
174183
175184 bool isTruncateFree(Type *Ty1, Type *Ty2) const {
176 return STTI->isTruncateFree(Ty1, Ty2);
185 return false;
177186 }
178187
179188 bool isTypeLegal(Type *Ty) const {
180 return STTI->isTypeLegal(Ty);
189 return false;
181190 }
182191
183192 unsigned getJumpBufAlignment() const {
184 return STTI->getJumpBufAlignment();
193 return 0;
185194 }
186195
187196 unsigned getJumpBufSize() const {
188 return STTI->getJumpBufSize();
197 return 0;
189198 }
190199
191200 bool shouldBuildLookupTables() const {
192 return STTI->shouldBuildLookupTables();
201 return true;
193202 }
194203
195204 PopcntHwSupport getPopcntHwSupport(unsigned IntTyWidthInBit) const {
196 return (PopcntHwSupport)STTI->getPopcntHwSupport(IntTyWidthInBit);
205 return None;
197206 }
198207
199208 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const {
200 return STTI->getIntImmCost(Imm, Ty);
209 return 1;
201210 }
202211
203212 unsigned getNumberOfRegisters(bool Vector) const {
204 return VTTI->getNumberOfRegisters(Vector);
213 return 8;
205214 }
206215
207216 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const {
208 return VTTI->getArithmeticInstrCost(Opcode, Ty);
217 return 1;
209218 }
210219
211220 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
212221 int Index = 0, Type *SubTp = 0) const {
213 return VTTI->getShuffleCost((VectorTargetTransformInfo::ShuffleKind)Kind,
214 Tp, Index, SubTp);
222 return 1;
215223 }
216224
217225 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
218226 Type *Src) const {
219 return VTTI->getCastInstrCost(Opcode, Dst, Src);
227 return 1;
220228 }
221229
222230 unsigned getCFInstrCost(unsigned Opcode) const {
223 return VTTI->getCFInstrCost(Opcode);
231 return 1;
224232 }
225233
226234 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
227235 Type *CondTy = 0) const {
228 return VTTI->getCmpSelInstrCost(Opcode, ValTy, CondTy);
236 return 1;
229237 }
230238
231239 unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
232240 unsigned Index = -1) const {
233 return VTTI->getVectorInstrCost(Opcode, Val, Index);
241 return 1;
234242 }
235243
236244 unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
237245 unsigned Alignment,
238246 unsigned AddressSpace) const {
239 return VTTI->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
247 return 1;
240248 }
241249
242250 unsigned getIntrinsicInstrCost(Intrinsic::ID ID,
243251 Type *RetTy,
244252 ArrayRef Tys) const {
245 return VTTI->getIntrinsicInstrCost(ID, RetTy, Tys);
253 return 1;
246254 }
247255
248256 unsigned getNumberOfParts(Type *Tp) const {
249 return VTTI->getNumberOfParts(Tp);
257 return 0;
250258 }
251259 };
252260
253261 } // end anonymous namespace
254262
255 INITIALIZE_AG_PASS(NoTTI, TargetTransformInfo, "no-tti",
263 INITIALIZE_AG_PASS(NoTTI, TargetTransformInfo, "notti",
256264 "No target information", true, true, true)
257265 char NoTTI::ID = 0;
258266
259 ImmutablePass *llvm::createNoTTIPass(const ScalarTargetTransformInfo *S,
260 const VectorTargetTransformInfo *V) {
261 return new NoTTI(S, V);
262 }
267 ImmutablePass *llvm::createNoTargetTransformInfoPass() {
268 return new NoTTI();
269 }
4343 FunctionPass *createThumb2ITBlockPass();
4444 FunctionPass *createThumb2SizeReductionPass();
4545
46 /// \brief Creates an X86-specific Target Transformation Info pass.
47 ImmutablePass *createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM);
48
4649 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
4750 ARMAsmPrinter &AP);
4851
1034310343 return false;
1034410344 }
1034510345
10346 unsigned
10347 ARMScalarTargetTransformImpl::getIntImmCost(const APInt &Imm, Type *Ty) const {
10348 assert(Ty->isIntegerTy());
10349
10350 unsigned Bits = Ty->getPrimitiveSizeInBits();
10351 if (Bits == 0 || Bits > 32)
10352 return 4;
10353
10354 int32_t SImmVal = Imm.getSExtValue();
10355 uint32_t ZImmVal = Imm.getZExtValue();
10356 if (!Subtarget->isThumb()) {
10357 if ((SImmVal >= 0 && SImmVal < 65536) ||
10358 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
10359 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
10360 return 1;
10361 return Subtarget->hasV6T2Ops() ? 2 : 3;
10362 } else if (Subtarget->isThumb2()) {
10363 if ((SImmVal >= 0 && SImmVal < 65536) ||
10364 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
10365 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
10366 return 1;
10367 return Subtarget->hasV6T2Ops() ? 2 : 3;
10368 } else /*Thumb1*/ {
10369 if (SImmVal >= 0 && SImmVal < 256)
10370 return 1;
10371 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
10372 return 2;
10373 // Load from constantpool.
10374 return 3;
10375 }
10376 return 2;
10377 }
2121 #include "llvm/CodeGen/SelectionDAG.h"
2222 #include "llvm/Target/TargetLowering.h"
2323 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Target/TargetTransformImpl.h"
2524 #include
2625
2726 namespace llvm {
573572 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
574573 const TargetLibraryInfo *libInfo);
575574 }
576
577 class ARMScalarTargetTransformImpl : public ScalarTargetTransformImpl {
578 const ARMSubtarget *Subtarget;
579 public:
580 explicit ARMScalarTargetTransformImpl(const TargetLowering *TL) :
581 ScalarTargetTransformImpl(TL),
582 Subtarget(&TL->getTargetMachine().getSubtarget()) {};
583
584 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
585 };
586575 }
587576
588577 #endif // ARMISELLOWERING_H
5050 this->Options.FloatABIType = FloatABI::Soft;
5151 }
5252
53 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
54 // Add first the target-independent BasicTTI pass, then our X86 pass. This
55 // allows the X86 pass to delegate to the target independent layer when
56 // appropriate.
57 PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
58 PM.add(createARMTargetTransformInfoPass(this));
59 }
60
61
5362 void ARMTargetMachine::anchor() { }
5463
5564 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
6978 "v128:64:128-v64:64:64-n32-S32")),
7079 TLInfo(*this),
7180 TSInfo(*this),
72 FrameLowering(Subtarget),
73 STTI(&TLInfo), VTTI(&TLInfo) {
81 FrameLowering(Subtarget) {
7482 if (!Subtarget.hasARMOps())
7583 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
7684 "support ARM mode execution!");
102110 TSInfo(*this),
103111 FrameLowering(Subtarget.hasThumb2()
104112 ? new ARMFrameLowering(Subtarget)
105 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)),
106 STTI(&TLInfo), VTTI(&TLInfo) {
113 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
107114 }
108115
109116 namespace {
2626 #include "llvm/IR/DataLayout.h"
2727 #include "llvm/MC/MCStreamer.h"
2828 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetTransformImpl.h"
3029
3130 namespace llvm {
3231
5049 return &InstrItins;
5150 }
5251
52 /// \brief Register X86 analysis passes with a pass manager.
53 virtual void addAnalysisPasses(PassManagerBase &PM);
54
5355 // Pass Pipeline Configuration
5456 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
5557
6567 ARMTargetLowering TLInfo;
6668 ARMSelectionDAGInfo TSInfo;
6769 ARMFrameLowering FrameLowering;
68 ARMScalarTargetTransformImpl STTI;
69 VectorTargetTransformImpl VTTI;
7070 public:
7171 ARMTargetMachine(const Target &T, StringRef TT,
7272 StringRef CPU, StringRef FS,
8888 virtual const ARMFrameLowering *getFrameLowering() const {
8989 return &FrameLowering;
9090 }
91 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
92 return &STTI;
93 }
94 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
95 return &VTTI;
96 }
9791 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
9892 virtual const DataLayout *getDataLayout() const { return &DL; }
9993 };
111105 ARMSelectionDAGInfo TSInfo;
112106 // Either Thumb1FrameLowering or ARMFrameLowering.
113107 OwningPtr FrameLowering;
114 ARMScalarTargetTransformImpl STTI;
115 VectorTargetTransformImpl VTTI;
116108 public:
117109 ThumbTargetMachine(const Target &T, StringRef TT,
118110 StringRef CPU, StringRef FS,
141133 virtual const ARMFrameLowering *getFrameLowering() const {
142134 return FrameLowering.get();
143135 }
144 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
145 return &STTI;
146 }
147 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
148 return &VTTI;
149 }
150136 virtual const DataLayout *getDataLayout() const { return &DL; }
151137 };
152138
0 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements a TargetTransformInfo analysis pass specific to the
10 /// ARM target machine. It uses the target's detailed information to provide
11 /// more precise answers to certain TTI queries, while letting the target
12 /// independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15
16 #define DEBUG_TYPE "armtti"
17 #include "ARM.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/TargetTransformInfo.h"
22 using namespace llvm;
23
24 // Declare the pass initialization routine locally as target-specific passes
25 // don't havve a target-wide initialization entry point, and so we rely on the
26 // pass constructor initialization.
27 namespace llvm {
28 void initializeARMTTIPass(PassRegistry &);
29 }
30
31 namespace {
32
33 class ARMTTI : public ImmutablePass, public TargetTransformInfo {
34 const ARMBaseTargetMachine *TM;
35 const ARMSubtarget *ST;
36
37 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
38 /// are set if the result needs to be inserted and/or extracted from vectors.
39 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
40
41 public:
42 ARMTTI() : ImmutablePass(ID), TM(0), ST(0) {
43 llvm_unreachable("This pass cannot be directly constructed");
44 }
45
46 ARMTTI(const ARMBaseTargetMachine *TM)
47 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()) {
48 initializeARMTTIPass(*PassRegistry::getPassRegistry());
49 }
50
51 virtual void initializePass() {
52 pushTTIStack(this);
53 }
54
55 virtual void finalizePass() {
56 popTTIStack();
57 }
58
59 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
60 TargetTransformInfo::getAnalysisUsage(AU);
61 }
62
63 /// Pass identification.
64 static char ID;
65
66 /// Provide necessary pointer adjustments for the two base classes.
67 virtual void *getAdjustedAnalysisPointer(const void *ID) {
68 if (ID == &TargetTransformInfo::ID)
69 return (TargetTransformInfo*)this;
70 return this;
71 }
72
73 /// \name Scalar TTI Implementations
74 /// @{
75
76 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
77
78 /// @}
79 };
80
81 } // end anonymous namespace
82
83 INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
84 "ARM Target Transform Info", true, true, false)
85 char ARMTTI::ID = 0;
86
87 ImmutablePass *
88 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
89 return new ARMTTI(TM);
90 }
91
92
93 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
94 assert(Ty->isIntegerTy());
95
96 unsigned Bits = Ty->getPrimitiveSizeInBits();
97 if (Bits == 0 || Bits > 32)
98 return 4;
99
100 int32_t SImmVal = Imm.getSExtValue();
101 uint32_t ZImmVal = Imm.getZExtValue();
102 if (!ST->isThumb()) {
103 if ((SImmVal >= 0 && SImmVal < 65536) ||
104 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
105 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
106 return 1;
107 return ST->hasV6T2Ops() ? 2 : 3;
108 } else if (ST->isThumb2()) {
109 if ((SImmVal >= 0 && SImmVal < 65536) ||
110 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
111 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
112 return 1;
113 return ST->hasV6T2Ops() ? 2 : 3;
114 } else /*Thumb1*/ {
115 if (SImmVal >= 0 && SImmVal < 256)
116 return 1;
117 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
118 return 2;
119 // Load from constantpool.
120 return 3;
121 }
122 return 2;
123 }
3636 ARMSubtarget.cpp
3737 ARMTargetMachine.cpp
3838 ARMTargetObjectFile.cpp
39 ARMTargetTransformInfo.cpp
3940 MLxExpansionPass.cpp
4041 Thumb1FrameLowering.cpp
4142 Thumb1InstrInfo.cpp
77 TargetMachine.cpp
88 TargetMachineC.cpp
99 TargetSubtargetInfo.cpp
10 TargetTransformImpl.cpp
1110 )
1211
1312 foreach(t ${LLVM_TARGETS_TO_BUILD})
7373 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
7474 TSInfo(*this),
7575 FrameLowering(Subtarget),
76 InstrItins(&Subtarget.getInstrItineraryData()),
77 STTI(&TLInfo), VTTI(&TLInfo) {
76 InstrItins(&Subtarget.getInstrItineraryData()) {
7877 setMCUseCFI(false);
7978 }
8079
2020 #include "HexagonSubtarget.h"
2121 #include "llvm/IR/DataLayout.h"
2222 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetTransformImpl.h"
2423
2524 namespace llvm {
2625
3433 HexagonSelectionDAGInfo TSInfo;
3534 HexagonFrameLowering FrameLowering;
3635 const InstrItineraryData* InstrItins;
37 ScalarTargetTransformImpl STTI;
38 VectorTargetTransformImpl VTTI;
3936
4037 public:
4138 HexagonTargetMachine(const Target &T, StringRef TT,StringRef CPU,
7067 return &TSInfo;
7168 }
7269
73 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
74 return &STTI;
75 }
76
77 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
78 return &VTTI;
79 }
80
8170 virtual const DataLayout *getDataLayout() const { return &DL; }
8271 static unsigned getModuleMatchQuality(const Module &M);
8372
4141 InstrInfo(*this),
4242 FrameLowering(Subtarget),
4343 TLInfo(*this), TSInfo(*this),
44 InstrItins(Subtarget.getInstrItineraryData()),
45 STTI(&TLInfo), VTTI(&TLInfo) {
44 InstrItins(Subtarget.getInstrItineraryData()) {
4645 }
4746
4847 namespace {
2323 #include "llvm/MC/MCStreamer.h"
2424 #include "llvm/Target/TargetFrameLowering.h"
2525 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetTransformImpl.h"
2726
2827 namespace llvm {
2928 class formatted_raw_ostream;
3736 MBlazeSelectionDAGInfo TSInfo;
3837 MBlazeIntrinsicInfo IntrinsicInfo;
3938 InstrItineraryData InstrItins;
40 ScalarTargetTransformImpl STTI;
41 VectorTargetTransformImpl VTTI;
4239
4340 public:
4441 MBlazeTargetMachine(const Target &T, StringRef TT,
7471 const TargetIntrinsicInfo *getIntrinsicInfo() const
7572 { return &IntrinsicInfo; }
7673
77 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const
78 { return &STTI; }
79 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const
80 { return &VTTI; }
81
8274 // Pass Pipeline Configuration
8375 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
8476 };
3535 // FIXME: Check DataLayout string.
3636 DL("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),
3737 InstrInfo(*this), TLInfo(*this), TSInfo(*this),
38 FrameLowering(Subtarget), STTI(&TLInfo), VTTI(&TLInfo) { }
38 FrameLowering(Subtarget) { }
3939
4040 namespace {
4141 /// MSP430 Code Generator Pass Configuration Options.
2323 #include "llvm/IR/DataLayout.h"
2424 #include "llvm/Target/TargetFrameLowering.h"
2525 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetTransformImpl.h"
2726
2827 namespace llvm {
2928
3635 MSP430TargetLowering TLInfo;
3736 MSP430SelectionDAGInfo TSInfo;
3837 MSP430FrameLowering FrameLowering;
39 ScalarTargetTransformImpl STTI;
40 VectorTargetTransformImpl VTTI;
4138
4239 public:
4340 MSP430TargetMachine(const Target &T, StringRef TT,
6360 virtual const MSP430SelectionDAGInfo* getSelectionDAGInfo() const {
6461 return &TSInfo;
6562 }
66 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
67 return &STTI;
68 }
69 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
70 return &VTTI;
71 }
7263 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
7364 }; // MSP430TargetMachine.
7465
5353 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64")),
5454 InstrInfo(MipsInstrInfo::create(*this)),
5555 FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
56 TLInfo(*this), TSInfo(*this), JITInfo(),
57 STTI(&TLInfo), VTTI(&TLInfo) {
56 TLInfo(*this), TSInfo(*this), JITInfo() {
5857 }
5958
6059 void MipsebTargetMachine::anchor() { }
2323 #include "llvm/IR/DataLayout.h"
2424 #include "llvm/Target/TargetFrameLowering.h"
2525 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetTransformImpl.h"
2726
2827 namespace llvm {
2928 class formatted_raw_ostream;
3736 MipsTargetLowering TLInfo;
3837 MipsSelectionDAGInfo TSInfo;
3938 MipsJITInfo JITInfo;
40 ScalarTargetTransformImpl STTI;
41 VectorTargetTransformImpl VTTI;
4239
4340 public:
4441 MipsTargetMachine(const Target &T, StringRef TT,
7269 return &TSInfo;
7370 }
7471
75 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
76 return &STTI;
77 }
78 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
79 return &VTTI;
80 }
81
8272 // Pass Pipeline Configuration
8373 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
8474 virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
7070 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
7171 Subtarget(TT, CPU, FS, is64bit),
7272 DL(Subtarget.getDataLayout()),
73 InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering(*this,is64bit),
74 STTI(&TLInfo), VTTI(&TLInfo)
73 InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering(*this,is64bit)
7574 /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
7675 }
7776
2424 #include "llvm/Target/TargetFrameLowering.h"
2525 #include "llvm/Target/TargetMachine.h"
2626 #include "llvm/Target/TargetSelectionDAGInfo.h"
27 #include "llvm/Target/TargetTransformImpl.h"
2827
2928 namespace llvm {
3029
4342
4443 // Hold Strings that can be free'd all together with NVPTXTargetMachine
4544 ManagedStringPool ManagedStrPool;
46
47 ScalarTargetTransformImpl STTI;
48 VectorTargetTransformImpl VTTI;
4945
5046 //bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
5147 // bool DisableVerify, MCContext *&OutCtx);
7470
7571 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
7672 return &TSInfo;
77 }
78 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
79 return &STTI;
80 }
81 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
82 return &VTTI;
8373 }
8474
8575 //virtual bool addInstSelector(PassManagerBase &PM,
4242 DL(Subtarget.getDataLayoutString()), InstrInfo(*this),
4343 FrameLowering(Subtarget), JITInfo(*this, is64Bit),
4444 TLInfo(*this), TSInfo(*this),
45 InstrItins(Subtarget.getInstrItineraryData()),
46 STTI(&TLInfo), VTTI(&TLInfo) {
45 InstrItins(Subtarget.getInstrItineraryData()) {
4746
4847 // The binutils for the BG/P are too old for CFI.
4948 if (Subtarget.isBGP())
2121 #include "PPCSubtarget.h"
2222 #include "llvm/IR/DataLayout.h"
2323 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetTransformImpl.h"
2524
2625 namespace llvm {
2726
3635 PPCTargetLowering TLInfo;
3736 PPCSelectionDAGInfo TSInfo;
3837 InstrItineraryData InstrItins;
39 ScalarTargetTransformImpl STTI;
40 VectorTargetTransformImpl VTTI;
4138
4239 public:
4340 PPCTargetMachine(const Target &T, StringRef TT,
6461 virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; }
6562 virtual const InstrItineraryData *getInstrItineraryData() const {
6663 return &InstrItins;
67 }
68 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
69 return &STTI;
70 }
71 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
72 return &VTTI;
7364 }
7465
7566 // Pass Pipeline Configuration
3535 DL(Subtarget.getDataLayout()),
3636 InstrInfo(Subtarget),
3737 TLInfo(*this), TSInfo(*this),
38 FrameLowering(Subtarget), STTI(&TLInfo), VTTI(&TLInfo) {
38 FrameLowering(Subtarget) {
3939 }
4040
4141 namespace {
2121 #include "llvm/IR/DataLayout.h"
2222 #include "llvm/Target/TargetFrameLowering.h"
2323 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetTransformImpl.h"
2524
2625 namespace llvm {
2726
3231 SparcTargetLowering TLInfo;
3332 SparcSelectionDAGInfo TSInfo;
3433 SparcFrameLowering FrameLowering;
35 ScalarTargetTransformImpl STTI;
36 VectorTargetTransformImpl VTTI;
3734 public:
3835 SparcTargetMachine(const Target &T, StringRef TT,
3936 StringRef CPU, StringRef FS, const TargetOptions &Options,
5350 }
5451 virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {
5552 return &TSInfo;
56 }
57 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
58 return &STTI;
59 }
60 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
61 return &VTTI;
6253 }
6354 virtual const DataLayout *getDataLayout() const { return &DL; }
6455
+0
-388
lib/Target/TargetTransformImpl.cpp less more
None // llvm/Target/TargetTransformImpl.cpp - Target Loop Trans Info ---*- C++ -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "llvm/Target/TargetTransformImpl.h"
10 #include "llvm/Target/TargetLowering.h"
11 #include
12
13 using namespace llvm;
14
15 //===----------------------------------------------------------------------===//
16 //
17 // Calls used by scalar transformations.
18 //
19 //===----------------------------------------------------------------------===//
20
21 bool ScalarTargetTransformImpl::isLegalAddImmediate(int64_t imm) const {
22 return TLI->isLegalAddImmediate(imm);
23 }
24
25 bool ScalarTargetTransformImpl::isLegalICmpImmediate(int64_t imm) const {
26 return TLI->isLegalICmpImmediate(imm);
27 }
28
29 bool ScalarTargetTransformImpl::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
30 int64_t BaseOffset, bool HasBaseReg,
31 int64_t Scale) const {
32 AddrMode AM;
33 AM.BaseGV = BaseGV;
34 AM.BaseOffs = BaseOffset;
35 AM.HasBaseReg = HasBaseReg;
36 AM.Scale = Scale;
37 return TLI->isLegalAddressingMode(AM, Ty);
38 }
39
40 bool ScalarTargetTransformImpl::isTruncateFree(Type *Ty1, Type *Ty2) const {
41 return TLI->isTruncateFree(Ty1, Ty2);
42 }
43
44 bool ScalarTargetTransformImpl::isTypeLegal(Type *Ty) const {
45 EVT T = TLI->getValueType(Ty);
46 return TLI->isTypeLegal(T);
47 }
48
49 unsigned ScalarTargetTransformImpl::getJumpBufAlignment() const {
50 return TLI->getJumpBufAlignment();
51 }
52
53 unsigned ScalarTargetTransformImpl::getJumpBufSize() const {
54 return TLI->getJumpBufSize();
55 }
56
57 bool ScalarTargetTransformImpl::shouldBuildLookupTables() const {
58 return TLI->supportJumpTables() &&
59 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
60 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
61 }
62
63 //===----------------------------------------------------------------------===//
64 //
65 // Calls used by the vectorizers.
66 //
67 //===----------------------------------------------------------------------===//
68 int VectorTargetTransformImpl::InstructionOpcodeToISD(unsigned Opcode) const {
69 enum InstructionOpcodes {
70 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
71 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
72 #include "llvm/IR/Instruction.def"
73 };
74 switch (static_cast(Opcode)) {
75 case Ret: return 0;
76 case Br: return 0;
77 case Switch: return 0;
78 case IndirectBr: return 0;
79 case Invoke: return 0;
80 case Resume: return 0;
81 case Unreachable: return 0;
82 case Add: return ISD::ADD;
83 case FAdd: return ISD::FADD;
84 case Sub: return ISD::SUB;
85 case FSub: return ISD::FSUB;
86 case Mul: return ISD::MUL;
87 case FMul: return ISD::FMUL;
88 case UDiv: return ISD::UDIV;
89 case SDiv: return ISD::UDIV;
90 case FDiv: return ISD::FDIV;
91 case URem: return ISD::UREM;
92 case SRem: return ISD::SREM;
93 case FRem: return ISD::FREM;
94 case Shl: return ISD::SHL;
95 case LShr: return ISD::SRL;
96 case AShr: return ISD::SRA;
97 case And: return ISD::AND;
98 case Or: return ISD::OR;
99 case Xor: return ISD::XOR;
100 case Alloca: return 0;
101 case Load: return ISD::LOAD;
102 case Store: return ISD::STORE;
103 case GetElementPtr: return 0;
104 case Fence: return 0;
105 case AtomicCmpXchg: return 0;
106 case AtomicRMW: return 0;
107 case Trunc: return ISD::TRUNCATE;
108 case ZExt: return ISD::ZERO_EXTEND;
109 case SExt: return ISD::SIGN_EXTEND;
110 case FPToUI: return ISD::FP_TO_UINT;
111 case FPToSI: return ISD::FP_TO_SINT;
112 case UIToFP: return ISD::UINT_TO_FP;
113 case SIToFP: return ISD::SINT_TO_FP;
114 case FPTrunc: return ISD::FP_ROUND;
115 case FPExt: return ISD::FP_EXTEND;
116 case PtrToInt: return ISD::BITCAST;
117 case IntToPtr: return ISD::BITCAST;
118 case BitCast: return ISD::BITCAST;
119 case ICmp: return ISD::SETCC;
120 case FCmp: return ISD::SETCC;
121 case PHI: return 0;
122 case Call: return 0;
123 case Select: return ISD::SELECT;
124 case UserOp1: return 0;
125 case UserOp2: return 0;
126 case VAArg: return 0;
127 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
128 case InsertElement: return ISD::INSERT_VECTOR_ELT;
129 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
130 case ExtractValue: return ISD::MERGE_VALUES;
131 case InsertValue: return ISD::MERGE_VALUES;
132 case LandingPad: return 0;
133 }
134
135 llvm_unreachable("Unknown instruction type encountered!");
136 }
137
138 std::pair
139 VectorTargetTransformImpl::getTypeLegalizationCost(Type *Ty) const {
140 LLVMContext &C = Ty->getContext();
141 EVT MTy = TLI->getValueType(Ty);
142
143 unsigned Cost = 1;
144 // We keep legalizing the type until we find a legal kind. We assume that
145 // the only operation that costs anything is the split. After splitting
146 // we need to handle two types.
147 while (true) {
148 TargetLowering::LegalizeKind LK = TLI->getTypeConversion(C, MTy);
149
150 if (LK.first == TargetLowering::TypeLegal)
151 return std::make_pair(Cost, MTy.getSimpleVT());
152
153 if (LK.first == TargetLowering::TypeSplitVector ||
154 LK.first == TargetLowering::TypeExpandInteger)
155 Cost *= 2;
156
157 // Keep legalizing the type.
158 MTy = LK.second;
159 }
160 }
161
162 unsigned
163 VectorTargetTransformImpl::getScalarizationOverhead(Type *Ty,
164 bool Insert,
165 bool Extract) const {
166 assert (Ty->isVectorTy() && "Can only scalarize vectors");
167 unsigned Cost = 0;
168
169 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) {
170 if (Insert)
171 Cost += getVectorInstrCost(Instruction::InsertElement, Ty, i);
172 if (Extract)
173 Cost += getVectorInstrCost(Instruction::ExtractElement, Ty, i);
174 }
175
176 return Cost;
177 }
178
179 unsigned VectorTargetTransformImpl::getNumberOfRegisters(bool Vector) const {
180 return 1;
181 }
182
183 unsigned VectorTargetTransformImpl::getArithmeticInstrCost(unsigned Opcode,
184 Type *Ty) const {
185 // Check if any of the operands are vector operands.
186 int ISD = InstructionOpcodeToISD(Opcode);
187 assert(ISD && "Invalid opcode");
188
189 std::pair LT = getTypeLegalizationCost(Ty);
190
191 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
192 // The operation is legal. Assume it costs 1.
193 // If the type is split to multiple registers, assume that thre is some
194 // overhead to this.
195 // TODO: Once we have extract/insert subvector cost we need to use them.
196 if (LT.first > 1)
197 return LT.first * 2;
198 return LT.first * 1;
199 }
200
201 if (!TLI->isOperationExpand(ISD, LT.second)) {
202 // If the operation is custom lowered then assume
203 // thare the code is twice as expensive.
204 return LT.first * 2;
205 }
206
207 // Else, assume that we need to scalarize this op.
208 if (Ty->isVectorTy()) {
209 unsigned Num = Ty->getVectorNumElements();
210 unsigned Cost = getArithmeticInstrCost(Opcode, Ty->getScalarType());
211 // return the cost of multiple scalar invocation plus the cost of inserting
212 // and extracting the values.
213 return getScalarizationOverhead(Ty, true, true) + Num * Cost;
214 }
215
216 // We don't know anything about this scalar instruction.
217 return 1;
218 }
219
220 unsigned VectorTargetTransformImpl::getShuffleCost(ShuffleKind Kind,
221 Type *Tp, int Index, Type *SubTp) const {
222 return 1;
223 }
224
225 unsigned VectorTargetTransformImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
226 Type *Src) const {
227 int ISD = InstructionOpcodeToISD(Opcode);
228 assert(ISD && "Invalid opcode");
229
230 std::pair SrcLT = getTypeLegalizationCost(Src);
231 std::pair DstLT = getTypeLegalizationCost(Dst);
232
233 // Handle scalar conversions.
234 if (!Src->isVectorTy() && !Dst->isVectorTy()) {
235
236 // Scalar bitcasts are usually free.
237 if (Opcode == Instruction::BitCast)
238 return 0;
239
240 if (Opcode == Instruction::Trunc &&
241 TLI->isTruncateFree(SrcLT.second, DstLT.second))
242 return 0;
243
244 if (Opcode == Instruction::ZExt &&
245 TLI->isZExtFree(SrcLT.second, DstLT.second))
246 return 0;
247
248 // Just check the op cost. If the operation is legal then assume it costs 1.
249 if (!TLI->isOperationExpand(ISD, DstLT.second))
250 return 1;
251
252 // Assume that illegal scalar instruction are expensive.
253 return 4;
254 }
255
256 // Check vector-to-vector casts.
257 if (Dst->isVectorTy() && Src->isVectorTy()) {
258
259 // If the cast is between same-sized registers, then the check is simple.
260 if (SrcLT.first == DstLT.first &&
261 SrcLT.second.getSizeInBits() == DstLT.second.getSizeInBits()) {
262
263 // Bitcast between types that are legalized to the same type are free.
264 if (Opcode == Instruction::BitCast || Opcode == Instruction::Trunc)
265 return 0;
266
267 // Assume that Zext is done using AND.
268 if (Opcode == Instruction::ZExt)
269 return 1;
270
271 // Assume that sext is done using SHL and SRA.
272 if (Opcode == Instruction::SExt)
273 return 2;
274
275 // Just check the op cost. If the operation is legal then assume it costs
276 // 1 and multiply by the type-legalization overhead.
277 if (!TLI->isOperationExpand(ISD, DstLT.second))
278 return SrcLT.first * 1;
279 }
280
281 // If we are converting vectors and the operation is illegal, or
282 // if the vectors are legalized to different types, estimate the
283 // scalarization costs.
284 unsigned Num = Dst->getVectorNumElements();
285 unsigned Cost = getCastInstrCost(Opcode, Dst->getScalarType(),
286 Src->getScalarType());
287
288 // Return the cost of multiple scalar invocation plus the cost of
289 // inserting and extracting the values.
290 return getScalarizationOverhead(Dst, true, true) + Num * Cost;
291 }
292
293 // We already handled vector-to-vector and scalar-to-scalar conversions. This
294 // is where we handle bitcast between vectors and scalars. We need to assume
295 // that the conversion is scalarized in one way or another.
296 if (Opcode == Instruction::BitCast)
297 // Illegal bitcasts are done by storing and loading from a stack slot.
298 return (Src->isVectorTy()? getScalarizationOverhead(Src, false, true):0) +
299 (Dst->isVectorTy()? getScalarizationOverhead(Dst, true, false):0);
300
301 llvm_unreachable("Unhandled cast");
302 }
303
304 unsigned VectorTargetTransformImpl::getCFInstrCost(unsigned Opcode) const {
305 // Branches are assumed to be predicted.
306 return 0;
307 }
308
309 unsigned VectorTargetTransformImpl::getCmpSelInstrCost(unsigned Opcode,
310 Type *ValTy,
311 Type *CondTy) const {
312 int ISD = InstructionOpcodeToISD(Opcode);
313 assert(ISD && "Invalid opcode");
314
315 // Selects on vectors are actually vector selects.
316 if (ISD == ISD::SELECT) {
317 assert(CondTy && "CondTy must exist");
318 if (CondTy->isVectorTy())
319 ISD = ISD::VSELECT;
320 }
321
322 std::pair LT = getTypeLegalizationCost(ValTy);
323
324 if (!TLI->isOperationExpand(ISD, LT.second)) {
325 // The operation is legal. Assume it costs 1. Multiply
326 // by the type-legalization overhead.
327 return LT.first * 1;
328 }
329
330 // Otherwise, assume that the cast is scalarized.
331 if (ValTy->isVectorTy()) {
332 unsigned Num = ValTy->getVectorNumElements();
333 if (CondTy)
334 CondTy = CondTy->getScalarType();
335 unsigned Cost = getCmpSelInstrCost(Opcode, ValTy->getScalarType(),
336 CondTy);
337
338 // Return the cost of multiple scalar invocation plus the cost of inserting
339 // and extracting the values.
340 return getScalarizationOverhead(ValTy, true, false) + Num * Cost;
341 }
342
343 // Unknown scalar opcode.
344 return 1;
345 }
346
347 unsigned VectorTargetTransformImpl::getVectorInstrCost(unsigned Opcode,
348 Type *Val,
349 unsigned Index) const {
350 return 1;
351 }
352
353 unsigned
354 VectorTargetTransformImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
355 unsigned Alignment,
356 unsigned AddressSpace) const {
357 assert(!Src->isVoidTy() && "Invalid type");
358 std::pair LT = getTypeLegalizationCost(Src);
359
360 // Assume that all loads of legal types cost 1.
361 return LT.first;
362 }
363
364 unsigned
365 VectorTargetTransformImpl::getIntrinsicInstrCost(Intrinsic::ID, Type *RetTy,
366 ArrayRef Tys) const {
367 // assume that we need to scalarize this intrinsic.
368 unsigned ScalarizationCost = 0;
369 unsigned ScalarCalls = 1;
370 if (RetTy->isVectorTy()) {
371 ScalarizationCost = getScalarizationOverhead(RetTy, true, false);
372 ScalarCalls = std::max(ScalarCalls, RetTy->getVectorNumElements());
373 }
374 for (unsigned i = 0, ie = Tys.size(); i != ie; ++i) {
375 if (Tys[i]->isVectorTy()) {
376 ScalarizationCost += getScalarizationOverhead(Tys[i], false, true);
377 ScalarCalls = std::max(ScalarCalls, RetTy->getVectorNumElements());
378 }
379 }
380 return ScalarCalls + ScalarizationCost;
381 }
382
383 unsigned
384 VectorTargetTransformImpl::getNumberOfParts(Type *Tp) const {
385 std::pair LT = getTypeLegalizationCost(Tp);
386 return LT.first;
387 }
2929 X86Subtarget.cpp
3030 X86TargetMachine.cpp
3131 X86TargetObjectFile.cpp
32 X86TargetTransformInfo.cpp
3233 X86VZeroUpper.cpp
3334 )
3435
6262 ///
6363 FunctionPass *createEmitX86CodeToMemory();
6464
65 /// \brief Creates an X86-specific Target Transformation Info pass.
66 ImmutablePass *createX86TargetTransformInfoPass(const X86TargetMachine *TM);
67
6568 } // End llvm namespace
6669
6770 #endif
1806218062
1806318063 return Res;
1806418064 }
18065
18066 //===----------------------------------------------------------------------===//
18067 //
18068 // X86 cost model.
18069 //
18070 //===----------------------------------------------------------------------===//
18071
18072 struct X86CostTblEntry {
18073 int ISD;
18074 MVT Type;
18075 unsigned Cost;
18076 };
18077
18078 static int
18079 FindInTable(const X86CostTblEntry *Tbl, unsigned len, int ISD, MVT Ty) {
18080 for (unsigned int i = 0; i < len; ++i)
18081 if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)
18082 return i;
18083
18084 // Could not find an entry.
18085 return -1;
18086 }
18087
18088 struct X86TypeConversionCostTblEntry {
18089 int ISD;
18090 MVT Dst;
18091 MVT Src;
18092 unsigned Cost;
18093 };
18094
18095 static int
18096 FindInConvertTable(const X86TypeConversionCostTblEntry *Tbl, unsigned len,
18097 int ISD, MVT Dst, MVT Src) {
18098 for (unsigned int i = 0; i < len; ++i)
18099 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
18100 return i;
18101
18102 // Could not find an entry.
18103 return -1;
18104 }
18105
18106 ScalarTargetTransformInfo::PopcntHwSupport
18107 X86ScalarTargetTransformImpl::getPopcntHwSupport(unsigned TyWidth) const {
18108 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
18109 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget();
18110
18111 // TODO: Currently the __builtin_popcount() implementation using SSE3
18112 // instructions is inefficient. Once the problem is fixed, we should
18113 // call ST.hasSSE3() instead of ST.hasSSE4().
18114 return ST.hasSSE41() ? Fast : None;
18115 }
18116
18117 unsigned X86VectorTargetTransformInfo::getNumberOfRegisters(bool Vector) const {
18118 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget();
18119 if (ST.is64Bit())
18120 return 16;
18121 return 8;
18122 }
18123
18124 unsigned
18125 X86VectorTargetTransformInfo::getArithmeticInstrCost(unsigned Opcode,
18126 Type *Ty) const {
18127 // Legalize the type.
18128 std::pair LT = getTypeLegalizationCost(Ty);
18129
18130 int ISD = InstructionOpcodeToISD(Opcode);
18131 assert(ISD && "Invalid opcode");
18132
18133 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget();
18134
18135 static const X86CostTblEntry AVX1CostTable[] = {
18136 // We don't have to scalarize unsupported ops. We can issue two half-sized
18137 // operations and we only need to extract the upper YMM half.
18138 // Two ops + 1 extract + 1 insert = 4.
18139 { ISD::MUL, MVT::v8i32, 4 },
18140 { ISD::SUB, MVT::v8i32, 4 },
18141 { ISD::ADD, MVT::v8i32, 4 },
18142 { ISD::MUL, MVT::v4i64, 4 },
18143 { ISD::SUB, MVT::v4i64, 4 },
18144 { ISD::ADD, MVT::v4i64, 4 },
18145 };
18146
18147 // Look for AVX1 lowering tricks.
18148 if (ST.hasAVX()) {
18149 int Idx = FindInTable(AVX1CostTable, array_lengthof(AVX1CostTable), ISD,
18150 LT.second);
18151 if (Idx != -1)
18152 return LT.first * AVX1CostTable[Idx].Cost;
18153 }
18154 // Fallback to the default implementation.
18155 return VectorTargetTransformImpl::getArithmeticInstrCost(Opcode, Ty);
18156 }
18157
18158 unsigned
18159 X86VectorTargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
18160 unsigned Alignment,
18161 unsigned AddressSpace) const {
18162 // Legalize the type.
18163 std::pair LT = getTypeLegalizationCost(Src);
18164 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
18165 "Invalid Opcode");
18166
18167 const X86Subtarget &ST =
18168 TLI->getTargetMachine().getSubtarget();
18169
18170 // Each load/store unit costs 1.
18171 unsigned Cost = LT.first * 1;
18172
18173 // On Sandybridge 256bit load/stores are double pumped
18174 // (but not on Haswell).
18175 if (LT.second.getSizeInBits() > 128 && !ST.hasAVX2())
18176 Cost*=2;
18177
18178 return Cost;
18179 }
18180
18181 unsigned
18182 X86VectorTargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
18183 unsigned Index) const {
18184 assert(Val->isVectorTy() && "This must be a vector type");
18185
18186 if (Index != -1U) {
18187 // Legalize the type.
18188 std::pair LT = getTypeLegalizationCost(Val);
18189
18190 // This type is legalized to a scalar type.
18191 if (!LT.second.isVector())
18192 return 0;
18193
18194 // The type may be split. Normalize the index to the new type.
18195 unsigned Width = LT.second.getVectorNumElements();
18196 Index = Index % Width;
18197
18198 // Floating point scalars are already located in index #0.
18199 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
18200 return 0;
18201 }
18202
18203 return VectorTargetTransformImpl::getVectorInstrCost(Opcode, Val, Index);
18204 }
18205
18206 unsigned X86VectorTargetTransformInfo::getCmpSelInstrCost(unsigned Opcode,
18207 Type *ValTy,
18208 Type *CondTy) const {
18209 // Legalize the type.
18210 std::pair LT = getTypeLegalizationCost(ValTy);
18211
18212 MVT MTy = LT.second;
18213
18214 int ISD = InstructionOpcodeToISD(Opcode);
18215 assert(ISD && "Invalid opcode");
18216
18217 const X86Subtarget &ST =
18218 TLI->getTargetMachine().getSubtarget();
18219
18220 static const X86CostTblEntry SSE42CostTbl[] = {
18221 { ISD::SETCC, MVT::v2f64, 1 },
18222 { ISD::SETCC, MVT::v4f32, 1 },
18223 { ISD::SETCC, MVT::v2i64, 1 },
18224 { ISD::SETCC, MVT::v4i32, 1 },
18225 { ISD::SETCC, MVT::v8i16, 1 },
18226 { ISD::SETCC, MVT::v16i8, 1 },
18227 };
18228
18229 static const X86CostTblEntry AVX1CostTbl[] = {
18230 { ISD::SETCC, MVT::v4f64, 1 },
18231 { ISD::SETCC, MVT::v8f32, 1 },
18232 // AVX1 does not support 8-wide integer compare.
18233 { ISD::SETCC, MVT::v4i64, 4 },
18234 { ISD::SETCC, MVT::v8i32, 4 },
18235 { ISD::SETCC, MVT::v16i16, 4 },
18236 { ISD::SETCC, MVT::v32i8, 4 },
18237 };
18238
18239 static const X86CostTblEntry AVX2CostTbl[] = {
18240 { ISD::SETCC, MVT::v4i64, 1 },
18241 { ISD::SETCC, MVT::v8i32, 1 },
18242 { ISD::SETCC, MVT::v16i16, 1 },
18243 { ISD::SETCC, MVT::v32i8, 1 },
18244 };
18245
18246 if (ST.hasAVX2()) {
18247 int Idx = FindInTable(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
18248 if (Idx != -1)
18249 return LT.first * AVX2CostTbl[Idx].Cost;
18250 }
18251
18252 if (ST.hasAVX()) {
18253 int Idx = FindInTable(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
18254 if (Idx != -1)
18255 return LT.first * AVX1CostTbl[Idx].Cost;
18256 }
18257
18258 if (ST.hasSSE42()) {
18259 int Idx = FindInTable(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
18260 if (Idx != -1)
18261 return LT.first * SSE42CostTbl[Idx].Cost;
18262 }
18263
18264 return VectorTargetTransformImpl::getCmpSelInstrCost(Opcode, ValTy, CondTy);
18265 }
18266
18267 unsigned X86VectorTargetTransformInfo::getCastInstrCost(unsigned Opcode,
18268 Type *Dst,
18269 Type *Src) const {
18270 int ISD = InstructionOpcodeToISD(Opcode);
18271 assert(ISD && "Invalid opcode");
18272
18273 EVT SrcTy = TLI->getValueType(Src);
18274 EVT DstTy = TLI->getValueType(Dst);
18275
18276 if (!SrcTy.isSimple() || !DstTy.isSimple())
18277 return VectorTargetTransformImpl::getCastInstrCost(Opcode, Dst, Src);
18278
18279 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget();
18280
18281 static const X86TypeConversionCostTblEntry AVXConversionTbl[] = {
18282 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
18283 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
18284 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
18285 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
18286 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
18287 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
18288 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
18289 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
18290 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
18291 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
18292 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
18293 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
18294 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
18295 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
18296 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
18297 };
18298
18299 if (ST.hasAVX()) {
18300 int Idx = FindInConvertTable(AVXConversionTbl,
18301 array_lengthof(AVXConversionTbl),
18302 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
18303 if (Idx != -1)
18304 return AVXConversionTbl[Idx].Cost;
18305 }
18306
18307 return VectorTargetTransformImpl::getCastInstrCost(Opcode, Dst, Src);
18308 }
18309
18310
18311 unsigned X86VectorTargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Tp,
18312 int Index,
18313 Type *SubTp) const {
18314 // We only estimate the cost of reverse shuffles.
18315 if (Kind != Reverse)
18316 return VectorTargetTransformImpl::getShuffleCost(Kind, Tp, Index, SubTp);
18317
18318 std::pair LT = getTypeLegalizationCost(Tp);
18319 unsigned Cost = 1;
18320 if (LT.second.getSizeInBits() > 128)
18321 Cost = 3; // Extract + insert + copy.
18322
18323 // Multiple by the number of parts.
18324 return Cost * LT.first;
18325 }
18326
2222 #include "llvm/CodeGen/SelectionDAG.h"
2323 #include "llvm/Target/TargetLowering.h"
2424 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetTransformImpl.h"
2625
2726 namespace llvm {
2827 namespace X86ISD {
944943 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
945944 const TargetLibraryInfo *libInfo);
946945 }
947
948 class X86ScalarTargetTransformImpl : public ScalarTargetTransformImpl {
949 public:
950 explicit X86ScalarTargetTransformImpl(const TargetLowering *TL) :
951 ScalarTargetTransformImpl(TL) {};
952
953 virtual PopcntHwSupport getPopcntHwSupport(unsigned TyWidth) const;
954 };
955
956 class X86VectorTargetTransformInfo : public VectorTargetTransformImpl {
957 public:
958 explicit X86VectorTargetTransformInfo(const TargetLowering *TL) :
959 VectorTargetTransformImpl(TL) {}
960
961 virtual unsigned getNumberOfRegisters(bool Vector) const;
962
963 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
964
965 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
966 unsigned Alignment,
967 unsigned AddressSpace) const;
968
969 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
970 unsigned Index) const;
971
972 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
973 Type *CondTy) const;
974
975 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
976 Type *Src) const;
977
978 unsigned getShuffleCost(ShuffleKind Kind,
979 Type *Tp, int Index, Type *SubTp) const;
980 };
981946 }
982947
983948 #endif // X86ISELLOWERING_H
4747 InstrInfo(*this),
4848 TLInfo(*this),
4949 TSInfo(*this),
50 JITInfo(*this),
51 STTI(&TLInfo), VTTI(&TLInfo) {
50 JITInfo(*this) {
5251 }
5352
5453 void X86_64TargetMachine::anchor() { }
6463 InstrInfo(*this),
6564 TLInfo(*this),
6665 TSInfo(*this),
67 JITInfo(*this),
68 STTI(&TLInfo), VTTI(&TLInfo){
66 JITInfo(*this) {
6967 }
7068
7169 /// X86TargetMachine ctor - Create an X86 target.
120118 cl::desc("Enable early if-conversion on X86"));
121119
122120 //===----------------------------------------------------------------------===//
121 // X86 Analysis Pass Setup
122 //===----------------------------------------------------------------------===//
123
124 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
125 // Add first the target-independent BasicTTI pass, then our X86 pass. This
126 // allows the X86 pass to delegate to the target independent layer when
127 // appropriate.
128 PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
129 PM.add(createX86TargetTransformInfoPass(this));
130 }
131
132
133 //===----------------------------------------------------------------------===//
123134 // Pass Pipeline Configuration
124135 //===----------------------------------------------------------------------===//
125136
2323 #include "llvm/IR/DataLayout.h"
2424 #include "llvm/Target/TargetFrameLowering.h"
2525 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetTransformImpl.h"
2726
2827 namespace llvm {
2928
6463 return &InstrItins;
6564 }
6665
66 /// \brief Register X86 analysis passes with a pass manager.
67 virtual void addAnalysisPasses(PassManagerBase &PM);
68
6769 // Set up the pass pipeline.
6870 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
6971
8082 X86TargetLowering TLInfo;
8183 X86SelectionDAGInfo TSInfo;
8284 X86JITInfo JITInfo;
83 ScalarTargetTransformImpl STTI;
84 X86VectorTargetTransformInfo VTTI;
8585 public:
8686 X86_32TargetMachine(const Target &T, StringRef TT,
8787 StringRef CPU, StringRef FS, const TargetOptions &Options,
100100 virtual X86JITInfo *getJITInfo() {
101101 return &JITInfo;
102102 }
103 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
104 return &STTI;
105 }
106 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
107 return &VTTI;
108 }
109103 };
110104
111105 /// X86_64TargetMachine - X86 64-bit target machine.
117111 X86TargetLowering TLInfo;
118112 X86SelectionDAGInfo TSInfo;
119113 X86JITInfo JITInfo;
120 X86ScalarTargetTransformImpl STTI;
121 X86VectorTargetTransformInfo VTTI;
122114 public:
123115 X86_64TargetMachine(const Target &T, StringRef TT,
124116 StringRef CPU, StringRef FS, const TargetOptions &Options,
137129 virtual X86JITInfo *getJITInfo() {
138130 return &JITInfo;
139131 }
140 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
141 return &STTI;
142 }
143 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
144 return &VTTI;
145 }
146132 };
147133
148134 } // End llvm namespace
0 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements a TargetTransformInfo analysis pass specific to the
10 /// X86 target machine. It uses the target's detailed information to provide
11 /// more precise answers to certain TTI queries, while letting the target
12 /// independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15
16 #define DEBUG_TYPE "x86tti"
17 #include "X86.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/TargetTransformInfo.h"
22 using namespace llvm;
23
24 // Declare the pass initialization routine locally as target-specific passes
25 // don't havve a target-wide initialization entry point, and so we rely on the
26 // pass constructor initialization.
27 namespace llvm {
28 void initializeX86TTIPass(PassRegistry &);
29 }
30
31 namespace {
32
33 class X86TTI : public ImmutablePass, public TargetTransformInfo {
34 const X86TargetMachine *TM;
35 const X86Subtarget *ST;
36 const X86TargetLowering *TLI;
37
38 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
39 /// are set if the result needs to be inserted and/or extracted from vectors.
40 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
41
42 public:
43 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
44 llvm_unreachable("This pass cannot be directly constructed");
45 }
46
47 X86TTI(const X86TargetMachine *TM)
48 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
49 TLI(TM->getTargetLowering()) {
50 initializeX86TTIPass(*PassRegistry::getPassRegistry());
51 }
52
53 virtual void initializePass() {
54 pushTTIStack(this);
55 }
56
57 virtual void finalizePass() {
58 popTTIStack();
59 }
60
61 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
62 TargetTransformInfo::getAnalysisUsage(AU);
63 }
64
65 /// Pass identification.
66 static char ID;
67
68 /// Provide necessary pointer adjustments for the two base classes.
69 virtual void *getAdjustedAnalysisPointer(const void *ID) {
70 if (ID == &TargetTransformInfo::ID)
71 return (TargetTransformInfo*)this;
72 return this;
73 }
74
75 /// \name Scalar TTI Implementations
76 /// @{
77
78 virtual PopcntHwSupport getPopcntHwSupport(unsigned TyWidth) const;
79
80 /// @}
81
82 /// \name Vector TTI Implementations
83 /// @{
84
85 virtual unsigned getNumberOfRegisters(bool Vector) const;
86 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
87 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
88 int Index, Type *SubTp) const;
89 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
90 Type *Src) const;
91 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
92 Type *CondTy) const;
93 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
94 unsigned Index) const;
95 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
96 unsigned Alignment,
97 unsigned AddressSpace) const;
98
99 /// @}
100 };
101
102 } // end anonymous namespace
103
104 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
105 "X86 Target Transform Info", true, true, false)
106 char X86TTI::ID = 0;
107
108 ImmutablePass *
109 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
110 return new X86TTI(TM);
111 }
112
113
114 //===----------------------------------------------------------------------===//
115 //
116 // X86 cost model.
117 //
118 //===----------------------------------------------------------------------===//
119
120 namespace {
121 struct X86CostTblEntry {
122 int ISD;
123 MVT Type;
124 unsigned Cost;
125 };
126 }
127
128 static int
129 FindInTable(const X86CostTblEntry *Tbl, unsigned len, int ISD, MVT Ty) {
130 for (unsigned int i = 0; i < len; ++i)
131 if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)
132 return i;
133
134 // Could not find an entry.
135 return -1;
136 }
137
138 namespace {
139 struct X86TypeConversionCostTblEntry {
140 int ISD;
141 MVT Dst;
142 MVT Src;
143 unsigned Cost;
144 };
145 }
146
147 static int
148 FindInConvertTable(const X86TypeConversionCostTblEntry *Tbl, unsigned len,
149 int ISD, MVT Dst, MVT Src) {
150 for (unsigned int i = 0; i < len; ++i)
151 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
152 return i;
153
154 // Could not find an entry.
155 return -1;
156 }
157
158
159 X86TTI::PopcntHwSupport X86TTI::getPopcntHwSupport(unsigned TyWidth) const {
160 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
161 // TODO: Currently the __builtin_popcount() implementation using SSE3
162 // instructions is inefficient. Once the problem is fixed, we should
163 // call ST->hasSSE3() instead of ST->hasSSE4().
164 return ST->hasSSE41() ? Fast : None;
165 }
166
167 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
168 if (ST->is64Bit())
169 return 16;
170 return 8;
171 }
172
173 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty) const {
174 // Legalize the type.
175 std::pair LT = TLI->getTypeLegalizationCost(Ty);
176
177 int ISD = TLI->InstructionOpcodeToISD(Opcode);
178 assert(ISD && "Invalid opcode");
179
180 static const X86CostTblEntry AVX1CostTable[] = {
181 // We don't have to scalarize unsupported ops. We can issue two half-sized
182 // operations and we only need to extract the upper YMM half.
183 // Two ops + 1 extract + 1 insert = 4.
184 { ISD::MUL, MVT::v8i32, 4 },
185 { ISD::SUB, MVT::v8i32, 4 },
186 { ISD::ADD, MVT::v8i32, 4 },
187 { ISD::MUL, MVT::v4i64, 4 },
188 { ISD::SUB, MVT::v4i64, 4 },
189 { ISD::ADD, MVT::v4i64, 4 },
190 };
191
192 // Look for AVX1 lowering tricks.
193 if (ST->hasAVX()) {
194 int Idx = FindInTable(AVX1CostTable, array_lengthof(AVX1CostTable), ISD,
195 LT.second);
196 if (Idx != -1)
197 return LT.first * AVX1CostTable[Idx].Cost;
198 }
199 // Fallback to the default implementation.
200 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty);
201 }
202
203 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
204 Type *SubTp) const {
205 // We only estimate the cost of reverse shuffles.
206 if (Kind != Reverse)
207 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
208
209 std::pair LT = TLI->getTypeLegalizationCost(Tp);
210 unsigned Cost = 1;
211 if (LT.second.getSizeInBits() > 128)
212 Cost = 3; // Extract + insert + copy.
213
214 // Multiple by the number of parts.
215 return Cost * LT.first;
216 }
217
218 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
219 int ISD = TLI->InstructionOpcodeToISD(Opcode);
220 assert(ISD && "Invalid opcode");
221
222 EVT SrcTy = TLI->getValueType(Src);
223 EVT DstTy = TLI->getValueType(Dst);
224
225 if (!SrcTy.isSimple() || !DstTy.isSimple())
226 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
227
228 static const X86TypeConversionCostTblEntry AVXConversionTbl[] = {
229 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
230 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
231 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
232 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
233 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
234 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
235 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
236 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
237 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
238 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
239 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
240 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
241 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
242 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
243 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
244 };
245
246 if (ST->hasAVX()) {
247 int Idx = FindInConvertTable(AVXConversionTbl,
248 array_lengthof(AVXConversionTbl),
249 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
250 if (Idx != -1)
251 return AVXConversionTbl[Idx].Cost;
252 }
253
254 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
255 }
256
257 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
258 Type *CondTy) const {
259 // Legalize the type.
260 std::pair LT = TLI->getTypeLegalizationCost(ValTy);
261
262 MVT MTy = LT.second;
263
264 int ISD = TLI->InstructionOpcodeToISD(Opcode);
265 assert(ISD && "Invalid opcode");
266
267 static const X86CostTblEntry SSE42CostTbl[] = {
268 { ISD::SETCC, MVT::v2f64, 1 },
269 { ISD::SETCC, MVT::v4f32, 1 },
270 { ISD::SETCC, MVT::v2i64, 1 },
271 { ISD::SETCC, MVT::v4i32, 1 },
272 { ISD::SETCC, MVT::v8i16, 1 },
273 { ISD::SETCC, MVT::v16i8, 1 },
274 };
275
276 static const X86CostTblEntry AVX1CostTbl[] = {
277 { ISD::SETCC, MVT::v4f64, 1 },
278 { ISD::SETCC, MVT::v8f32, 1 },
279 // AVX1 does not support 8-wide integer compare.
280 { ISD::SETCC, MVT::v4i64, 4 },
281 { ISD::SETCC, MVT::v8i32, 4 },
282 { ISD::SETCC, MVT::v16i16, 4 },
283 { ISD::SETCC, MVT::v32i8, 4 },
284 };
285
286 static const X86CostTblEntry AVX2CostTbl[] = {
287 { ISD::SETCC, MVT::v4i64, 1 },
288 { ISD::SETCC, MVT::v8i32, 1 },
289 { ISD::SETCC, MVT::v16i16, 1 },
290 { ISD::SETCC, MVT::v32i8, 1 },
291 };
292
293 if (ST->hasAVX2()) {
294 int Idx = FindInTable(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
295 if (Idx != -1)
296 return LT.first * AVX2CostTbl[Idx].Cost;
297 }
298
299 if (ST->hasAVX()) {
300 int Idx = FindInTable(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
301 if (Idx != -1)
302 return LT.first * AVX1CostTbl[Idx].Cost;
303 }
304
305 if (ST->hasSSE42()) {
306 int Idx = FindInTable(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
307 if (Idx != -1)
308 return LT.first * SSE42CostTbl[Idx].Cost;
309 }
310
311 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
312 }
313
314 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
315 unsigned Index) const {
316 assert(Val->isVectorTy() && "This must be a vector type");
317
318 if (Index != -1U) {
319 // Legalize the type.
320 std::pair LT = TLI->getTypeLegalizationCost(Val);
321
322 // This type is legalized to a scalar type.
323 if (!LT.second.isVector())
324 return 0;
325
326 // The type may be split. Normalize the index to the new type.
327 unsigned Width = LT.second.getVectorNumElements();
328 Index = Index % Width;
329
330 // Floating point scalars are already located in index #0.
331 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
332 return 0;
333 }
334
335 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
336 }
337
338 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
339 unsigned AddressSpace) const {
340 // Legalize the type.
341 std::pair LT = TLI->getTypeLegalizationCost(Src);
342 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
343 "Invalid Opcode");
344
345 // Each load/store unit costs 1.
346 unsigned Cost = LT.first * 1;
347
348 // On Sandybridge 256bit load/stores are double pumped
349 // (but not on Haswell).
350 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
351 Cost*=2;
352
353 return Cost;
354 }
3131 InstrInfo(),
3232 FrameLowering(Subtarget),
3333 TLInfo(*this),
34 TSInfo(*this), STTI(&TLInfo), VTTI(&TLInfo) {
34 TSInfo(*this) {
3535 }
3636
3737 namespace {
2020 #include "XCoreSubtarget.h"
2121 #include "llvm/IR/DataLayout.h"
2222 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetTransformImpl.h"
2423
2524 namespace llvm {
2625
3130 XCoreFrameLowering FrameLowering;
3231 XCoreTargetLowering TLInfo;
3332 XCoreSelectionDAGInfo TSInfo;
34 ScalarTargetTransformImpl STTI;
35 VectorTargetTransformImpl VTTI;
3633 public:
3734 XCoreTargetMachine(const Target &T, StringRef TT,
3835 StringRef CPU, StringRef FS, const TargetOptions &Options,
5552 virtual const TargetRegisterInfo *getRegisterInfo() const {
5653 return &InstrInfo.getRegisterInfo();
5754 }
58 virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const {
59 return &STTI;
60 }
61 virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const {
62 return &VTTI;
63 }
6455 virtual const DataLayout *getDataLayout() const { return &DL; }
6556
6657 // Pass Pipeline Configuration
3737 #include "llvm/Support/ToolOutputFile.h"
3838 #include "llvm/Target/TargetLibraryInfo.h"
3939 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/TargetTransformInfo.h"
4140 #include
4241 using namespace llvm;
4342
319318 TLI->disableAllFunctions();
320319 PM.add(TLI);
321320
322 if (target.get()) {
323 PM.add(createNoTTIPass(target->getScalarTargetTransformInfo(),
324 target->getVectorTargetTransformInfo()));
325 }
321 // Add intenal analysis passes from the target machine.
322 Target.addAnalysisPasses(PM);
326323
327324 // Add the target data from the target machine, if it exists, or the module.
328325 if (const DataLayout *TD = Target.getDataLayout())
4141 #include "llvm/Target/TargetMachine.h"
4242 #include "llvm/Target/TargetOptions.h"
4343 #include "llvm/Target/TargetRegisterInfo.h"
44 #include "llvm/TargetTransformInfo.h"
4544 #include "llvm/Transforms/IPO.h"
4645 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
4746 using namespace llvm;
371370
372371 // Add an appropriate DataLayout instance for this module...
373372 passes.add(new DataLayout(*_target->getDataLayout()));
374 passes.add(createNoTTIPass(_target->getScalarTargetTransformInfo(),
375 _target->getVectorTargetTransformInfo()));
373 _target->addAnalysisPasses(passes);
376374
377375 // Enabling internalize here would use its AllButMain variant. It
378376 // keeps only main if it exists and does nothing for libraries. Instead
4242 #include "llvm/Support/ToolOutputFile.h"
4343 #include "llvm/Target/TargetLibraryInfo.h"
4444 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/TargetTransformInfo.h"
4645 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
4746 #include
4847 #include
656655 Machine = GetTargetMachine(Triple(ModuleTriple));
657656 std::auto_ptr TM(Machine);
658657
659 if (TM.get()) {
660 Passes.add(createNoTTIPass(TM->getScalarTargetTransformInfo(),
661 TM->getVectorTargetTransformInfo()));
662 }
658 // Add internal analysis passes from the target machine.
659 if (TM.get())
660 TM->addAnalysisPasses(Passes);
663661
664662 OwningPtr FPasses;
665663 if (OptLevelO1 || OptLevelO2 || OptLevelOs || OptLevelOz || OptLevelO3) {