llvm.org GIT mirror llvm / ae5612e
[AMDGPU][llvm-mc] s_setreg* - Fix order of operands Order should match the sp3 syntax, where destination (simm16 denoting the hwreg) is coming first. Differential Revision: http://reviews.llvm.org/D19161 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266617 91177308-0d34-0410-b5e6-96231b3b80d8 Artem Tamazov 4 years ago
3 changed file(s) with 10 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
422422
423423 defm S_SETREG_B32 : SOPK_m <
424424 sopk<0x13, 0x12>, "s_setreg_b32", (outs),
425 (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16"
425 (ins SReg_32:$sdst, u16imm:$simm16), " $simm16, $sdst"
426426 >;
427427 // FIXME: Not on SI?
428428 //defm S_GETREG_REGRD_B32 : SOPK_32 , "s_getreg_regrd_b32", []>;
429429 defm S_SETREG_IMM32_B32 : SOPK_IMM32 <
430430 sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs),
431 (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16"
431 (ins i32imm:$imm, u16imm:$simm16), " $simm16, $imm"
432432 >;
433433
434434 //===----------------------------------------------------------------------===//
7676 // SICI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
7777 // VI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
7878
79 s_setreg_b32 s2, 0x6
80 // SICI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb9]
81 // VI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
79 s_setreg_b32 0x6, s2
80 // SICI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x82,0xb9]
81 // VI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9]
8282
83 s_setreg_imm32_b32 0xff, 0x6
84 // SICI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
85 // VI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
83 s_setreg_imm32_b32 0x6, 0xff
84 // SICI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x80,0xba,0xff,0x00,0x00,0x00]
85 // VI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
5050 # VI: s_getreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb8]
5151 0x06 0x00 0x82 0xb8
5252
53 # VI: s_setreg_b32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb9]
53 # VI: s_setreg_b32 0x6, s2 ; encoding: [0x06,0x00,0x02,0xb9]
5454 0x06 0x00 0x02 0xb9
5555
56 # VI: s_setreg_imm32_b32 0xff, 0x6 ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
56 # VI: s_setreg_imm32_b32 0x6, 0xff ; encoding: [0x06,0x00,0x00,0xba,0xff,0x00,0x00,0x00]
5757 0x06 0x00 0x00 0xba 0xff 0x00 0x00 0x00