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ARM: enforce SRS decoding constraints git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8 Amaury de la Vieuville 7 years ago
2 changed file(s) with 14 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
17671767 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
17681768
17691769 if (pred == 0xF) {
1770 // Ambiguous with RFE and SRS
17701771 switch (Inst.getOpcode()) {
17711772 case ARM::LDMDA:
17721773 Inst.setOpcode(ARM::RFEDA);
18171818 Inst.setOpcode(ARM::SRSIB_UPD);
18181819 break;
18191820 default:
1820 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1821 return MCDisassembler::Fail;
18211822 }
18221823
18231824 // For stores (which become SRS's, the only operand is the mode.
18241825 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1826 // Check SRS encoding constraints
1827 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1828 fieldFromInstruction(Insn, 20, 1) == 0))
1829 return MCDisassembler::Fail;
1830
18251831 Inst.addOperand(
18261832 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
18271833 return S;
None # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
1
2 # Opcode=0 Name=PHI Format=(42)
31 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
42 # -------------------------------------------------------------------------------------------------
97 # B6.1.10 SRS
108 # Inst{19-8} = 0xd05
119 # Inst{7-5} = 0b000
12 0x83 0x1c 0xc5 0xf8
10 # RUN: echo "0x83 0x1c 0xc5 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
11
12 # RUN: echo "0x00 0x00 0x20 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
13 # RUN: echo "0xff 0xff 0xaf 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
14 # RUN: echo "0x13 0x00 0xa0 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
15
16 # CHECK: invalid instruction encoding