llvm.org GIT mirror llvm / ae43cab
Fix known typos Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8 Alp Toker 5 years ago
111 changed file(s) with 234 addition(s) and 233 deletion(s). Raw diff Collapse all Expand all
9393
9494 /// The standard DAG builder does not normally include terminators as DAG
9595 /// nodes because it does not create the necessary dependencies to prevent
96 /// reordering. A specialized scheduler can overide
96 /// reordering. A specialized scheduler can override
9797 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
9898 /// it has taken responsibility for scheduling the terminator correctly.
9999 bool CanHandleTerminators;
157157 /// model.
158158 ///
159159 /// Compute and return the expected latency of this instruction independent of
160 /// a particular use. computeOperandLatency is the prefered API, but this is
160 /// a particular use. computeOperandLatency is the preferred API, but this is
161161 /// occasionally useful to help estimate instruction cost.
162162 ///
163163 /// If UseDefaultDefLatency is false and no new machine sched model is
3232
3333 enum Status {
3434 StatusOK,
35 StatusUnsupported, // zlib is unavaliable
36 StatusOutOfMemory, // there was not enough memory
37 StatusBufferTooShort, // there was not enough room in the output buffer
38 StatusInvalidArg, // invalid input parameter
39 StatusInvalidData // data was corrupted or incomplete
35 StatusUnsupported, // zlib is unavailable
36 StatusOutOfMemory, // there was not enough memory
37 StatusBufferTooShort, // there was not enough room in the output buffer
38 StatusInvalidArg, // invalid input parameter
39 StatusInvalidData // data was corrupted or incomplete
4040 };
4141
4242 bool isAvailable();
9494 /// memory was not allocated using the allocateMappedMemory method.
9595 /// \p Block describes the memory block to be protected.
9696 /// \p Flags specifies the new protection state to be assigned to the block.
97 /// \p ErrMsg [out] returns a string describing any error that occured.
97 /// \p ErrMsg [out] returns a string describing any error that occurred.
9898 ///
9999 /// If \p Flags is MF_WRITE, the actual behavior varies
100100 /// with the operating system (i.e. MF_READ | MF_WRITE on Windows) and the
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This header defines ComputeASanStackFrameLayout and auxilary data structs.
9 // This header defines ComputeASanStackFrameLayout and auxiliary data structs.
1010 //
1111 //===----------------------------------------------------------------------===//
1212 #ifndef LLVM_TRANSFORMS_UTILS_ASANSTACKFRAMELAYOUT_H
2323 * Read LLVM IR from a memory buffer and convert it into an in-memory Module
2424 * object. Returns 0 on success.
2525 * Optionally returns a human-readable description of any errors that
26 * occured during parsing IR. OutMessage must be disposed with
26 * occurred during parsing IR. OutMessage must be disposed with
2727 * LLVMDisposeMessage.
2828 *
2929 * @see llvm::ParseIR()
153153 /// isIdentifiedFunctionLocal - Return true if V is umabigously identified
154154 /// at the function-level. Different IdentifiedFunctionLocals can't alias.
155155 /// Further, an IdentifiedFunctionLocal can not alias with any function
156 /// arguments other than itself, which is not neccessarily true for
156 /// arguments other than itself, which is not necessarily true for
157157 /// IdentifiedObjects.
158158 static bool isIdentifiedFunctionLocal(const Value *V)
159159 {
31773177
31783178 /// Check if we can delinearize the subscripts. If the SCEVs representing the
31793179 /// source and destination array references are recurrences on a nested loop,
3180 /// this function flattens the nested recurrences into seperate recurrences
3180 /// this function flattens the nested recurrences into separate recurrences
31813181 /// for each loop level.
31823182 bool
31833183 DependenceAnalysis::tryDelinearize(const SCEV *SrcSCEV, const SCEV *DstSCEV,
71427142 const SCEV *Start = this->getStart();
71437143 const SCEV *Step = this->getStepRecurrence(SE);
71447144
7145 // Build the SCEV representation of the cannonical induction variable in the
7145 // Build the SCEV representation of the canonical induction variable in the
71467146 // loop of this SCEV.
71477147 const SCEV *Zero = SE.getConstant(this->getType(), 0);
71487148 const SCEV *One = SE.getConstant(this->getType(), 1);
71887188 else
71897189 Rem = Quotient;
71907190
7191 // Scale up the cannonical induction variable IV by whatever remains from the
7191 // Scale up the canonical induction variable IV by whatever remains from the
71927192 // Step after division by the GCD: the GCD is the size of all the sub-array.
71937193 if (Step != GCD) {
71947194 Step = SCEVDivision::divide(SE, Step, GCD);
71957195 IV = SE.getMulExpr(IV, Step);
71967196 }
7197 // The access function in the current subscript is computed as the cannonical
7197 // The access function in the current subscript is computed as the canonical
71987198 // induction variable IV (potentially scaled up by the step) and offset by
71997199 // Rem, the offset of delinearization in the sub-array.
72007200 const SCEV *Index = SE.getAddExpr(IV, Rem);
76517651
76527652 typedef DenseMap VerifyMap;
76537653
7654 /// replaceSubString - Replaces all occurences of From in Str with To.
7654 /// replaceSubString - Replaces all occurrences of From in Str with To.
76557655 static void replaceSubString(std::string &Str, StringRef From, StringRef To) {
76567656 size_t Pos = 0;
76577657 while ((Pos = Str.find(From, Pos)) != std::string::npos) {
594594 if (RC == reinterpret_cast(-1))
595595 AntiDepReg = 0;
596596
597 // Look for a suitable register to use to break the anti-depenence.
597 // Look for a suitable register to use to break the anti-dependence.
598598 //
599599 // TODO: Instead of picking the first free register, consider which might
600600 // be the best.
19751975 }
19761976 else {
19771977 // After updating ZoneCritResIdx and ExpectedLatency, check if we're
1978 // resource limited. If a stall occured, bumpCycle does this.
1978 // resource limited. If a stall occurred, bumpCycle does this.
19791979 unsigned LFactor = SchedModel->getLatencyFactor();
19801980 IsResourceLimited =
19811981 (int)(getCriticalCount() - (getScheduledLatency() * LFactor))
6262 /// not already. It also adds the current node as a successor of the
6363 /// specified node.
6464 bool SUnit::addPred(const SDep &D, bool Required) {
65 // If this node already has this depenence, don't add a redundant one.
65 // If this node already has this dependence, don't add a redundant one.
6666 for (SmallVectorImpl::iterator I = Preds.begin(), E = Preds.end();
6767 I != E; ++I) {
6868 // Zero-latency weak edges may be added purely for heuristic ordering. Don't
67396739 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
67406740 }
67416741
6742 // The next optimizations are desireable only if SELECT_CC can be lowered.
6742 // The next optimizations are desirable only if SELECT_CC can be lowered.
67436743 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
67446744 // having to say they don't support SELECT_CC on every type the DAG knows
67456745 // about, since there is no way to mark an opcode illegal at all value types
67966796 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
67976797 }
67986798
6799 // The next optimizations are desireable only if SELECT_CC can be lowered.
6799 // The next optimizations are desirable only if SELECT_CC can be lowered.
68006800 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
68016801 // having to say they don't support SELECT_CC on every type the DAG knows
68026802 // about, since there is no way to mark an opcode illegal at all value types
82648264 // The width of the type must be a power of 2 and greater than 8-bits.
82658265 // Otherwise the load cannot be represented in LLVM IR.
82668266 // Moreover, if we shifted with a non-8-bits multiple, the slice
8267 // will be accross several bytes. We do not support that.
8267 // will be across several bytes. We do not support that.
82688268 unsigned Width = User->getValueSizeInBits(0);
82698269 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
82708270 return 0;
4040 ++CheckStartIdx;
4141
4242 assert(getMetaIdx() == CheckStartIdx &&
43 "Unexpected additonal definition in Patchpoint intrinsic.");
43 "Unexpected additional definition in Patchpoint intrinsic.");
4444 #endif
4545 }
4646
163163
164164 typedef struct _LineNumberInfo
165165 {
166 /* x86 Offset from the begining of the method*/
167 unsigned int Offset;
168
169 /* source line number from the begining of the source file */
166 /* x86 Offset from the beginning of the method*/
167 unsigned int Offset;
168
169 /* source line number from the beginning of the source file */
170170 unsigned int LineNumber;
171171
172172 } *pLineNumberInfo, LineNumberInfo;
190190 unsigned int method_size;
191191
192192 /* Line Table size in number of entries - Zero if none */
193 unsigned int line_number_size;
194
195 /* Pointer to the begining of the line numbers info array */
193 unsigned int line_number_size;
194
195 /* Pointer to the beginning of the line numbers info array */
196196 pLineNumberInfo line_number_table;
197197
198198 /* unique class ID */
11191119 callFunction((Function*)GVTOP(SRC), ArgVals);
11201120 }
11211121
1122 // auxilary function for shift operations
1122 // auxiliary function for shift operations
11231123 static unsigned getShiftAmount(uint64_t orgShiftAmount,
11241124 llvm::APInt valueToShift) {
11251125 unsigned valueWidth = valueToShift.getBitWidth();
7777 sys::Memory::MF_WRITE,
7878 ec);
7979 if (ec) {
80 // FIXME: Add error propogation to the interface.
80 // FIXME: Add error propagation to the interface.
8181 return NULL;
8282 }
8383
115115
116116 virtual void updateGOTEntries(StringRef Name, uint64_t Addr);
117117
118 // Relocation entries for symbols whose position-independant offset is
118 // Relocation entries for symbols whose position-independent offset is
119119 // updated in a global offset table.
120120 typedef SmallVector GOTRelocations;
121121 GOTRelocations GOTEntries; // List of entries requiring finalization.
13401340 if (!getTargetParser().ParseDirective(ID))
13411341 return false;
13421342
1343 // Next, check the extention directive map to see if any extension has
1343 // Next, check the extension directive map to see if any extension has
13441344 // registered itself to parse this directive.
13451345 std::pair Handler =
13461346 ExtensionDirectiveMap.lookup(IDVal);
31633163 ///
31643164 /// With the support added for named parameters there may be code out there that
31653165 /// is transitioning from positional parameters. In versions of gas that did
3166 /// not support named parameters they would be ignored on the macro defintion.
3166 /// not support named parameters they would be ignored on the macro definition.
31673167 /// But to support both styles of parameters this is not possible so if a macro
3168 /// defintion has named parameters but does not use them and has what appears
3168 /// definition has named parameters but does not use them and has what appears
31693169 /// to be positional parameters, strings like $1, $2, ... and $n, then issue a
31703170 /// warning that the positional parameter found in body which have no effect.
31713171 /// Hoping the developer will either remove the named parameters from the macro
3172 /// definiton so the positional parameters get used if that was what was
3172 /// definition so the positional parameters get used if that was what was
31733173 /// intended or change the macro to use the named parameters. It is possible
31743174 /// this warning will trigger when the none of the named parameters are used
31753175 /// and the strings like $1 are infact to simply to be passed trough unchanged.
37753775 // change the payload.
37763776 if (isSignaling()) {
37773777 result = opInvalidOp;
3778 // For consistency, propogate the sign of the sNaN to the qNaN.
3778 // For consistency, propagate the sign of the sNaN to the qNaN.
37793779 makeNaN(false, isNegative(), 0);
37803780 }
37813781 break;
10951095 // to include in this word.
10961096 val[breakWord] = pVal[breakWord+offset] >> wordShift;
10971097
1098 // Deal with sign extenstion in the break word, and possibly the word before
1098 // Deal with sign extension in the break word, and possibly the word before
10991099 // it.
11001100 if (isNegative()) {
11011101 if (wordShift > bitsInWord) {
245245 return Best;
246246 }
247247
248 /// CommaSeparateAndAddOccurence - A wrapper around Handler->addOccurence() that
249 /// does special handling of cl::CommaSeparated options.
250 static bool CommaSeparateAndAddOccurence(Option *Handler, unsigned pos,
251 StringRef ArgName,
252 StringRef Value, bool MultiArg = false)
253 {
248 /// CommaSeparateAndAddOccurrence - A wrapper around Handler->addOccurrence()
249 /// that does special handling of cl::CommaSeparated options.
250 static bool CommaSeparateAndAddOccurrence(Option *Handler, unsigned pos,
251 StringRef ArgName, StringRef Value,
252 bool MultiArg = false) {
254253 // Check to see if this option accepts a comma separated list of values. If
255254 // it does, we have to split up the value into multiple values.
256255 if (Handler->getMiscFlags() & CommaSeparated) {
311310
312311 // If this isn't a multi-arg option, just run the handler.
313312 if (NumAdditionalVals == 0)
314 return CommaSeparateAndAddOccurence(Handler, i, ArgName, Value);
313 return CommaSeparateAndAddOccurrence(Handler, i, ArgName, Value);
315314
316315 // If it is, run the handle several times.
317316 bool MultiArg = false;
318317
319318 if (Value.data()) {
320 if (CommaSeparateAndAddOccurence(Handler, i, ArgName, Value, MultiArg))
319 if (CommaSeparateAndAddOccurrence(Handler, i, ArgName, Value, MultiArg))
321320 return true;
322321 --NumAdditionalVals;
323322 MultiArg = true;
328327 return Handler->error("not enough values!");
329328 Value = argv[++i];
330329
331 if (CommaSeparateAndAddOccurence(Handler, i, ArgName, Value, MultiArg))
330 if (CommaSeparateAndAddOccurrence(Handler, i, ArgName, Value, MultiArg))
332331 return true;
333332 MultiArg = true;
334333 --NumAdditionalVals;
15011500 std::vector SortedCategories;
15021501 std::map > CategorizedOptions;
15031502
1504 // Collect registered option categories into vector in preperation for
1503 // Collect registered option categories into vector in preparation for
15051504 // sorting.
15061505 for (OptionCatSet::const_iterator I = RegisteredOptionCategories->begin(),
15071506 E = RegisteredOptionCategories->end();
3131
3232 #ifdef LLVM_ON_WIN32
3333 const char *separators = "\\/";
34 const char prefered_separator = '\\';
34 const char preferred_separator = '\\';
3535 #else
3636 const char separators = '/';
37 const char prefered_separator = '/';
37 const char preferred_separator = '/';
3838 #endif
3939
4040 StringRef find_first_component(StringRef path) {
402402
403403 if (!component_has_sep && !(path.empty() || is_root_name)) {
404404 // Add a separator.
405 path.push_back(prefered_separator);
405 path.push_back(preferred_separator);
406406 }
407407
408408 path.append(i->begin(), i->end());
531531 sopno subno;
532532 # define BACKSL (1<
533533
534 pos = HERE(); /* repetion op, if any, covers from here */
535
536 assert(MORE()); /* caller should have ensured this */
537 c = GETNEXT();
534 pos = HERE(); /* repetition op, if any, covers from here */
535
536 assert(MORE()); /* caller should have ensured this */
537 c = GETNEXT();
538538 if (c == '\\') {
539539 REQUIRE(MORE(), REG_EESCAPE);
540540 c = BACKSL | GETNEXT();
610610 int &AccessScale, int &MinOffset,
611611 int &MaxOffset) const {
612612 switch (MI.getOpcode()) {
613 default: llvm_unreachable("Unkown load/store kind");
613 default:
614 llvm_unreachable("Unknown load/store kind");
614615 case TargetOpcode::DBG_VALUE:
615616 AccessScale = 1;
616617 MinOffset = INT_MIN;
64316431 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
64326432 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
64336433
6434 // Table lookup extention
6434 // Table lookup extension
64356435 class NI_TBX op2, bits<2> len, bit op,
64366436 string asmop, string OpS, RegisterOperand OpVPR,
64376437 RegisterOperand VecList>
15161516 unsigned Q = fieldFromInstruction(Insn, 30, 1);
15171517 unsigned S = fieldFromInstruction(Insn, 10, 3);
15181518 unsigned lane = 0;
1519 // Calculate the number of lanes by number of vectors and transfered bytes.
1519 // Calculate the number of lanes by number of vectors and transferred bytes.
15201520 // NumLanes = 16 bytes / bytes of each lane
15211521 unsigned NumLanes = 16 / (TransferBytes / NumVecs);
15221522 switch (NumLanes) {
14061406
14071407 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
14081408 SDValue &OffImm) {
1409 // This *must* succeed since it's used for the irreplacable ldrex and strex
1409 // This *must* succeed since it's used for the irreplaceable ldrex and strex
14101410 // instructions.
14111411 Base = N;
14121412 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
59865986 if (cast(Op)->getOrdering() <= Monotonic)
59875987 return Op;
59885988
5989 // Aquire/Release load/store is not legal for targets without a
5989 // Acquire/Release load/store is not legal for targets without a
59905990 // dmb or equivalent available.
59915991 return SDValue();
59925992 }
1018810188 case MVT::v2f64: {
1018910189 // For any little-endian targets with neon, we can support unaligned ld/st
1019010190 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
10191 // A big-endian target may also explictly support unaligned accesses
10191 // A big-endian target may also explicitly support unaligned accesses
1019210192 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
1019310193 if (Fast)
1019410194 *Fast = true;
213213 }
214214
215215 // GPRs without the PC but with APSR. Some instructions allow accessing the
216 // APSR, while actually encoding PC in the register field. This is usefull
216 // APSR, while actually encoding PC in the register field. This is useful
217217 // for assembly and disassembly only.
218218 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
219219 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
17201720 SchedVar
17211721 SwiftWriteLM13CyNo, SwiftWriteP01OneCycle,
17221722 SwiftVLDMPerm3]>,
1723 // Load of a Q register (not neccessarily true). We should not be mapping to
1723 // Load of a Q register (not necessarily true). We should not be mapping to
17241724 // 4 S registers, either.
17251725 SchedVar
17261726 SwiftWriteLM4CyNo, SwiftWriteLM4CyNo]>,
18571857 // Assume 5 D registers.
18581858 SchedVar,
18591859 SchedVar,
1860 // Asume three Q registers.
1860 // Assume three Q registers.
18611861 SchedVar,
18621862 SchedVar,
18631863 // Assume 7 D registers.
532532 // creates a sequence of shift, and, or instructions to construct values.
533533 // These sequences are recognized by the ISel and have zero-cost. Not so for
534534 // the vectorized code. Because we have support for v2i64 but not i64 those
535 // sequences look particularily beneficial to vectorize.
535 // sequences look particularly beneficial to vectorize.
536536 // To work around this we increase the cost of v2i64 operations to make them
537537 // seem less beneficial.
538538 if (LT.second == MVT::v2i64 &&
182182
183183 inline static const char *InstSyncBOptToString(unsigned val) {
184184 switch (val) {
185 default: llvm_unreachable("Unkown memory operation");
185 default:
186 llvm_unreachable("Unknown memory operation");
186187 case RESERVED_0: return "#0x0";
187188 case RESERVED_1: return "#0x1";
188189 case RESERVED_2: return "#0x2";
10341034 }
10351035
10361036 void ARMELFStreamer::emitFnEnd() {
1037 assert(FnStart && ".fnstart must preceeds .fnend");
1037 assert(FnStart && ".fnstart must precedes .fnend");
10381038
10391039 // Emit unwind opcodes if there is no .handlerdata directive
10401040 if (!ExTab && !CantUnwind)
284284 // Update the intermediate instruction to with the kill flag.
285285 if (KillingInstr) {
286286 bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
287 (void)Added; // supress compiler warning
287 (void)Added; // suppress compiler warning
288288 assert(Added && "Must successfully update kill flag");
289289 removeKillInfo(I2, KilledOperand);
290290 }
342342 // Update I1 to set the kill flag. This flag will later be picked up by
343343 // the new COMBINE instruction.
344344 bool Added = I1->addRegisterKilled(KilledOperand, TRI);
345 (void)Added; // supress compiler warning
345 (void)Added; // suppress compiler warning
346346 assert(Added && "Must successfully update kill flag");
347347 }
348348 DoInsertAtI1 = false;
15211521 if (PB != Latch) {
15221522 Tmp2.clear();
15231523 bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp2, false);
1524 (void)NotAnalyzed; // supress compiler warning
1524 (void)NotAnalyzed; // suppress compiler warning
15251525 assert (!NotAnalyzed && "Should be analyzable!");
15261526 if (TB != Header && (Tmp2.empty() || FB != Header))
15271527 TII->InsertBranch(*PB, NewPH, 0, EmptyCond, DL);
15331533 // Insert an unconditional branch to the header.
15341534 TB = FB = 0;
15351535 bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false);
1536 (void)LatchNotAnalyzed; // supress compiler warning
1536 (void)LatchNotAnalyzed; // suppress compiler warning
15371537 assert (!LatchNotAnalyzed && "Should be analyzable!");
15381538 if (!TB && !FB)
15391539 TII->InsertBranch(*Latch, Header, 0, EmptyCond, DL);
17921792 return true;
17931793
17941794 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1795 // Check addressing mode and retreive non-ext equivalent instruction.
1795 // Check addressing mode and retrieve non-ext equivalent instruction.
17961796
17971797 switch (getAddrMode(MI)) {
17981798 case HexagonII::Absolute :
18261826 return NonExtOpcode;
18271827
18281828 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
1829 // Check addressing mode and retreive non-ext equivalent instruction.
1829 // Check addressing mode and retrieve non-ext equivalent instruction.
18301830 switch (getAddrMode(MI)) {
18311831 case HexagonII::Absolute :
18321832 return Hexagon::getBasedWithImmOffset(MI->getOpcode());
868868 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
869869 Instructions.push_back(TempInst);
870870 TempInst.clear();
871 // And finaly, create original instruction with low part
871 // And finally, create original instruction with low part
872872 // of offset and new base.
873873 TempInst.setOpcode(Inst.getOpcode());
874874 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
12461246 return false;
12471247 }
12481248 // Look for the existing symbol, we should check if
1249 // we need to assigne the propper RegisterKind.
1249 // we need to assigne the proper RegisterKind.
12501250 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
12511251 return false;
12521252 // Else drop to expression parsing.
35183518 MSAPat<(DstVT (bitconvert SrcVT:$src)),
35193519 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
35203520
3521 // These are endian-independant because the element size doesnt change
3521 // These are endian-independent because the element size doesnt change
35223522 def : MSABitconvertPat;
35233523 def : MSABitconvertPat;
35243524 def : MSABitconvertPat;
12571257
12581258 // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
12591259 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
1260 // stored type to i16 and propogate the "real" type as the memory type.
1260 // stored type to i16 and propagate the "real" type as the memory type.
12611261 bool NeedExt = false;
12621262 if (EltVT.getSizeInBits() < 16)
12631263 NeedExt = true;
20732073
20742074 // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
20752075 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
2076 // loaded type to i16 and propogate the "real" type as the memory type.
2076 // loaded type to i16 and propagate the "real" type as the memory type.
20772077 bool NeedTrunc = false;
20782078 if (EltVT.getSizeInBits() < 16) {
20792079 EltVT = MVT::i16;
21602160 // Since LDU/LDG are target nodes, we cannot rely on DAG type
21612161 // legalization.
21622162 // Therefore, we must ensure the type is legal. For i1 and i8, we set the
2163 // loaded type to i16 and propogate the "real" type as the memory type.
2163 // loaded type to i16 and propagate the "real" type as the memory type.
21642164 bool NeedTrunc = false;
21652165 if (EltVT.getSizeInBits() < 16) {
21662166 EltVT = MVT::i16;
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This pass replaces occurences of __nvvm_reflect("string") with an
9 // This pass replaces occurrences of __nvvm_reflect("string") with an
1010 // integer based on -nvvm-reflect-list string= option given to this pass.
1111 // If an undefined string value is seen in a call to __nvvm_reflect("string"),
1212 // a default value of 0 will be used.
8383
8484 char NVVMReflect::ID = 0;
8585 INITIALIZE_PASS(NVVMReflect, "nvvm-reflect",
86 "Replace occurences of __nvvm_reflect() calls with 0/1", false,
86 "Replace occurrences of __nvvm_reflect() calls with 0/1", false,
8787 false)
8888
8989 static cl::list
72047204 // you might suspect (sizeof(vector) bytes after the last requested
72057205 // load), but rather sizeof(vector) - 1 bytes after the last
72067206 // requested vector. The point of this is to avoid a page fault if the
7207 // base address happend to be aligned. This works because if the base
7207 // base address happened to be aligned. This works because if the base
72087208 // address is aligned, then adding less than a full vector length will
72097209 // cause the last vector in the sequence to be (re)loaded. Otherwise,
72107210 // the next vector will be fetched as you might suspect was necessary.
6767 /// various memory regions on the hardware. On the CPU
6868 /// all of the address spaces point to the same memory,
6969 /// however on the GPU, each address space points to
70 /// a seperate piece of memory that is unique from other
70 /// a separate piece of memory that is unique from other
7171 /// memory locations.
7272 namespace AMDGPUAS {
7373 enum AddressSpaces {
223223 /// Compute the reversed DFS post order of Blocks
224224 void orderBlocks(MachineFunction *MF);
225225
226 // Function originaly from CFGStructTraits
226 // Function originally from CFGStructTraits
227227 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
228228 DebugLoc DL = DebugLoc());
229229 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
5252
5353 ~SIMCCodeEmitter() { }
5454
55 /// \breif Encode the instruction and write it to the OS.
55 /// \brief Encode the instruction and write it to the OS.
5656 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
5757 SmallVectorImpl &Fixups) const;
5858
4949
5050 /// IfCvt pass can generate "disabled" ALU clause marker that need to be
5151 /// removed and their content affected to the previous alu clause.
52 /// This function parse instructions after CFAlu untill it find a disabled
52 /// This function parse instructions after CFAlu until it find a disabled
5353 /// CFAlu and merge the content, or an enabled CFAlu.
5454 void cleanPotentialDisabledCFAlu(MachineInstr *CFAlu) const;
5555
5151
5252 #define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
5353
54 /// \brief Defines for extracting register infomation from register encoding
54 /// \brief Defines for extracting register information from register encoding
5555 #define HW_REG_MASK 0x1ff
5656 #define HW_CHAN_SHIFT 9
5757
989989 DAG.getCondCode(ISD::SETNE));
990990 }
991991
992 /// LLVM generates byte-addresed pointers. For indirect addressing, we need to
992 /// LLVM generates byte-addressed pointers. For indirect addressing, we need to
993993 /// convert these pointers to a register index. Each register holds
994994 /// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
995995 /// \p StackWidth, which tells us how many of the 4 sub-registrers will be used
13881388 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
13891389 MachinePointerInfo(UndefValue::get(PtrTy)),
13901390 MemVT, false, false, 4);
1391 // 4 is the prefered alignment for
1392 // the CONSTANT memory space.
1391 // 4 is the preferred alignment for
1392 // the CONSTANT memory space.
13931393 InVals.push_back(Arg);
13941394 }
13951395 return Chain;
4242 unsigned Gen;
4343 /// Each OpenCL kernel has nine implicit parameters that are stored in the
4444 /// first nine dwords of a Vertex Buffer. These implicit parameters are
45 /// lowered to load instructions which retreive the values from the Vertex
45 /// lowered to load instructions which retrieve the values from the Vertex
4646 /// Buffer.
4747 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
4848 SDLoc DL, unsigned DwordOffset) const;
137137 /// Same but using const index set instead of MI set.
138138 bool fitsConstReadLimitations(const std::vector&) const;
139139
140 /// \breif Vector instructions are instructions that must fill all
140 /// \brief Vector instructions are instructions that must fill all
141141 /// instruction slots within an instruction group.
142142 bool isVector(const MachineInstr &MI) const;
143143
22622262 //===--------------------------------------------------------------------===//
22632263 //===---------------------------------------------------------------------===//
22642264 // Custom Inserter for Branches and returns, this eventually will be a
2265 // seperate pass
2265 // separate pass
22662266 //===---------------------------------------------------------------------===//
22672267 let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in {
22682268 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
6565 }
6666
6767 /// \returns register to PV chan mapping for bundle/single instructions that
68 /// immediatly precedes I.
68 /// immediately precedes I.
6969 DenseMap getPreviousVector(MachineBasicBlock::iterator I)
7070 const {
7171 DenseMap Result;
10821082 else
10831083 return;
10841084
1085 // Nothing todo if they fit naturaly
1085 // Nothing to do if they fit naturally
10861086 if (fitsRegClass(DAG, Operand, RegClass))
10871087 return;
10881088
121121 return RC;
122122
123123 // If this register has a sub-register, we can safely assume it is a 32-bit
124 // register, becuase all of SI's sub-registers are 32-bit.
124 // register, because all of SI's sub-registers are 32-bit.
125125 if (isSGPRClass(RC)) {
126126 return &AMDGPU::SGPR_32RegClass;
127127 } else {
3434 // Assembler: %hi(addr) or %lm(addr)
3535 MO_HI,
3636
37 // Extract bits 43-22 of an adress. Only for sethi.
37 // Extract bits 43-22 of an address. Only for sethi.
3838 // Assembler: %h44(addr)
3939 MO_H44,
4040
10751075 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
10761076 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
10771077
1078 // The remaing cases are 1, 2, 0/1/3 and 0/2/3. All these are
1078 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
10791079 // can be done by inverting the low CC bit and applying one of the
10801080 // sign-based extractions above.
10811081 if (CCMask == (CCValid & SystemZ::CCMASK_1))
5252 MachineFunction &MF = *MBB->getParent();
5353
5454 // Get two load or store instructions. Use the original instruction for one
55 // of them (arbitarily the second here) and create a clone for the other.
55 // of them (arbitrarily the second here) and create a clone for the other.
5656 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
5757 MBB->insert(MI, EarlierMI);
5858
758758 // Subtraction
759759 //===----------------------------------------------------------------------===//
760760
761 // Plain substraction. Although immediate forms exist, we use the
761 // Plain subtraction. Although immediate forms exist, we use the
762762 // add-immediate instruction instead.
763763 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
764764 // Subtraction of a register.
562562 uint8_t prefixPresent[0x100];
563563 /* contains the location (for use with the reader) of the prefix byte */
564564 uint64_t prefixLocations[0x100];
565 /* The value of the vector extention prefix(EVEX/VEX/XOP), if present */
565 /* The value of the vector extension prefix(EVEX/VEX/XOP), if present */
566566 uint8_t vectorExtensionPrefix[4];
567567 /* The type of the vector extension prefix */
568568 VectorExtensionType vectorExtensionType;
15111511 // garbage. Indeed, only the less significant bit is supposed to be accurate.
15121512 // If we read more than the lsb, we may see non-zero values whereas lsb
15131513 // is zero. Therefore, we have to truncate Op0Reg to i1 for the select.
1514 // This is acheived by performing TEST against 1.
1514 // This is achieved by performing TEST against 1.
15151515 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
15161516 .addReg(Op0Reg).addImm(1);
15171517 unsigned ResultReg = createResultReg(RC);
576576 //===----------------------------------------------------------------------===//
577577 // Processor instruction itineraries.
578578
579 // IssueWidth is analagous to the number of decode units. Core and its
579 // IssueWidth is analogous to the number of decode units. Core and its
580580 // descendents, including Nehalem and SandyBridge have 4 decoders.
581581 // Resources beyond the decoder operate on micro-ops and are bufferred
582582 // so adjacent micro-ops don't directly compete.
153153 return false;
154154 }
155155 }
156 } while (CE->hasNUsesOrMore(1)); // We need to check becasue a recursive
157 // sibbling may have used 'CE' when createReplacementInstr was called.
156 } while (CE->hasNUsesOrMore(1)); // We need to check because a recursive
157 // sibling may have used 'CE' when createReplacementInstr was called.
158158 CE->destroyConstant();
159159 return true;
160160 }
7676 }
7777
7878 // True if A is better than B.
79 static bool IsBetterCannonical(const GlobalVariable &A,
80 const GlobalVariable &B) {
79 static bool IsBetterCanonical(const GlobalVariable &A,
80 const GlobalVariable &B) {
8181 if (!A.hasLocalLinkage() && B.hasLocalLinkage())
8282 return true;
8383
159159 // If this is the first constant we find or if the old one is local,
160160 // replace with the current one. If the current is externally visible
161161 // it cannot be replace, but can be the canonical constant we merge with.
162 if (Slot == 0 || IsBetterCannonical(*GV, *Slot))
162 if (Slot == 0 || IsBetterCanonical(*GV, *Slot))
163163 Slot = GV;
164164 }
165165
722722
723723 // Helper for writeThunk,
724724 // Selects proper bitcast operation,
725 // but a bit simplier then CastInst::getCastOpcode.
725 // but a bit simpler then CastInst::getCastOpcode.
726726 static Value* createCast(IRBuilder &Builder, Value *V, Type *DestTy) {
727727 Type *SrcTy = V->getType();
728728 if (SrcTy->isIntegerTy() && DestTy->isPointerTy())
7676 // A single load+store correctly handles overlapping memory in the memmove
7777 // case.
7878 uint64_t Size = MemOpLength->getLimitedValue();
79 assert(Size && "0-sized memory transfering should be removed already.");
79 assert(Size && "0-sized memory transferring should be removed already.");
8080
8181 if (Size > 8 || (Size&(Size-1)))
8282 return 0; // If not 1/2/4/8 bytes, exit.
683683 return ReplaceInstUsesWith(CI, ConstantVector::get(NewElems));
684684 }
685685
686 // Couldn't simplify - cannonicalize constant to the RHS.
686 // Couldn't simplify - canonicalize constant to the RHS.
687687 std::swap(Arg0, Arg1);
688688 }
689689
11921192 // will not occur because the result of OpI is exact (as we will for
11931193 // FMul, for example) is hopeless. However, we *can* nonetheless
11941194 // frequently know that double rounding cannot occur (or that it is
1195 // innoculous) by taking advantage of the specific structure of
1195 // innocuous) by taking advantage of the specific structure of
11961196 // infinitely-precise results that admit double rounding.
11971197 //
1198 // Specifically, if OpWidth >= 2*DstWdith+1 and DstWidth is sufficent
1198 // Specifically, if OpWidth >= 2*DstWdith+1 and DstWidth is sufficient
11991199 // to represent both sources, we can guarantee that the double
12001200 // rounding is innocuous (See p50 of Figueroa's 2000 PhD thesis,
12011201 // "A Rigorous Framework for Fully Supporting the IEEE Standard ..."
20472047
20482048 /// \brief Check if the order of \p Op0 and \p Op1 as operand in an ICmpInst
20492049 /// should be swapped.
2050 /// The descision is based on how many times these two operands are reused
2050 /// The decision is based on how many times these two operands are reused
20512051 /// as subtract operands and their positions in those instructions.
20522052 /// The rational is that several architectures use the same instruction for
20532053 /// both subtract and cmp, thus it is better if the order of those operands
20632063 // Each time Op0 is the first operand, count -1: swapping is bad, the
20642064 // subtract has already the same layout as the compare.
20652065 // Each time Op0 is the second operand, count +1: swapping is good, the
2066 // subtract has a diffrent layout as the compare.
2066 // subtract has a different layout as the compare.
20672067 // At the end, if the benefit is greater than 0, Op0 should come second to
20682068 // expose more CSE opportunities.
20692069 int GlobalSwapBenefits = 0;
10121012 // references from RHSOp0 to LHSOp0, so we don't need to shift the mask.
10131013 // If newRHS == newLHS, we want to remap any references from newRHS to
10141014 // newLHS so that we can properly identify splats that may occur due to
1015 // obfuscation accross the two vectors.
1015 // obfuscation across the two vectors.
10161016 if (eltMask >= 0 && newRHS != NULL && newLHS != newRHS)
10171017 eltMask += newLHSWidth;
10181018 }
16281628 return &BI;
16291629 }
16301630
1631 // Cannonicalize fcmp_one -> fcmp_oeq
1631 // Canonicalize fcmp_one -> fcmp_oeq
16321632 FCmpInst::Predicate FPred; Value *Y;
16331633 if (match(&BI, m_Br(m_FCmp(FPred, m_Value(X), m_Value(Y)),
16341634 TrueDest, FalseDest)) &&
16441644 return &BI;
16451645 }
16461646
1647 // Cannonicalize icmp_ne -> icmp_eq
1647 // Canonicalize icmp_ne -> icmp_eq
16481648 ICmpInst::Predicate IPred;
16491649 if (match(&BI, m_Br(m_ICmp(IPred, m_Value(X), m_Value(Y)),
16501650 TrueDest, FalseDest)) &&
248248 ShadowMapping Mapping;
249249
250250 // OR-ing shadow offset if more efficient (at least on x86),
251 // but on ppc64 we have to use add since the shadow offset is not neccesary
251 // but on ppc64 we have to use add since the shadow offset is not necessary
252252 // 1/8-th of the address space.
253253 Mapping.OrShadowOffset = !IsPPC64 && !ClShort64BitOffset;
254254
19631963 // Now, get the shadow for the RetVal.
19641964 if (!I.getType()->isSized()) return;
19651965 IRBuilder<> IRBBefore(&I);
1966 // Untill we have full dynamic coverage, make sure the retval shadow is 0.
1966 // Until we have full dynamic coverage, make sure the retval shadow is 0.
19671967 Value *Base = getShadowPtrForRetval(&I, IRBBefore);
19681968 IRBBefore.CreateAlignedStore(getCleanShadow(&I), Base, kShadowTLSAlignment);
19691969 Instruction *NextInsn = 0;
486486 }
487487
488488 // Both llvm and ThreadSanitizer atomic operations are based on C++11/C1x
489 // standards. For background see C++11 standard. A slightly older, publically
489 // standards. For background see C++11 standard. A slightly older, publicly
490490 // available draft of the standard (not entirely up-to-date, but close enough
491491 // for casual browsing) is available here:
492492 // http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2011/n3242.pdf
381381 void clear();
382382
383383 /// Conservatively merge the two RRInfo. Returns true if a partial merge has
384 /// occured, false otherwise.
384 /// occurred, false otherwise.
385385 bool Merge(const RRInfo &Other);
386386
387387 };
658658 /// which pass through this block. This is only valid after both the
659659 /// top-down and bottom-up traversals are complete.
660660 ///
661 /// Returns true if overflow occured. Returns false if overflow did not
661 /// Returns true if overflow occurred. Returns false if overflow did not
662662 /// occur.
663663 bool GetAllPathCountWithOverflow(unsigned &PathCount) const {
664664 if (TopDownPathCount == OverflowOccurredValue ||
666666 return true;
667667 unsigned long long Product =
668668 (unsigned long long)TopDownPathCount*BottomUpPathCount;
669 // Overflow occured if any of the upper bits of Product are set or if all
669 // Overflow occurred if any of the upper bits of Product are set or if all
670670 // the lower bits of Product are all set.
671671 return (Product >> 32) ||
672672 ((PathCount = Product) == OverflowOccurredValue);
710710
711711 // In order to be consistent, we clear the top down pointers when by adding
712712 // TopDownPathCount becomes OverflowOccurredValue even though "true" overflow
713 // has not occured.
713 // has not occurred.
714714 if (TopDownPathCount == OverflowOccurredValue) {
715715 clearTopDownPointers();
716716 return;
754754
755755 // In order to be consistent, we clear the top down pointers when by adding
756756 // BottomUpPathCount becomes OverflowOccurredValue even though "true" overflow
757 // has not occured.
757 // has not occurred.
758758 if (BottomUpPathCount == OverflowOccurredValue) {
759759 clearBottomUpPointers();
760760 return;
18071807 // pointer has multiple owners implying that we must be more conservative.
18081808 //
18091809 // This comes up in the context of a pointer being ``KnownSafe''. In the
1810 // presense of a block being initialized, the frontend will emit the
1810 // presence of a block being initialized, the frontend will emit the
18111811 // objc_retain on the original pointer and the release on the pointer loaded
18121812 // from the alloca. The optimizer will through the provenance analysis
18131813 // realize that the two are related, but since we only require KnownSafe in
18141814 // one direction, will match the inner retain on the original pointer with
18151815 // the guard release on the original pointer. This is fixed by ensuring that
1816 // in the presense of allocas we only unconditionally remove pointers if
1816 // in the presence of allocas we only unconditionally remove pointers if
18171817 // both our retain and our release are KnownSafe.
18181818 if (StoreInst *SI = dyn_cast(Inst)) {
18191819 if (AreAnyUnderlyingObjectsAnAlloca(SI->getPointerOperand())) {
108108 bool preliminaryScreen();
109109
110110 /// Check if the given conditional branch is based on the comparison
111 /// beween a variable and zero, and if the variable is non-zero, the
112 /// control yeilds to the loop entry. If the branch matches the behavior,
111 /// between a variable and zero, and if the variable is non-zero, the
112 /// control yields to the loop entry. If the branch matches the behavior,
113113 /// the variable involved in the comparion is returned. This function will
114114 /// be called to see if the precondition and postcondition of the loop
115115 /// are in desirable form.
520520 // TripCnt is exactly the number of iterations the loop has
521521 TripCnt = NewCount;
522522
523 // If the popoulation counter's initial value is not zero, insert Add Inst.
523 // If the population counter's initial value is not zero, insert Add Inst.
524524 Value *CntInitVal = CntPhi->getIncomingValueForBlock(PreHead);
525525 ConstantInt *InitConst = dyn_cast(CntInitVal);
526526 if (!InitConst || !InitConst->isZero()) {
239239 BranchInst *BI = dyn_cast(CurrBlock->getTerminator());
240240 CmpInst *CI = dyn_cast(BI->getCondition());
241241 CmpInst::Predicate Predicate = CI->getPredicate();
242 // Cannonicalize icmp_ne -> icmp_eq, fcmp_one -> fcmp_oeq
242 // Canonicalize icmp_ne -> icmp_eq, fcmp_one -> fcmp_oeq
243243 if ((Predicate == CmpInst::ICMP_NE) || (Predicate == CmpInst::FCMP_ONE)) {
244244 CI->setPredicate(ICmpInst::getInversePredicate(Predicate));
245245 BI->swapSuccessors();
6161 SinkCommon("simplifycfg-sink-common", cl::Hidden, cl::init(true),
6262 cl::desc("Sink common instructions down to the end block"));
6363
64 static cl::opt
65 HoistCondStores("simplifycfg-hoist-cond-stores", cl::Hidden, cl::init(true),
66 cl::desc("Hoist conditional stores if an unconditional store preceeds"));
64 static cl::opt HoistCondStores(
65 "simplifycfg-hoist-cond-stores", cl::Hidden, cl::init(true),
66 cl::desc("Hoist conditional stores if an unconditional store precedes"));
6767
6868 STATISTIC(NumBitMaps, "Number of switch instructions turned into bitmaps");
6969 STATISTIC(NumLookupTables, "Number of switch instructions turned into lookup tables");
23702370 setDebugLocFromInst(Builder, RdxDesc.StartValue);
23712371
23722372 // We need to generate a reduction vector from the incoming scalar.
2373 // To do so, we need to generate the 'identity' vector and overide
2373 // To do so, we need to generate the 'identity' vector and override
23742374 // one of the elements with the incoming scalar reduction. We need
23752375 // to do it in the vector-loop preheader.
23762376 Builder.SetInsertPoint(LoopBypassBlocks.front()->getTerminator());
37123712 }
37133713
37143714 bool NeedDepCheck = false;
3715 // Check whether there is the possiblity of dependency because of underlying
3716 // objects being the same.
3715 // Check whether there is the possibility of dependency because of
3716 // underlying objects being the same.
37173717 typedef SmallVector ValueVector;
37183718 ValueVector TempObjects;
37193719 GetUnderlyingObjects(Ptr, TempObjects, DL);
18701870 StoreListMap StoreRefs;
18711871 };
18721872
1873 /// \brief Check that the Values in the slice in VL array are still existant in
1873 /// \brief Check that the Values in the slice in VL array are still existent in
18741874 /// the WeakVH array.
18751875 /// Vectorization of part of the VL array may cause later values in the VL array
18761876 /// to become invalid. We track when this has happened in the WeakVH array.
25152515 break;
25162516 }
25172517
2518 // Start over at the next instruction of a differnt type (or the end).
2518 // Start over at the next instruction of a different type (or the end).
25192519 IncIt = SameTypeIt;
25202520 }
25212521 }
33 ; getUDivExpr()->getZeroExtendExpr()->isLoopBackedgeGuardedBy()
44 ;
55 ; We actually want SCEV simplification to fail gracefully in this
6 ; case, so there's no output to check, just the absense of stack overflow.
6 ; case, so there's no output to check, just the absence of stack overflow.
77
88 @c = common global i8 0, align 1
99
4242 ; OPT: define
4343 ; OPT: store i32 1
4444 ; OPT: store i16 4
45 ; Remove a load and propogate the value from store.
45 ; Remove a load and propagate the value from store.
4646 ; OPT: ret i32 1
4747 %s.addr = alloca i32*, align 8
4848 %A.addr = alloca %struct.StructA*, align 8
9797 ; OPT: define
9898 ; OPT: store i32 1
9999 ; OPT: store i16 4
100 ; Remove a load and propogate the value from store.
100 ; Remove a load and propagate the value from store.
101101 ; OPT: ret i32 1
102102 %A.addr = alloca %struct.StructA*, align 8
103103 %B.addr = alloca %struct.StructB*, align 8
126126 ; OPT: define
127127 ; OPT: store i32 1
128128 ; OPT: store i32 4
129 ; Remove a load and propogate the value from store.
129 ; Remove a load and propagate the value from store.
130130 ; OPT: ret i32 1
131131 %A.addr = alloca %struct.StructA*, align 8
132132 %B.addr = alloca %struct.StructB*, align 8
154154 ; OPT: define
155155 ; OPT: store i32 1
156156 ; OPT: store i32 4
157 ; Remove a load and propogate the value from store.
157 ; Remove a load and propagate the value from store.
158158 ; OPT: ret i32 1
159159 %A.addr = alloca %struct.StructA*, align 8
160160 %B.addr = alloca %struct.StructB*, align 8
183183 ; OPT: define
184184 ; OPT: store i32 1
185185 ; OPT: store i32 4
186 ; Remove a load and propogate the value from store.
186 ; Remove a load and propagate the value from store.
187187 ; OPT: ret i32 1
188188 %A.addr = alloca %struct.StructA*, align 8
189189 %S.addr = alloca %struct.StructS*, align 8
211211 ; OPT: define
212212 ; OPT: store i32 1
213213 ; OPT: store i16 4
214 ; Remove a load and propogate the value from store.
214 ; Remove a load and propagate the value from store.
215215 ; OPT: ret i32 1
216216 %A.addr = alloca %struct.StructA*, align 8
217217 %S.addr = alloca %struct.StructS*, align 8
239239 ; OPT: define
240240 ; OPT: store i32 1
241241 ; OPT: store i32 4
242 ; Remove a load and propogate the value from store.
242 ; Remove a load and propagate the value from store.
243243 ; OPT: ret i32 1
244244 %S.addr = alloca %struct.StructS*, align 8
245245 %S2.addr = alloca %struct.StructS2*, align 8
267267 ; OPT: define
268268 ; OPT: store i32 1
269269 ; OPT: store i16 4
270 ; Remove a load and propogate the value from store.
270 ; Remove a load and propagate the value from store.
271271 ; OPT: ret i32 1
272272 %S.addr = alloca %struct.StructS*, align 8
273273 %S2.addr = alloca %struct.StructS2*, align 8
295295 ; OPT: define
296296 ; OPT: store i32 1
297297 ; OPT: store i32 4
298 ; Remove a load and propogate the value from store.
298 ; Remove a load and propagate the value from store.
299299 ; OPT: ret i32 1
300300 %C.addr = alloca %struct.StructC*, align 8
301301 %D.addr = alloca %struct.StructD*, align 8
412412
413413 let test_global_variables () =
414414 let (++) x f = f x; x in
415 let fourty_two32 = const_int i32_type 42 in
415 let forty_two32 = const_int i32_type 42 in
416416
417417 group "declarations"; begin
418418 (* CHECK: @GVar01 = external global i32
443443 * CHECK: @QGVar02 = addrspace(3) global i32 42
444444 * CHECK: @QGVar03 = addrspace(3) global i32 42
445445 *)
446 let g = define_global "GVar02" fourty_two32 m in
446 let g = define_global "GVar02" forty_two32 m in
447447 let g2 = declare_global i32_type "GVar03" m ++
448 set_initializer fourty_two32 in
448 set_initializer forty_two32 in
449449 insist (not (is_declaration g));
450450 insist (not (is_declaration g2));
451451 insist ((global_initializer g) == (global_initializer g2));
452452
453 let g = define_qualified_global "QGVar02" fourty_two32 3 m in
453 let g = define_qualified_global "QGVar02" forty_two32 3 m in
454454 let g2 = declare_qualified_global i32_type "QGVar03" 3 m ++
455 set_initializer fourty_two32 in
455 set_initializer forty_two32 in
456456 insist (not (is_declaration g));
457457 insist (not (is_declaration g2));
458458 insist ((global_initializer g) == (global_initializer g2));
461461 (* CHECK: GVar04{{.*}}thread_local
462462 *)
463463 group "threadlocal";
464 let g = define_global "GVar04" fourty_two32 m ++
464 let g = define_global "GVar04" forty_two32 m ++
465465 set_thread_local true in
466466 insist (is_thread_local g);
467467
468468 (* CHECK: GVar05{{.*}}thread_local(initialexec)
469469 *)
470470 group "threadlocal_mode";
471 let g = define_global "GVar05" fourty_two32 m ++
471 let g = define_global "GVar05" forty_two32 m ++
472472 set_thread_local_mode ThreadLocalMode.InitialExec in
473473 insist ((thread_local_mode g) = ThreadLocalMode.InitialExec);
474474
475475 (* CHECK: GVar06{{.*}}externally_initialized
476476 *)
477477 group "externally_initialized";
478 let g = define_global "GVar06" fourty_two32 m ++
478 let g = define_global "GVar06" forty_two32 m ++
479479 set_externally_initialized true in
480480 insist (is_externally_initialized g);
481481
482482 (* CHECK-NOWHERE-NOT: GVar07
483483 *)
484484 group "delete";
485 let g = define_global "GVar07" fourty_two32 m in
485 let g = define_global "GVar07" forty_two32 m in
486486 delete_global g;
487487
488488 (* CHECK: ConstGlobalVar{{.*}}constant
489489 *)
490490 group "constant";
491 let g = define_global "ConstGlobalVar" fourty_two32 m in
491 let g = define_global "ConstGlobalVar" forty_two32 m in
492492 insist (not (is_global_constant g));
493493 set_global_constant true g;
494494 insist (is_global_constant g);
1212 ;structs at varying alignments. Each test is run for arm, thumb2 and thumb1.
1313 ;We check for the strings in the generated object code using llvm-objdump
1414 ;because it provides better assurance that we are generating instructions
15 ;for the correct architecture. Otherwise we could accidently generate an
15 ;for the correct architecture. Otherwise we could accidentally generate an
1616 ;ARM instruction for THUMB1 and wouldn't detect it because the assembly
1717 ;code representation is the same, but the object code would be generated
1818 ;incorrectly. For each test we check for the label, a load instruction of the
66
77 ; Test that the MI Scheduler's initPolicy does not crash when i32 is
88 ; unsupported. The content of the asm check below is unimportant. It
9 ; only verifies that the code generator ran succesfully.
9 ; only verifies that the code generator ran successfully.
1010 ;
1111 ; CHECK-LABEL: @f
1212 ; CHECK: mov.w &y, &x
99 ; The legalizer legalized ; the <4 x i8>'s into <4 x i32>'s, then a call to
1010 ; isVSplat() returned the splat value for as a 32-bit APInt
1111 ; (255), but the zeroinitializer splat value as an 8-bit APInt (0). The
12 ; assertion occured when trying to check the values were bitwise inverses of
12 ; assertion occurred when trying to check the values were bitwise inverses of
1313 ; each-other.
1414 ;
1515 ; It should at least successfully build.
None ; Test that floating-point compares are ommitted if CC already has the
0 ; Test that floating-point compares are omitted if CC already has the
11 ; right value.
22 ;
33 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
207207 ret void
208208 }
209209
210 ; This is the largest frame size for which the prepatory increment for
210 ; This is the largest frame size for which the preparatory increment for
211211 ; "lmg %r14, %r15, ..." can be done using AGHI.
212212 define void @f5(i32 *%ptr, i64 %x) {
213213 ; CHECK-LABEL: f5:
241241 ret void
242242 }
243243
244 ; This is the smallest frame size for which the prepatory increment for
244 ; This is the smallest frame size for which the preparatory increment for
245245 ; "lmg %r14, %r15, ..." needs to be done using AGFI.
246246 define void @f6(i32 *%ptr, i64 %x) {
247247 ; CHECK-LABEL: f6:
None ; Test that compares are ommitted if CC already has the right value
0 ; Test that compares are omitted if CC already has the right value
11 ; (z10 version).
22 ;
33 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
None ; Test that compares are ommitted if CC already has the right value
0 ; Test that compares are omitted if CC already has the right value
11 ; (z196 version).
22 ;
33 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
22 ; During X86 fastisel, the address of indirect call was resolved
33 ; through bitcast, ptrtoint, and inttoptr instructions. This is valid
44 ; only if the related instructions are in that same basic block, otherwise
5 ; we may reference variables that were not live accross basic blocks
5 ; we may reference variables that were not live across basic blocks
66 ; resulting in undefined virtual registers.
77 ;
88 ; In this example, this is illustrated by a the spill/reload of the
2424 ; CHECK: movq [[ARG2_SLOT]], %rdi
2525 ; Load the second argument
2626 ; CHECK: movq [[ARG2_SLOT]], %rsi
27 ; Load the thrid argument
27 ; Load the third argument
2828 ; CHECK: movq [[ARG2_SLOT]], %rdx
2929 ; Load the function pointer.
3030 ; CHECK: movq [[LOADED_PTR_SLOT]], [[FCT_PTR:%[a-z]+]]
6363 ; CHECK: movq [[ARG2_SLOT]], %rdi
6464 ; Load the second argument
6565 ; CHECK: movq [[ARG2_SLOT]], %rsi
66 ; Load the thrid argument
66 ; Load the third argument
6767 ; CHECK: movq [[ARG2_SLOT]], %rdx
6868 ; Load the function pointer.
6969 ; CHECK: movq [[LOADED_PTR_SLOT]], [[FCT_PTR:%[a-z]+]]
102102 ; CHECK: movq [[ARG2_SLOT]], %rdi
103103 ; Load the second argument
104104 ; CHECK: movq [[ARG2_SLOT]], %rsi
105 ; Load the thrid argument
105 ; Load the third argument
106106 ; CHECK: movq [[ARG2_SLOT]], %rdx
107107 ; Load the function pointer.
108108 ; CHECK: movq [[LOADED_PTR_SLOT]], [[FCT_PTR:%[a-z]+]]
700700
701701 define void @unanalyzable_branch_to_best_succ(i1 %cond) {
702702 ; Ensure that we can handle unanalyzable branches where the destination block
703 ; gets selected as the optimal sucessor to merge.
703 ; gets selected as the optimal successor to merge.
704704 ;
705705 ; CHECK: unanalyzable_branch_to_best_succ
706706 ; CHECK: %entry
55 %class.Complex = type { float, float }
66
77
8 ; Check that independant slices leads to independant loads then the slices leads to
8 ; Check that independent slices leads to independent loads then the slices leads to
99 ; different register file.
1010 ;
1111 ; The layout is:
33 ; %tmp1676 = xor i32 %tmp1634, %tmp1530 have zero demanded bits after
44 ; DAGCombiner optimization pass. These are changed to undef and in turn
55 ; the successor shl(s) become shl undef, 1. This pattern then matches
6 ; shl x, 1 -> add x, x. add undef, undef doesn't guarentee the low
6 ; shl x, 1 -> add x, x. add undef, undef doesn't guarantee the low
77 ; order bit is zero and is incorrect.
88 ;
99 ; See rdar://9453156 and rdar://9487392.
55
66 ; 10 bytes of data in this DW_FORM_block1 representation of the location of 'tls'
77 ; CHECK: .byte 10{{ *}}# DW_AT_location
8 ; DW_OP_const8u (0x0e == 14) of adress
8 ; DW_OP_const8u (0x0e == 14) of address
99 ; CHECK: .byte 14
1010 ; The debug relocation of the address of the tls variable
1111 ; CHECK: .quad tls@DTPOFF
88 @ then libunwind will reconstruct the stack pointer from the frame pointer.
99 @ The reconstruction code is implemented by two different unwind opcode:
1010 @ (i) the unwind opcode to copy stack offset from the other register, and
11 @ (ii) the unwind opcode to add or substract the stack offset.
11 @ (ii) the unwind opcode to add or subtract the stack offset.
1212 @
1313 @ This file includes several cases separated by different range of -offset
1414 @
22 ; RUN: FileCheck %s
33
44 ; FIXME: This file needs to be in .s form!
5 ; We wanna test relocatable thumb function call,
5 ; We want to test relocatable thumb function call,
66 ; but ARMAsmParser cannot handle "bl foo(PLT)" yet
77
88 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:32-n32"
None // The purpose of this test is to verify that bss sections are emited correctly.
0 // The purpose of this test is to verify that bss sections are emitted correctly.
11
22 // RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -s | FileCheck %s
33 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -s | FileCheck %s
5151
5252 // /1000029 == 4 + 10 + (5 * (2 + (20 * 10 * 1000) + 1))
5353 // v | | v ~~~~~~~~~~~~~~ v
54 // table size v v "p0" pad NUL seperator
54 // table size v v "p0" pad NUL separator
5555 // "s12345678\0" # of pad sections
5656 //
5757 // CHECK: Section {
None // The purpose of this test is to verify that bss sections are emited correctly.
0 // The purpose of this test is to verify that bss sections are emitted correctly.
11
22 // RUN: llvm-mc -filetype=obj -triple i686-apple-darwin9 %s | llvm-readobj -s | FileCheck %s
33 // RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 %s | llvm-readobj -s | FileCheck %s
3030
3131 define i32 @outer2(i32* %ptr) {
3232 ; Test that an inbounds GEP disables this -- it isn't safe in general as
33 ; wrapping changes the behavior of lessthan and greaterthan comparisions.
33 ; wrapping changes the behavior of lessthan and greaterthan comparisons.
3434 ; CHECK-LABEL: @outer2(
3535 ; CHECK: call i32 @inner2
3636 ; CHECK: ret i32
33
44 ; PR16073
55
6 ; Because we were caching value pointers accross a function call that could RAUW
6 ; Because we were caching value pointers across a function call that could RAUW
77 ; we would generate an undefined value store below:
88 ; SCEVExpander::expandCodeFor would change a value (the start value of an
99 ; induction) that we cached in the induction variable list.
2727 declare i8* @objc_msgSend(i8*, i8*, ...)
2828
2929
30 ; In the presense of allocas, unconditionally remove retain/release pairs only
30 ; In the presence of allocas, unconditionally remove retain/release pairs only
3131 ; if they are known safe in both directions. This prevents matching up an inner
3232 ; retain with the boundary guarding release in the following situation:
3333 ;
335335 ret void
336336 }
337337
338 ; Make sure in the presense of allocas, if we find a cfghazard we do not perform
338 ; Make sure in the presence of allocas, if we find a cfghazard we do not perform
339339 ; code motion even if we are known safe. These two concepts are separate and
340340 ; should be treated as such.
341341 ;
108108 CurOffset += Size;
109109 }
110110 }
111 // Adjust to keep code and data aligned on seperate pages.
111 // Adjust to keep code and data aligned on separate pages.
112112 CurOffset = (CurOffset + MaxAlign - 1) / MaxAlign * MaxAlign;
113113 for (size_t i = 0, e = NumSections; i != e; ++i) {
114114 Allocation &Section = UnmappedSections[i];
9595 virtual bool executeCode(uint64_t Address,
9696 int &RetVal);
9797
98 /// Minimum alignment for memory permissions. Used to seperate code and
98 /// Minimum alignment for memory permissions. Used to separate code and
9999 /// data regions to make sure data doesn't get marked as code or vice
100100 /// versa.
101101 ///
8080 /// descriptive text of the encountered error.
8181 virtual bool executeCode(uint64_t Address, int &RetVal);
8282
83 /// Minimum alignment for memory permissions. Used to seperate code and
83 /// Minimum alignment for memory permissions. Used to separate code and
8484 /// data regions to make sure data doesn't get marked as code or vice
8585 /// versa.
8686 ///
99 /// \file
1010 /// \brief This file implements the COFF-specific dumper for llvm-objdump.
1111 /// It outputs the Win64 EH data structures as plain text.
12 /// The encoding of the unwind codes is decribed in MSDN:
12 /// The encoding of the unwind codes is described in MSDN:
1313 /// http://msdn.microsoft.com/en-us/library/ck9asaa9.aspx
1414 ///
1515 //===----------------------------------------------------------------------===//
6767 memcpy(Buffer2->getBufferStart(), "AABBCCDDEEFFGGHHIIJJ", 20);
6868 // Do *not* commit buffer.
6969 }
70 // Verify file does not exist (because buffer not commited).
70 // Verify file does not exist (because buffer not committed).
7171 bool Exists = false;
7272 ASSERT_NO_ERROR(fs::exists(Twine(File2), Exists));
7373 EXPECT_FALSE(Exists);
1616
1717 namespace {
1818
19 // In these first two tests all of the origional_uintx values are truncated
19 // In these first two tests all of the original_uintx values are truncated
2020 // except for 64. We could avoid this, but there's really no point.
2121
2222 TEST(SwapByteOrder, UnsignedRoundTrip) {
2424 // in every byte.
2525 uint64_t value = 1;
2626 for (std::size_t i = 0; i <= sizeof(value); ++i) {
27 uint8_t origional_uint8 = static_cast(value);
28 EXPECT_EQ(origional_uint8,
29 sys::SwapByteOrder(sys::SwapByteOrder(origional_uint8)));
27 uint8_t original_uint8 = static_cast(value);
28 EXPECT_EQ(original_uint8,
29 sys::SwapByteOrder(sys::SwapByteOrder(original_uint8)));
3030
31 uint16_t origional_uint16 = static_cast(value);
32 EXPECT_EQ(origional_uint16,
33 sys::SwapByteOrder(sys::SwapByteOrder(origional_uint16)));
31 uint16_t original_uint16 = static_cast(value);
32 EXPECT_EQ(original_uint16,
33 sys::SwapByteOrder(sys::SwapByteOrder(original_uint16)));
3434
35 uint32_t origional_uint32 = static_cast(value);
36 EXPECT_EQ(origional_uint32,
37 sys::SwapByteOrder(sys::SwapByteOrder(origional_uint32)));
35 uint32_t original_uint32 = static_cast(value);
36 EXPECT_EQ(original_uint32,
37 sys::SwapByteOrder(sys::SwapByteOrder(original_uint32)));
3838
39 uint64_t origional_uint64 = static_cast(value);
40 EXPECT_EQ(origional_uint64,
41 sys::SwapByteOrder(sys::SwapByteOrder(origional_uint64)));
39 uint64_t original_uint64 = static_cast(value);
40 EXPECT_EQ(original_uint64,
41 sys::SwapByteOrder(sys::SwapByteOrder(original_uint64)));
4242
4343 value = (value << 8) | 0x55; // binary 0101 0101.
4444 }
4949 // in every byte.
5050 uint64_t value = 1;
5151 for (std::size_t i = 0; i <= sizeof(value); ++i) {
52 int8_t origional_int8 = static_cast(value);
53 EXPECT_EQ(origional_int8,
54 sys::SwapByteOrder(sys::SwapByteOrder(origional_int8)));
52 int8_t original_int8 = static_cast(value);
53 EXPECT_EQ(original_int8,
54 sys::SwapByteOrder(sys::SwapByteOrder(original_int8)));
5555
56 int16_t origional_int16 = static_cast(value);
57 EXPECT_EQ(origional_int16,
58 sys::SwapByteOrder(sys::SwapByteOrder(origional_int16)));
56 int16_t original_int16 = static_cast(value);
57 EXPECT_EQ(original_int16,
58 sys::SwapByteOrder(sys::SwapByteOrder(original_int16)));
5959
60 int32_t origional_int32 = static_cast(value);
61 EXPECT_EQ(origional_int32,
62 sys::SwapByteOrder(sys::SwapByteOrder(origional_int32)));
60 int32_t original_int32 = static_cast(value);
61 EXPECT_EQ(original_int32,
62 sys::SwapByteOrder(sys::SwapByteOrder(original_int32)));
6363
64 int64_t origional_int64 = static_cast(value);
65 EXPECT_EQ(origional_int64,
66 sys::SwapByteOrder(sys::SwapByteOrder(origional_int64)));
64 int64_t original_int64 = static_cast(value);
65 EXPECT_EQ(original_int64,
66 sys::SwapByteOrder(sys::SwapByteOrder(original_int64)));
6767
6868 // Test other sign.
6969 value *= -1;
7070
71 origional_int8 = static_cast(value);
72 EXPECT_EQ(origional_int8,
73 sys::SwapByteOrder(sys::SwapByteOrder(origional_int8)));
71 original_int8 = static_cast(value);
72 EXPECT_EQ(original_int8,
73 sys::SwapByteOrder(sys::SwapByteOrder(original_int8)));
7474
75 origional_int16 = static_cast(value);
76 EXPECT_EQ(origional_int16,
77 sys::SwapByteOrder(sys::SwapByteOrder(origional_int16)));
75 original_int16 = static_cast(value);
76 EXPECT_EQ(original_int16,
77 sys::SwapByteOrder(sys::SwapByteOrder(original_int16)));
7878
79 origional_int32 = static_cast(value);
80 EXPECT_EQ(origional_int32,
81 sys::SwapByteOrder(sys::SwapByteOrder(origional_int32)));
79 original_int32 = static_cast(value);
80 EXPECT_EQ(original_int32,
81 sys::SwapByteOrder(sys::SwapByteOrder(original_int32)));
8282
83 origional_int64 = static_cast(value);
84 EXPECT_EQ(origional_int64,
85 sys::SwapByteOrder(sys::SwapByteOrder(origional_int64)));
83 original_int64 = static_cast(value);
84 EXPECT_EQ(original_int64,
85 sys::SwapByteOrder(sys::SwapByteOrder(original_int64)));
8686
8787 // Return to normal sign and twiddle.
8888 value *= -1;
334334
335335 // getSubClasses - Returns a constant BitVector of subclasses indexed by
336336 // EnumValue.
337 // The SubClasses vector includs an entry for this class.
337 // The SubClasses vector includes an entry for this class.
338338 const BitVector &getSubClasses() const { return SubClasses; }
339339
340340 // getSuperClasses - Returns a list of super classes ordered by EnumValue.
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file defines structures to encapsulate the machine model as decribed in
9 // This file defines structures to encapsulate the machine model as described in
1010 // the target description.
1111 //
1212 //===----------------------------------------------------------------------===//
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file defines structures to encapsulate the machine model as decribed in
9 // This file defines structures to encapsulate the machine model as described in
1010 // the target description.
1111 //
1212 //===----------------------------------------------------------------------===//
161161 // ModelName is a unique name used to name an instantiation of MCSchedModel.
162162 //
163163 // ModelDef is NULL for inferred Models. This happens when a processor defines
164 // an itinerary but no machine model. If the processer defines neither a machine
164 // an itinerary but no machine model. If the processor defines neither a machine
165165 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
166166 // the special "NoModel" field set to true.
167167 //
109109
110110 owners_name = find_owners(path)
111111
112 # be gramatically correct
112 # be grammatically correct
113113 print "The owner(s) of the (" + path + ") is(are) : " + str(owners_name)
114114
115115 exit(0)