llvm.org GIT mirror llvm / ae1c853
[LegacyPassManager] Remove TargetMachine constructors This provides a new way to access the TargetMachine through TargetPassConfig, as a dependency. The patterns replaced here are: * Passes handling a null TargetMachine call `getAnalysisIfAvailable<TargetPassConfig>`. * Passes not handling a null TargetMachine `addRequired<TargetPassConfig>` and call `getAnalysis<TargetPassConfig>`. * MachineFunctionPasses now use MF.getTarget(). * Remove all the TargetMachine constructors. * Remove INITIALIZE_TM_PASS. This fixes a crash when running `llc -start-before prologepilog`. PEI needs StackProtector, which gets constructed without a TargetMachine by the pass manager. The StackProtector pass doesn't handle the case where there is no TargetMachine, so it segfaults. Related to PR30324. Differential Revision: https://reviews.llvm.org/D33222 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303360 91177308-0d34-0410-b5e6-96231b3b80d8 Francis Visoiu Mistrih 3 years ago
53 changed file(s) with 423 addition(s) and 470 deletion(s). Raw diff Collapse all Expand all
3232
3333 /// List of target independent CodeGen pass IDs.
3434 namespace llvm {
35 FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
35 FunctionPass *createAtomicExpandPass();
3636
3737 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
3838 /// work well with unreachable basic blocks (what live ranges make sense for a
6565
6666 /// createCodeGenPreparePass - Transform the code to expose more pattern
6767 /// matching during instruction selection.
68 FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
68 FunctionPass *createCodeGenPreparePass();
6969
7070 /// createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather
7171 /// and scatter intrinsics with scalar code when target doesn't support them.
176176 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
177177 /// and eliminates abstract frame references.
178178 extern char &PrologEpilogCodeInserterID;
179 MachineFunctionPass *createPrologEpilogInserterPass(const TargetMachine *TM);
179 MachineFunctionPass *createPrologEpilogInserterPass();
180180
181181 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
182182 /// register allocation.
304304
305305 /// createStackProtectorPass - This pass adds stack protectors to functions.
306306 ///
307 FunctionPass *createStackProtectorPass(const TargetMachine *TM);
307 FunctionPass *createStackProtectorPass();
308308
309309 /// createMachineVerifierPass - This pass verifies cenerated machine code
310310 /// instructions for correctness.
313313
314314 /// createDwarfEHPass - This pass mulches exception handling code into a form
315315 /// adapted to code generation. Required if using dwarf exception handling.
316 FunctionPass *createDwarfEHPass(const TargetMachine *TM);
316 FunctionPass *createDwarfEHPass();
317317
318318 /// createWinEHPass - Prepares personality functions used by MSVC on Windows,
319319 /// in addition to the Itanium LSDA based personalities.
320 FunctionPass *createWinEHPass(const TargetMachine *TM);
320 FunctionPass *createWinEHPass();
321321
322322 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
323323 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
361361 /// InterleavedAccess Pass - This pass identifies and matches interleaved
362362 /// memory accesses to target specific intrinsics.
363363 ///
364 FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);
364 FunctionPass *createInterleavedAccessPass();
365365
366366 /// LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all
367367 /// TLS variables for the emulated TLS model.
368368 ///
369 ModulePass *createLowerEmuTLSPass(const TargetMachine *TM);
369 ModulePass *createLowerEmuTLSPass();
370370
371371 /// This pass lowers the @llvm.load.relative intrinsic to instructions.
372372 /// This is unsafe to do earlier because a pass may combine the constant
383383
384384 /// This pass splits the stack into a safe stack and an unsafe stack to
385385 /// protect against stack-based overflow vulnerabilities.
386 FunctionPass *createSafeStackPass(const TargetMachine *TM = nullptr);
386 FunctionPass *createSafeStackPass();
387387
388388 /// This pass detects subregister lanes in a virtual register that are used
389389 /// independently of other lanes and splits them into separate virtual
418418
419419 } // End llvm namespace
420420
421 /// Target machine pass initializer for passes with dependencies. Use with
422 /// INITIALIZE_TM_PASS_END.
423 #define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
424
425 /// Target machine pass initializer for passes with dependencies. Use with
426 /// INITIALIZE_TM_PASS_BEGIN.
427 #define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
428 PassInfo *PI = new PassInfo( \
429 name, arg, &passName::ID, \
430 PassInfo::NormalCtor_t(callDefaultCtor), cfg, analysis, \
431 PassInfo::TargetMachineCtor_t(callTargetMachineCtor)); \
432 Registry.registerPass(*PI, true); \
433 return PI; \
434 } \
435 static llvm::once_flag Initialize##passName##PassFlag; \
436 void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
437 llvm::call_once(Initialize##passName##PassFlag, \
438 initialize##passName##PassOnce, std::ref(Registry)); \
439 }
440
441 /// This initializer registers TargetMachine constructor, so the pass being
442 /// initialized can use target dependent interfaces. Please do not move this
443 /// macro to be together with INITIALIZE_PASS, which is a complete target
444 /// independent initializer, and we don't want to make libScalarOpts depend
445 /// on libCodeGen.
446 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
447 INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
448 INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)
449
450421 #endif
1818
1919 #include "llvm/ADT/SmallPtrSet.h"
2020 #include "llvm/ADT/Triple.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
2122 #include "llvm/IR/Dominators.h"
2223 #include "llvm/IR/ValueMap.h"
2324 #include "llvm/Pass.h"
5455 /// TLI - Keep a pointer of a TargetLowering to consult for determining
5556 /// target type sizes.
5657 const TargetLoweringBase *TLI = nullptr;
57 const Triple Trip;
58 Triple Trip;
5859
5960 Function *F;
6061 Module *M;
113114 public:
114115 static char ID; // Pass identification, replacement for typeid.
115116
116 StackProtector() : FunctionPass(ID) {
117 initializeStackProtectorPass(*PassRegistry::getPassRegistry());
118 }
119
120 StackProtector(const TargetMachine *TM)
121 : FunctionPass(ID), TM(TM), Trip(TM->getTargetTriple()),
122 SSPBufferSize(8) {
117 StackProtector() : FunctionPass(ID), SSPBufferSize(8) {
123118 initializeStackProtectorPass(*PassRegistry::getPassRegistry());
124119 }
125120
126121 void getAnalysisUsage(AnalysisUsage &AU) const override {
122 AU.addRequired();
127123 AU.addPreserved();
128124 }
129125
3131 class PassInfo {
3232 public:
3333 typedef Pass* (*NormalCtor_t)();
34 typedef Pass *(*TargetMachineCtor_t)(TargetMachine *);
3534
3635 private:
3736 StringRef PassName; // Nice name for Pass
4342 std::vector ItfImpl; // Interfaces implemented by this pass
4443
4544 NormalCtor_t NormalCtor;
46 TargetMachineCtor_t TargetMachineCtor;
4745
4846 public:
4947 /// PassInfo ctor - Do not call this directly, this should only be invoked
5048 /// through RegisterPass.
5149 PassInfo(StringRef name, StringRef arg, const void *pi, NormalCtor_t normal,
52 bool isCFGOnly, bool is_analysis,
53 TargetMachineCtor_t machine = nullptr)
50 bool isCFGOnly, bool is_analysis)
5451 : PassName(name), PassArgument(arg), PassID(pi), IsCFGOnlyPass(isCFGOnly),
55 IsAnalysis(is_analysis), IsAnalysisGroup(false), NormalCtor(normal),
56 TargetMachineCtor(machine) {}
52 IsAnalysis(is_analysis), IsAnalysisGroup(false), NormalCtor(normal) {}
5753 /// PassInfo ctor - Do not call this directly, this should only be invoked
5854 /// through RegisterPass. This version is for use by analysis groups; it
5955 /// does not auto-register the pass.
6056 PassInfo(StringRef name, const void *pi)
6157 : PassName(name), PassArgument(""), PassID(pi), IsCFGOnlyPass(false),
62 IsAnalysis(false), IsAnalysisGroup(true), NormalCtor(nullptr),
63 TargetMachineCtor(nullptr) {}
58 IsAnalysis(false), IsAnalysisGroup(true), NormalCtor(nullptr) {}
6459
6560 /// getPassName - Return the friendly name for the pass, never returns null
6661 ///
10095 NormalCtor = Ctor;
10196 }
10297
103 /// getTargetMachineCtor - Return a pointer to a function, that when called
104 /// with a TargetMachine, creates an instance of the pass and returns it.
105 /// This pointer may be null if there is no constructor with a TargetMachine
106 /// for the pass.
107 ///
108 TargetMachineCtor_t getTargetMachineCtor() const { return TargetMachineCtor; }
109 void setTargetMachineCtor(TargetMachineCtor_t Ctor) {
110 TargetMachineCtor = Ctor;
111 }
112
11398 /// createPass() - Use this method to create an instance of this pass.
11499 Pass *createPass() const {
115100 assert((!isAnalysisGroup() || NormalCtor) &&
3030
3131 namespace llvm {
3232
33 class TargetMachine;
34
3533 #define INITIALIZE_PASS(passName, arg, name, cfg, analysis) \
3634 static void *initialize##passName##PassOnce(PassRegistry &Registry) { \
3735 PassInfo *PI = new PassInfo( \
7674 PassName::registerOptions();
7775
7876 template Pass *callDefaultCtor() { return new PassName(); }
79
80 template Pass *callTargetMachineCtor(TargetMachine *TM) {
81 return new PassName(TM);
82 }
8377
8478 //===---------------------------------------------------------------------------
8579 /// RegisterPass template - This template class is used to notify the system
1616
1717 #include "llvm/CodeGen/AtomicExpandUtils.h"
1818 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/CodeGen/TargetPassConfig.h"
1920 #include "llvm/IR/Function.h"
2021 #include "llvm/IR/IRBuilder.h"
2122 #include "llvm/IR/InstIterator.h"
3435
3536 namespace {
3637 class AtomicExpand: public FunctionPass {
37 const TargetMachine *TM;
3838 const TargetLowering *TLI;
3939 public:
4040 static char ID; // Pass identification, replacement for typeid
41 explicit AtomicExpand(const TargetMachine *TM = nullptr)
42 : FunctionPass(ID), TM(TM), TLI(nullptr) {
41 AtomicExpand() : FunctionPass(ID), TLI(nullptr) {
4342 initializeAtomicExpandPass(*PassRegistry::getPassRegistry());
4443 }
4544
9695
9796 char AtomicExpand::ID = 0;
9897 char &llvm::AtomicExpandID = AtomicExpand::ID;
99 INITIALIZE_TM_PASS(AtomicExpand, "atomic-expand", "Expand Atomic instructions",
100 false, false)
101
102 FunctionPass *llvm::createAtomicExpandPass(const TargetMachine *TM) {
103 return new AtomicExpand(TM);
104 }
98 INITIALIZE_PASS(AtomicExpand, "atomic-expand", "Expand Atomic instructions",
99 false, false)
100
101 FunctionPass *llvm::createAtomicExpandPass() { return new AtomicExpand(); }
105102
106103 namespace {
107104 // Helper functions to retrieve the size of atomic instructions.
171168 } // end anonymous namespace
172169
173170 bool AtomicExpand::runOnFunction(Function &F) {
174 if (!TM || !TM->getSubtargetImpl(F)->enableAtomicExpand())
171 auto *TPC = getAnalysisIfAvailable();
172 if (!TPC)
175173 return false;
176 TLI = TM->getSubtargetImpl(F)->getTargetLowering();
174
175 auto &TM = TPC->getTM();
176 if (!TM.getSubtargetImpl(F)->enableAtomicExpand())
177 return false;
178 TLI = TM.getSubtargetImpl(F)->getTargetLowering();
177179
178180 SmallVector AtomicInsts;
179181
1313 //===----------------------------------------------------------------------===//
1414
1515 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/CodeGen/TargetPassConfig.h"
1617 #include "llvm/ADT/DenseMap.h"
1718 #include "llvm/ADT/SetVector.h"
1819 #include "llvm/ADT/SmallSet.h"
196197
197198 public:
198199 static char ID; // Pass identification, replacement for typeid
199 explicit CodeGenPrepare(const TargetMachine *TM = nullptr)
200 : FunctionPass(ID), TM(TM), TLI(nullptr), TTI(nullptr), DL(nullptr) {
201 initializeCodeGenPreparePass(*PassRegistry::getPassRegistry());
202 }
200 CodeGenPrepare()
201 : FunctionPass(ID), TM(nullptr), TLI(nullptr), TTI(nullptr),
202 DL(nullptr) {
203 initializeCodeGenPreparePass(*PassRegistry::getPassRegistry());
204 }
203205 bool runOnFunction(Function &F) override;
204206
205207 StringRef getPassName() const override { return "CodeGen Prepare"; }
254256 }
255257
256258 char CodeGenPrepare::ID = 0;
257 INITIALIZE_TM_PASS_BEGIN(CodeGenPrepare, "codegenprepare",
258 "Optimize for code generation", false, false)
259 INITIALIZE_PASS_BEGIN(CodeGenPrepare, "codegenprepare",
260 "Optimize for code generation", false, false)
259261 INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
260 INITIALIZE_TM_PASS_END(CodeGenPrepare, "codegenprepare",
261 "Optimize for code generation", false, false)
262
263 FunctionPass *llvm::createCodeGenPreparePass(const TargetMachine *TM) {
264 return new CodeGenPrepare(TM);
265 }
262 INITIALIZE_PASS_END(CodeGenPrepare, "codegenprepare",
263 "Optimize for code generation", false, false)
264
265 FunctionPass *llvm::createCodeGenPreparePass() { return new CodeGenPrepare(); }
266266
267267 bool CodeGenPrepare::runOnFunction(Function &F) {
268268 if (skipFunction(F))
278278 BPI.reset();
279279
280280 ModifiedDT = false;
281 if (TM) {
281 if (auto *TPC = getAnalysisIfAvailable()) {
282 TM = &TPC->getTM();
282283 SubtargetInfo = TM->getSubtargetImpl(F);
283284 TLI = SubtargetInfo->getTargetLowering();
284285 TRI = SubtargetInfo->getRegisterInfo();
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "llvm/CodeGen/Passes.h"
15 #include "llvm/CodeGen/TargetPassConfig.h"
1516 #include "llvm/ADT/BitVector.h"
1617 #include "llvm/ADT/Statistic.h"
1718 #include "llvm/Analysis/CFG.h"
3334
3435 namespace {
3536 class DwarfEHPrepare : public FunctionPass {
36 const TargetMachine *TM;
37
3837 // RewindFunction - _Unwind_Resume or the target equivalent.
3938 Constant *RewindFunction;
4039
5150 public:
5251 static char ID; // Pass identification, replacement for typeid.
5352
54 // INITIALIZE_TM_PASS requires a default constructor, but it isn't used in
55 // practice.
5653 DwarfEHPrepare()
57 : FunctionPass(ID), TM(nullptr), RewindFunction(nullptr), DT(nullptr),
58 TLI(nullptr) {}
59
60 DwarfEHPrepare(const TargetMachine *TM)
61 : FunctionPass(ID), TM(TM), RewindFunction(nullptr), DT(nullptr),
62 TLI(nullptr) {}
54 : FunctionPass(ID), RewindFunction(nullptr), DT(nullptr), TLI(nullptr) {
55 }
6356
6457 bool runOnFunction(Function &Fn) override;
6558
7770 } // end anonymous namespace
7871
7972 char DwarfEHPrepare::ID = 0;
80 INITIALIZE_TM_PASS_BEGIN(DwarfEHPrepare, "dwarfehprepare",
81 "Prepare DWARF exceptions", false, false)
73 INITIALIZE_PASS_BEGIN(DwarfEHPrepare, "dwarfehprepare",
74 "Prepare DWARF exceptions", false, false)
8275 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
76 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
8377 INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
84 INITIALIZE_TM_PASS_END(DwarfEHPrepare, "dwarfehprepare",
85 "Prepare DWARF exceptions", false, false)
86
87 FunctionPass *llvm::createDwarfEHPass(const TargetMachine *TM) {
88 return new DwarfEHPrepare(TM);
89 }
78 INITIALIZE_PASS_END(DwarfEHPrepare, "dwarfehprepare",
79 "Prepare DWARF exceptions", false, false)
80
81 FunctionPass *llvm::createDwarfEHPass() { return new DwarfEHPrepare(); }
9082
9183 void DwarfEHPrepare::getAnalysisUsage(AnalysisUsage &AU) const {
84 AU.addRequired();
9285 AU.addRequired();
9386 AU.addRequired();
9487 }
253246 }
254247
255248 bool DwarfEHPrepare::runOnFunction(Function &Fn) {
256 assert(TM && "DWARF EH preparation requires a target machine");
249 const TargetMachine &TM =
250 getAnalysis().getTM();
257251 DT = &getAnalysis().getDomTree();
258 TLI = TM->getSubtargetImpl(Fn)->getTargetLowering();
252 TLI = TM.getSubtargetImpl(Fn)->getTargetLowering();
259253 bool Changed = InsertUnwindResumeCalls(Fn);
260254 DT = nullptr;
261255 TLI = nullptr;
4444 //===----------------------------------------------------------------------===//
4545
4646 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/CodeGen/TargetPassConfig.h"
4748 #include "llvm/IR/Dominators.h"
4849 #include "llvm/IR/InstIterator.h"
4950 #include "llvm/Support/Debug.h"
6768
6869 public:
6970 static char ID;
70 InterleavedAccess(const TargetMachine *TM = nullptr)
71 : FunctionPass(ID), DT(nullptr), TM(TM), TLI(nullptr) {
71 InterleavedAccess() : FunctionPass(ID), DT(nullptr), TLI(nullptr) {
7272 initializeInterleavedAccessPass(*PassRegistry::getPassRegistry());
7373 }
7474
8383
8484 private:
8585 DominatorTree *DT;
86 const TargetMachine *TM;
8786 const TargetLowering *TLI;
8887
8988 /// The maximum supported interleave factor.
107106 } // end anonymous namespace.
108107
109108 char InterleavedAccess::ID = 0;
110 INITIALIZE_TM_PASS_BEGIN(
109 INITIALIZE_PASS_BEGIN(
111110 InterleavedAccess, "interleaved-access",
112111 "Lower interleaved memory accesses to target specific intrinsics", false,
113112 false)
114113 INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
115 INITIALIZE_TM_PASS_END(
114 INITIALIZE_PASS_END(
116115 InterleavedAccess, "interleaved-access",
117116 "Lower interleaved memory accesses to target specific intrinsics", false,
118117 false)
119118
120 FunctionPass *llvm::createInterleavedAccessPass(const TargetMachine *TM) {
121 return new InterleavedAccess(TM);
119 FunctionPass *llvm::createInterleavedAccessPass() {
120 return new InterleavedAccess();
122121 }
123122
124123 /// \brief Check if the mask is a DE-interleave mask of the given factor
425424 }
426425
427426 bool InterleavedAccess::runOnFunction(Function &F) {
428 if (!TM || !LowerInterleavedAccesses)
427 auto *TPC = getAnalysisIfAvailable();
428 if (!TPC || !LowerInterleavedAccesses)
429429 return false;
430430
431431 DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
432432
433433 DT = &getAnalysis().getDomTree();
434 TLI = TM->getSubtargetImpl(F)->getTargetLowering();
434 auto &TM = TPC->getTM();
435 TLI = TM.getSubtargetImpl(F)->getTargetLowering();
435436 MaxFactor = TLI->getMaxSupportedInterleaveFactor();
436437
437438 // Holds dead instructions that will be erased later.
108108 AnalysisID StopAfter,
109109 MachineFunctionInitializer *MFInitializer = nullptr) {
110110
111 // When in emulated TLS mode, add the LowerEmuTLS pass.
112 if (TM->Options.EmulatedTLS)
113 PM.add(createLowerEmuTLSPass(TM));
114
115 PM.add(createPreISelIntrinsicLoweringPass());
116
117 // Add internal analysis passes from the target machine.
118 PM.add(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
119
120111 // Targets may override createPassConfig to provide a target-specific
121112 // subclass.
122113 TargetPassConfig *PassConfig = TM->createPassConfig(PM);
123114 PassConfig->setStartStopPasses(StartBefore, StartAfter, StopBefore,
124115 StopAfter);
125
126116 // Set PassConfig options provided by TargetMachine.
127117 PassConfig->setDisableVerify(DisableVerify);
128
129118 PM.add(PassConfig);
119
120 // When in emulated TLS mode, add the LowerEmuTLS pass.
121 if (TM->Options.EmulatedTLS)
122 PM.add(createLowerEmuTLSPass());
123
124 PM.add(createPreISelIntrinsicLoweringPass());
125
126 // Add internal analysis passes from the target machine.
127 PM.add(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
130128
131129 PassConfig->addIRPasses();
132130
1515
1616 #include "llvm/ADT/SmallVector.h"
1717 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
1819 #include "llvm/IR/LLVMContext.h"
1920 #include "llvm/IR/Module.h"
2021 #include "llvm/Pass.h"
2728 namespace {
2829
2930 class LowerEmuTLS : public ModulePass {
30 const TargetMachine *TM;
3131 public:
3232 static char ID; // Pass identification, replacement for typeid
33 explicit LowerEmuTLS() : ModulePass(ID), TM(nullptr) { }
34 explicit LowerEmuTLS(const TargetMachine *TM)
35 : ModulePass(ID), TM(TM) {
33 LowerEmuTLS() : ModulePass(ID) {
3634 initializeLowerEmuTLSPass(*PassRegistry::getPassRegistry());
3735 }
36
3837 bool runOnModule(Module &M) override;
3938 private:
4039 bool addEmuTlsVar(Module &M, const GlobalVariable *GV);
5453 char LowerEmuTLS::ID = 0;
5554
5655 INITIALIZE_PASS(LowerEmuTLS, "loweremutls",
57 "Add __emutls_[vt]. variables for emultated TLS model",
58 false, false)
56 "Add __emutls_[vt]. variables for emultated TLS model", false,
57 false)
5958
60 ModulePass *llvm::createLowerEmuTLSPass(const TargetMachine *TM) {
61 return new LowerEmuTLS(TM);
62 }
59 ModulePass *llvm::createLowerEmuTLSPass() { return new LowerEmuTLS(); }
6360
6461 bool LowerEmuTLS::runOnModule(Module &M) {
6562 if (skipModule(M))
6663 return false;
6764
68 if (!TM || !TM->Options.EmulatedTLS)
65 auto *TPC = getAnalysisIfAvailable();
66 if (!TPC)
67 return false;
68
69 auto &TM = TPC->getTM();
70 if (!TM.Options.EmulatedTLS)
6971 return false;
7072
7173 bool Changed = false;
3131 using namespace llvm::dwarf;
3232
3333 // Handle the Pass registration stuff necessary to use DataLayout's.
34 INITIALIZE_TM_PASS(MachineModuleInfo, "machinemoduleinfo",
35 "Machine Module Information", false, false)
34 INITIALIZE_PASS(MachineModuleInfo, "machinemoduleinfo",
35 "Machine Module Information", false, false)
3636 char MachineModuleInfo::ID = 0;
3737
3838 // Out of line virtual method.
5959 class PEI : public MachineFunctionPass {
6060 public:
6161 static char ID;
62 explicit PEI(const TargetMachine *TM = nullptr) : MachineFunctionPass(ID) {
62 PEI() : MachineFunctionPass(ID) {
6363 initializePEIPass(*PassRegistry::getPassRegistry());
64
65 if (TM && (!TM->usesPhysRegsForPEI())) {
64 }
65
66 void getAnalysisUsage(AnalysisUsage &AU) const override;
67
68 MachineFunctionProperties getRequiredProperties() const override {
69 MachineFunctionProperties MFP;
70 if (UsesCalleeSaves)
71 MFP.set(MachineFunctionProperties::Property::NoVRegs);
72 return MFP;
73 }
74
75 /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
76 /// frame indexes with appropriate references.
77 ///
78 bool runOnMachineFunction(MachineFunction &Fn) override;
79
80 private:
81 std::function
82 unsigned &MinCSFrameIndex, unsigned &MaxCSFrameIndex,
83 const MBBVector &SaveBlocks,
84 const MBBVector &RestoreBlocks)>
85 SpillCalleeSavedRegisters;
86 std::function
87 ScavengeFrameVirtualRegs;
88
89 bool UsesCalleeSaves = false;
90
91 RegScavenger *RS;
92
93 // MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee saved
94 // stack frame indexes.
95 unsigned MinCSFrameIndex = std::numeric_limits::max();
96 unsigned MaxCSFrameIndex = 0;
97
98 // Save and Restore blocks of the current function. Typically there is a
99 // single save block, unless Windows EH funclets are involved.
100 MBBVector SaveBlocks;
101 MBBVector RestoreBlocks;
102
103 // Flag to control whether to use the register scavenger to resolve
104 // frame index materialization registers. Set according to
105 // TRI->requiresFrameIndexScavenging() for the current function.
106 bool FrameIndexVirtualScavenging;
107
108 // Flag to control whether the scavenger should be passed even though
109 // FrameIndexVirtualScavenging is used.
110 bool FrameIndexEliminationScavenging;
111
112 void calculateCallFrameInfo(MachineFunction &Fn);
113 void calculateSaveRestoreBlocks(MachineFunction &Fn);
114
115 void calculateFrameObjectOffsets(MachineFunction &Fn);
116 void replaceFrameIndices(MachineFunction &Fn);
117 void replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
118 int &SPAdj);
119 void insertPrologEpilogCode(MachineFunction &Fn);
120 };
121 } // namespace
122
123 char PEI::ID = 0;
124 char &llvm::PrologEpilogCodeInserterID = PEI::ID;
125
126 static cl::opt
127 WarnStackSize("warn-stack-size", cl::Hidden, cl::init((unsigned)-1),
128 cl::desc("Warn for stack size bigger than the given"
129 " number"));
130
131 INITIALIZE_PASS_BEGIN(PEI, "prologepilog", "Prologue/Epilogue Insertion", false,
132 false)
133 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
134 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
135 INITIALIZE_PASS_DEPENDENCY(StackProtector)
136 INITIALIZE_PASS_END(PEI, "prologepilog",
137 "Prologue/Epilogue Insertion & Frame Finalization", false,
138 false)
139
140 MachineFunctionPass *llvm::createPrologEpilogInserterPass() {
141 return new PEI();
142 }
143
144 STATISTIC(NumScavengedRegs, "Number of frame index regs scavenged");
145 STATISTIC(NumBytesStackSpace,
146 "Number of bytes used for stack in all functions");
147
148 void PEI::getAnalysisUsage(AnalysisUsage &AU) const {
149 AU.setPreservesCFG();
150 AU.addPreserved();
151 AU.addPreserved();
152 AU.addRequired();
153 MachineFunctionPass::getAnalysisUsage(AU);
154 }
155
156
157 /// StackObjSet - A set of stack object indexes
158 typedef SmallSetVector StackObjSet;
159
160 /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
161 /// frame indexes with appropriate references.
162 ///
163 bool PEI::runOnMachineFunction(MachineFunction &Fn) {
164 if (!SpillCalleeSavedRegisters) {
165 const TargetMachine &TM = Fn.getTarget();
166 if (!TM.usesPhysRegsForPEI()) {
66167 SpillCalleeSavedRegisters = [](MachineFunction &, RegScavenger *,
67168 unsigned &, unsigned &, const MBBVector &,
68169 const MBBVector &) {};
74175 }
75176 }
76177
77 void getAnalysisUsage(AnalysisUsage &AU) const override;
78
79 MachineFunctionProperties getRequiredProperties() const override {
80 MachineFunctionProperties MFP;
81 if (UsesCalleeSaves)
82 MFP.set(MachineFunctionProperties::Property::NoVRegs);
83 return MFP;
84 }
85
86 /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
87 /// frame indexes with appropriate references.
88 ///
89 bool runOnMachineFunction(MachineFunction &Fn) override;
90
91 private:
92 std::function
93 unsigned &MinCSFrameIndex, unsigned &MaxCSFrameIndex,
94 const MBBVector &SaveBlocks,
95 const MBBVector &RestoreBlocks)>
96 SpillCalleeSavedRegisters;
97 std::function
98 ScavengeFrameVirtualRegs;
99
100 bool UsesCalleeSaves = false;
101
102 RegScavenger *RS;
103
104 // MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee saved
105 // stack frame indexes.
106 unsigned MinCSFrameIndex = std::numeric_limits::max();
107 unsigned MaxCSFrameIndex = 0;
108
109 // Save and Restore blocks of the current function. Typically there is a
110 // single save block, unless Windows EH funclets are involved.
111 MBBVector SaveBlocks;
112 MBBVector RestoreBlocks;
113
114 // Flag to control whether to use the register scavenger to resolve
115 // frame index materialization registers. Set according to
116 // TRI->requiresFrameIndexScavenging() for the current function.
117 bool FrameIndexVirtualScavenging;
118
119 // Flag to control whether the scavenger should be passed even though
120 // FrameIndexVirtualScavenging is used.
121 bool FrameIndexEliminationScavenging;
122
123 void calculateCallFrameInfo(MachineFunction &Fn);
124 void calculateSaveRestoreBlocks(MachineFunction &Fn);
125
126 void calculateFrameObjectOffsets(MachineFunction &Fn);
127 void replaceFrameIndices(MachineFunction &Fn);
128 void replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &Fn,
129 int &SPAdj);
130 void insertPrologEpilogCode(MachineFunction &Fn);
131 };
132 } // namespace
133
134 char PEI::ID = 0;
135 char &llvm::PrologEpilogCodeInserterID = PEI::ID;
136
137 static cl::opt
138 WarnStackSize("warn-stack-size", cl::Hidden, cl::init((unsigned)-1),
139 cl::desc("Warn for stack size bigger than the given"
140 " number"));
141
142 INITIALIZE_TM_PASS_BEGIN(PEI, "prologepilog", "Prologue/Epilogue Insertion",
143 false, false)
144 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
145 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
146 INITIALIZE_PASS_DEPENDENCY(StackProtector)
147 INITIALIZE_TM_PASS_END(PEI, "prologepilog",
148 "Prologue/Epilogue Insertion & Frame Finalization",
149 false, false)
150
151 MachineFunctionPass *
152 llvm::createPrologEpilogInserterPass(const TargetMachine *TM) {
153 return new PEI(TM);
154 }
155
156 STATISTIC(NumScavengedRegs, "Number of frame index regs scavenged");
157 STATISTIC(NumBytesStackSpace,
158 "Number of bytes used for stack in all functions");
159
160 void PEI::getAnalysisUsage(AnalysisUsage &AU) const {
161 AU.setPreservesCFG();
162 AU.addPreserved();
163 AU.addPreserved();
164 AU.addRequired();
165 MachineFunctionPass::getAnalysisUsage(AU);
166 }
167
168
169 /// StackObjSet - A set of stack object indexes
170 typedef SmallSetVector StackObjSet;
171
172 /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
173 /// frame indexes with appropriate references.
174 ///
175 bool PEI::runOnMachineFunction(MachineFunction &Fn) {
176178 const Function* F = Fn.getFunction();
177179 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
178180 const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
2323 #include "llvm/Analysis/ScalarEvolution.h"
2424 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
2525 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
2627 #include "llvm/IR/Constants.h"
2728 #include "llvm/IR/DIBuilder.h"
2829 #include "llvm/IR/DataLayout.h"
766767
767768 public:
768769 static char ID; // Pass identification, replacement for typeid..
769 SafeStackLegacyPass(const TargetMachine *TM) : FunctionPass(ID), TM(TM) {
770 SafeStackLegacyPass() : FunctionPass(ID), TM(nullptr) {
770771 initializeSafeStackLegacyPassPass(*PassRegistry::getPassRegistry());
771772 }
772773
773 SafeStackLegacyPass() : SafeStackLegacyPass(nullptr) {}
774
775774 void getAnalysisUsage(AnalysisUsage &AU) const override {
775 AU.addRequired();
776776 AU.addRequired();
777777 AU.addRequired();
778778 }
792792 return false;
793793 }
794794
795 if (!TM)
796 report_fatal_error("Target machine is required");
795 TM = &getAnalysis().getTM();
797796 auto *TL = TM->getSubtargetImpl(F)->getTargetLowering();
798797 if (!TL)
799798 report_fatal_error("TargetLowering instance is required");
820819 } // anonymous namespace
821820
822821 char SafeStackLegacyPass::ID = 0;
823 INITIALIZE_TM_PASS_BEGIN(SafeStackLegacyPass, "safe-stack",
824 "Safe Stack instrumentation pass", false, false)
825 INITIALIZE_TM_PASS_END(SafeStackLegacyPass, "safe-stack",
826 "Safe Stack instrumentation pass", false, false)
827
828 FunctionPass *llvm::createSafeStackPass(const llvm::TargetMachine *TM) {
829 return new SafeStackLegacyPass(TM);
830 }
822 INITIALIZE_PASS_BEGIN(SafeStackLegacyPass, "safe-stack",
823 "Safe Stack instrumentation pass", false, false)
824 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
825 INITIALIZE_PASS_END(SafeStackLegacyPass, "safe-stack",
826 "Safe Stack instrumentation pass", false, false)
827
828 FunctionPass *llvm::createSafeStackPass() { return new SafeStackLegacyPass(); }
5757 cl::init(true), cl::Hidden);
5858
5959 char StackProtector::ID = 0;
60 INITIALIZE_TM_PASS(StackProtector, "stack-protector", "Insert stack protectors",
61 false, true)
62
63 FunctionPass *llvm::createStackProtectorPass(const TargetMachine *TM) {
64 return new StackProtector(TM);
65 }
60 INITIALIZE_PASS_BEGIN(StackProtector, "stack-protector",
61 "Insert stack protectors", false, true)
62 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
63 INITIALIZE_PASS_END(StackProtector, "stack-protector",
64 "Insert stack protectors", false, true)
65
66 FunctionPass *llvm::createStackProtectorPass() { return new StackProtector(); }
6667
6768 StackProtector::SSPLayoutKind
6869 StackProtector::getSSPLayout(const AllocaInst *AI) const {
9697 DominatorTreeWrapperPass *DTWP =
9798 getAnalysisIfAvailable();
9899 DT = DTWP ? &DTWP->getDomTree() : nullptr;
100 TM = &getAnalysis().getTM();
101 Trip = TM->getTargetTriple();
99102 TLI = TM->getSubtargetImpl(Fn)->getTargetLowering();
100103 HasPrologue = false;
101104 HasIRCheck = false;
314314
315315 TargetPassConfig::TargetPassConfig()
316316 : ImmutablePass(ID), PM(nullptr) {
317 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
317 report_fatal_error("Trying to construct TargetPassConfig without a target "
318 "machine. Scheduling a CodeGen pass without a target "
319 "triple set?");
318320 }
319321
320322 // Helper to verify the analysis is really immutable.
513515 LLVM_FALLTHROUGH;
514516 case ExceptionHandling::DwarfCFI:
515517 case ExceptionHandling::ARM:
516 addPass(createDwarfEHPass(TM));
518 addPass(createDwarfEHPass());
517519 break;
518520 case ExceptionHandling::WinEH:
519521 // We support using both GCC-style and MSVC-style exceptions on Windows, so
520522 // add both preparation passes. Each pass will only actually run if it
521523 // recognizes the personality function.
522 addPass(createWinEHPass(TM));
523 addPass(createDwarfEHPass(TM));
524 addPass(createWinEHPass());
525 addPass(createDwarfEHPass());
524526 break;
525527 case ExceptionHandling::None:
526528 addPass(createLowerInvokePass());
535537 /// before exception handling preparation passes.
536538 void TargetPassConfig::addCodeGenPrepare() {
537539 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
538 addPass(createCodeGenPreparePass(TM));
540 addPass(createCodeGenPreparePass());
539541 addPass(createRewriteSymbolsPass());
540542 }
541543
550552
551553 // Add both the safe stack and the stack protection passes: each of them will
552554 // only protect functions that have corresponding attributes.
553 addPass(createSafeStackPass(TM));
554 addPass(createStackProtectorPass(TM));
555 addPass(createSafeStackPass());
556 addPass(createStackProtectorPass());
555557
556558 if (PrintISelInput)
557559 addPass(createPrintFunctionPass(
646648 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
647649 // do so if it hasn't been disabled, substituted, or overridden.
648650 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
649 addPass(createPrologEpilogInserterPass(TM));
651 addPass(createPrologEpilogInserterPass());
650652
651653 /// Add passes that optimize machine instructions after register allocation.
652654 if (getOptLevel() != CodeGenOpt::None)
5353 class WinEHPrepare : public FunctionPass {
5454 public:
5555 static char ID; // Pass identification, replacement for typeid.
56 WinEHPrepare(const TargetMachine *TM = nullptr) : FunctionPass(ID) {}
56 WinEHPrepare() : FunctionPass(ID) {}
5757
5858 bool runOnFunction(Function &Fn) override;
5959
9393 } // end anonymous namespace
9494
9595 char WinEHPrepare::ID = 0;
96 INITIALIZE_TM_PASS(WinEHPrepare, "winehprepare", "Prepare Windows exceptions",
97 false, false)
98
99 FunctionPass *llvm::createWinEHPass(const TargetMachine *TM) {
100 return new WinEHPrepare(TM);
101 }
96 INITIALIZE_PASS(WinEHPrepare, "winehprepare", "Prepare Windows exceptions",
97 false, false)
98
99 FunctionPass *llvm::createWinEHPass() { return new WinEHPrepare(); }
102100
103101 bool WinEHPrepare::runOnFunction(Function &Fn) {
104102 if (!Fn.hasPersonalityFn())
104104 ImplementationInfo->getNormalCtor() &&
105105 "Cannot specify pass as default if it does not have a default ctor");
106106 InterfaceInfo->setNormalCtor(ImplementationInfo->getNormalCtor());
107 InterfaceInfo->setTargetMachineCtor(
108 ImplementationInfo->getTargetMachineCtor());
109107 }
110108 }
111109
323323 void AArch64PassConfig::addIRPasses() {
324324 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
325325 // ourselves.
326 addPass(createAtomicExpandPass(TM));
326 addPass(createAtomicExpandPass());
327327
328328 // Cmpxchg instructions are often used with a subsequent comparison to
329329 // determine whether it succeeded. We can exploit existing control-flow in
342342
343343 // Match interleaved memory accesses to ldN/stN intrinsics.
344344 if (TM->getOptLevel() != CodeGenOpt::None)
345 addPass(createInterleavedAccessPass(TM));
345 addPass(createInterleavedAccessPass());
346346
347347 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
348348 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
2626 class Module;
2727
2828 // R600 Passes
29 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
30 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
29 FunctionPass *createR600VectorRegMerger();
30 FunctionPass *createR600ExpandSpecialInstrsPass();
3131 FunctionPass *createR600EmitClauseMarkers();
32 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
33 FunctionPass *createR600Packetizer(TargetMachine &tm);
34 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
32 FunctionPass *createR600ClauseMergePass();
33 FunctionPass *createR600Packetizer();
34 FunctionPass *createR600ControlFlowFinalizer();
3535 FunctionPass *createAMDGPUCFGStructurizerPass();
3636
3737 // SI Passes
4141 FunctionPass *createSIPeepholeSDWAPass();
4242 FunctionPass *createSILowerI1CopiesPass();
4343 FunctionPass *createSIShrinkInstructionsPass();
44 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
44 FunctionPass *createSILoadStoreOptimizerPass();
4545 FunctionPass *createSIWholeQuadModePass();
4646 FunctionPass *createSIFixControlFlowLiveIntervalsPass();
4747 FunctionPass *createSIFixSGPRCopiesPass();
4848 FunctionPass *createSIDebuggerInsertNopsPass();
4949 FunctionPass *createSIInsertWaitsPass();
5050 FunctionPass *createSIInsertWaitcntsPass();
51 FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
51 FunctionPass *createAMDGPUCodeGenPreparePass();
5252 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
5353
5454 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
5555 extern char &AMDGPUMachineCFGStructurizerID;
5656
57 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM = nullptr);
57 ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
5858 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
5959 extern char &AMDGPUAnnotateKernelFeaturesID;
6060
61 ModulePass *createAMDGPULowerIntrinsicsPass(const TargetMachine *TM = nullptr);
61 ModulePass *createAMDGPULowerIntrinsicsPass();
6262 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
6363 extern char &AMDGPULowerIntrinsicsID;
6464
9696 extern char &SIOptimizeExecMaskingID;
9797
9898 // Passes common to R600 and SI
99 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
99 FunctionPass *createAMDGPUPromoteAlloca();
100100 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
101101 extern char &AMDGPUPromoteAllocaID;
102102
1414 #include "AMDGPU.h"
1515 #include "AMDGPUSubtarget.h"
1616 #include "llvm/ADT/Triple.h"
17 #include "llvm/CodeGen/TargetPassConfig.h"
1718 #include "llvm/IR/Constants.h"
1819 #include "llvm/IR/Instructions.h"
1920 #include "llvm/IR/Module.h"
2627
2728 class AMDGPUAnnotateKernelFeatures : public ModulePass {
2829 private:
29 const TargetMachine *TM;
3030 AMDGPUAS AS;
3131 static bool hasAddrSpaceCast(const Function &F, AMDGPUAS AS);
3232
3636 public:
3737 static char ID;
3838
39 AMDGPUAnnotateKernelFeatures(const TargetMachine *TM_ = nullptr) :
40 ModulePass(ID), TM(TM_) {}
39 AMDGPUAnnotateKernelFeatures() : ModulePass(ID) {}
4140 bool runOnModule(Module &M) override;
4241 StringRef getPassName() const override {
4342 return "AMDGPU Annotate Kernel Features";
220219 if (F.hasFnAttribute("amdgpu-queue-ptr"))
221220 continue;
222221
223 bool HasApertureRegs =
224 TM && TM->getSubtarget(F).hasApertureRegs();
222 auto *TPC = getAnalysisIfAvailable();
223 bool HasApertureRegs = TPC && TPC->getTM()
224 .getSubtarget(F)
225 .hasApertureRegs();
225226 if (!HasApertureRegs && hasAddrSpaceCast(F, AS))
226227 F.addFnAttr("amdgpu-queue-ptr");
227228 }
230231 return Changed;
231232 }
232233
233 ModulePass *llvm::createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM) {
234 return new AMDGPUAnnotateKernelFeatures(TM);
235 }
234 ModulePass *llvm::createAMDGPUAnnotateKernelFeaturesPass() {
235 return new AMDGPUAnnotateKernelFeatures();
236 }
1818 #include "llvm/ADT/StringRef.h"
1919 #include "llvm/Analysis/DivergenceAnalysis.h"
2020 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/TargetPassConfig.h"
2122 #include "llvm/IR/Attributes.h"
2223 #include "llvm/IR/BasicBlock.h"
2324 #include "llvm/IR/Constants.h"
4748
4849 class AMDGPUCodeGenPrepare : public FunctionPass,
4950 public InstVisitor {
50 const GCNTargetMachine *TM;
5151 const SISubtarget *ST = nullptr;
5252 DivergenceAnalysis *DA = nullptr;
5353 Module *Mod = nullptr;
126126 public:
127127 static char ID;
128128
129 AMDGPUCodeGenPrepare(const TargetMachine *TM = nullptr) :
130 FunctionPass(ID), TM(static_cast(TM)) {}
129 AMDGPUCodeGenPrepare() : FunctionPass(ID) {}
131130
132131 bool visitFDiv(BinaryOperator &I);
133132
486485 }
487486
488487 bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
489 if (!TM || skipFunction(F))
490 return false;
491
492 ST = &TM->getSubtarget(F);
488 if (skipFunction(F))
489 return false;
490
491 auto *TPC = getAnalysisIfAvailable();
492 if (!TPC)
493 return false;
494
495 const TargetMachine &TM = TPC->getTM();
496 ST = &TM.getSubtarget(F);
493497 DA = &getAnalysis();
494498 HasUnsafeFPMath = hasUnsafeFPMath(F);
495499
506510 return MadeChange;
507511 }
508512
509 INITIALIZE_TM_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE,
513 INITIALIZE_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE,
510514 "AMDGPU IR optimizations", false, false)
511515 INITIALIZE_PASS_DEPENDENCY(DivergenceAnalysis)
512 INITIALIZE_TM_PASS_END(AMDGPUCodeGenPrepare, DEBUG_TYPE,
513 "AMDGPU IR optimizations", false, false)
516 INITIALIZE_PASS_END(AMDGPUCodeGenPrepare, DEBUG_TYPE, "AMDGPU IR optimizations",
517 false, false)
514518
515519 char AMDGPUCodeGenPrepare::ID = 0;
516520
517 FunctionPass *llvm::createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM) {
518 return new AMDGPUCodeGenPrepare(TM);
519 }
521 FunctionPass *llvm::createAMDGPUCodeGenPreparePass() {
522 return new AMDGPUCodeGenPrepare();
523 }
88
99 #include "AMDGPU.h"
1010 #include "AMDGPUSubtarget.h"
11 #include "llvm/CodeGen/TargetPassConfig.h"
1112 #include "llvm/IR/Constants.h"
1213 #include "llvm/IR/Instructions.h"
1314 #include "llvm/IR/IntrinsicInst.h"
2425
2526 class AMDGPULowerIntrinsics : public ModulePass {
2627 private:
27 const TargetMachine *TM;
28
2928 bool makeLIDRangeMetadata(Function &F) const;
3029
3130 public:
3231 static char ID;
3332
34 AMDGPULowerIntrinsics(const TargetMachine *TM = nullptr)
35 : ModulePass(ID), TM(TM) { }
33 AMDGPULowerIntrinsics() : ModulePass(ID) {}
34
3635 bool runOnModule(Module &M) override;
3736 StringRef getPassName() const override {
3837 return "AMDGPU Lower Intrinsics";
4544
4645 char &llvm::AMDGPULowerIntrinsicsID = AMDGPULowerIntrinsics::ID;
4746
48 INITIALIZE_TM_PASS(AMDGPULowerIntrinsics, DEBUG_TYPE,
49 "Lower intrinsics", false, false)
47 INITIALIZE_PASS(AMDGPULowerIntrinsics, DEBUG_TYPE, "Lower intrinsics", false,
48 false)
5049
5150 // TODO: Should refine based on estimated number of accesses (e.g. does it
5251 // require splitting based on alignment)
103102 }
104103
105104 bool AMDGPULowerIntrinsics::makeLIDRangeMetadata(Function &F) const {
106 if (!TM)
105 auto *TPC = getAnalysisIfAvailable();
106 if (!TPC)
107107 return false;
108108
109 const TargetMachine &TM = TPC->getTM();
110 const AMDGPUSubtarget &ST = TM.getSubtarget(F);
109111 bool Changed = false;
110 const AMDGPUSubtarget &ST = TM->getSubtarget(F);
111112
112113 for (auto *U : F.users()) {
113114 auto *CI = dyn_cast(U);
154155 return Changed;
155156 }
156157
157 ModulePass *llvm::createAMDGPULowerIntrinsicsPass(const TargetMachine *TM) {
158 return new AMDGPULowerIntrinsics(TM);
158 ModulePass *llvm::createAMDGPULowerIntrinsicsPass() {
159 return new AMDGPULowerIntrinsics();
159160 }
2222 #include "llvm/ADT/Twine.h"
2323 #include "llvm/Analysis/CaptureTracking.h"
2424 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/TargetPassConfig.h"
2526 #include "llvm/IR/Attributes.h"
2627 #include "llvm/IR/BasicBlock.h"
2728 #include "llvm/IR/Constant.h"
9899 public:
99100 static char ID;
100101
101 AMDGPUPromoteAlloca(const TargetMachine *TM_ = nullptr) :
102 FunctionPass(ID), TM(TM_) {}
102 AMDGPUPromoteAlloca() : FunctionPass(ID) {}
103103
104104 bool doInitialization(Module &M) override;
105105 bool runOnFunction(Function &F) override;
118118
119119 char AMDGPUPromoteAlloca::ID = 0;
120120
121 INITIALIZE_TM_PASS(AMDGPUPromoteAlloca, DEBUG_TYPE,
122 "AMDGPU promote alloca to vector or LDS", false, false)
121 INITIALIZE_PASS(AMDGPUPromoteAlloca, DEBUG_TYPE,
122 "AMDGPU promote alloca to vector or LDS", false, false)
123123
124124 char &llvm::AMDGPUPromoteAllocaID = AMDGPUPromoteAlloca::ID;
125125
126126 bool AMDGPUPromoteAlloca::doInitialization(Module &M) {
127 if (!TM)
128 return false;
129
130127 Mod = &M;
131128 DL = &Mod->getDataLayout();
132129
130 return false;
131 }
132
133 bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
134 if (skipFunction(F))
135 return false;
136
137 if (auto *TPC = getAnalysisIfAvailable())
138 TM = &TPC->getTM();
139 else
140 return false;
141
133142 const Triple &TT = TM->getTargetTriple();
134
135143 IsAMDGCN = TT.getArch() == Triple::amdgcn;
136144 IsAMDHSA = TT.getOS() == Triple::AMDHSA;
137
138 return false;
139 }
140
141 bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
142 if (!TM || skipFunction(F))
143 return false;
144145
145146 const AMDGPUSubtarget &ST = TM->getSubtarget(F);
146147 if (!ST.isPromoteAllocaEnabled())
873874 }
874875 }
875876
876 FunctionPass *llvm::createAMDGPUPromoteAlloca(const TargetMachine *TM) {
877 return new AMDGPUPromoteAlloca(TM);
878 }
877 FunctionPass *llvm::createAMDGPUPromoteAlloca() {
878 return new AMDGPUPromoteAlloca();
879 }
569569 disablePass(&FuncletLayoutID);
570570 disablePass(&PatchableFunctionID);
571571
572 addPass(createAMDGPULowerIntrinsicsPass(&TM));
572 addPass(createAMDGPULowerIntrinsicsPass());
573573
574574 // Function calls are not supported, so make sure we inline everything.
575575 addPass(createAMDGPUAlwaysInlinePass());
584584 if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
585585 // TODO: May want to move later or split into an early and late one.
586586
587 addPass(createAMDGPUCodeGenPreparePass(
588 static_cast(&TM)));
587 addPass(createAMDGPUCodeGenPreparePass());
589588 }
590589
591590 // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
593592
594593 if (TM.getOptLevel() > CodeGenOpt::None) {
595594 addPass(createInferAddressSpacesPass());
596 addPass(createAMDGPUPromoteAlloca(&TM));
595 addPass(createAMDGPUPromoteAlloca());
597596
598597 if (EnableSROA)
599598 addPass(createSROAPass());
663662 }
664663
665664 void R600PassConfig::addPreRegAlloc() {
666 addPass(createR600VectorRegMerger(*TM));
665 addPass(createR600VectorRegMerger());
667666 }
668667
669668 void R600PassConfig::addPreSched2() {
670669 addPass(createR600EmitClauseMarkers(), false);
671670 if (EnableR600IfConvert)
672671 addPass(&IfConverterID, false);
673 addPass(createR600ClauseMergePass(*TM), false);
672 addPass(createR600ClauseMergePass(), false);
674673 }
675674
676675 void R600PassConfig::addPreEmitPass() {
677676 addPass(createAMDGPUCFGStructurizerPass(), false);
678 addPass(createR600ExpandSpecialInstrsPass(*TM), false);
677 addPass(createR600ExpandSpecialInstrsPass(), false);
679678 addPass(&FinalizeMachineBundlesID, false);
680 addPass(createR600Packetizer(*TM), false);
681 addPass(createR600ControlFlowFinalizer(*TM), false);
679 addPass(createR600Packetizer(), false);
680 addPass(createR600ControlFlowFinalizer(), false);
682681 }
683682
684683 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
702701
703702 // FIXME: We need to run a pass to propagate the attributes when calls are
704703 // supported.
705 const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
706 addPass(createAMDGPUAnnotateKernelFeaturesPass(&TM));
704 addPass(createAMDGPUAnnotateKernelFeaturesPass());
707705
708706 // Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
709707 // regions formed by them.
6161 const MachineInstr &LatrCFAlu) const;
6262
6363 public:
64 R600ClauseMergePass(TargetMachine &tm) : MachineFunctionPass(ID) { }
64 R600ClauseMergePass() : MachineFunctionPass(ID) { }
6565
6666 bool runOnMachineFunction(MachineFunction &MF) override;
6767
207207 } // end anonymous namespace
208208
209209
210 llvm::FunctionPass *llvm::createR600ClauseMergePass(TargetMachine &TM) {
211 return new R600ClauseMergePass(TM);
212 }
210 llvm::FunctionPass *llvm::createR600ClauseMergePass() {
211 return new R600ClauseMergePass();
212 }
498498 }
499499
500500 public:
501 R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID) {}
501 R600ControlFlowFinalizer() : MachineFunctionPass(ID) {}
502502
503503 bool runOnMachineFunction(MachineFunction &MF) override {
504504 ST = &MF.getSubtarget();
705705
706706 } // end anonymous namespace
707707
708 FunctionPass *llvm::createR600ControlFlowFinalizer(TargetMachine &TM) {
709 return new R600ControlFlowFinalizer(TM);
710 }
708 FunctionPass *llvm::createR600ControlFlowFinalizer() {
709 return new R600ControlFlowFinalizer();
710 }
3636 unsigned Op);
3737
3838 public:
39 R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
39 R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID),
4040 TII(nullptr) { }
4141
4242 bool runOnMachineFunction(MachineFunction &MF) override;
5050
5151 char R600ExpandSpecialInstrsPass::ID = 0;
5252
53 FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
54 return new R600ExpandSpecialInstrsPass(TM);
53 FunctionPass *llvm::createR600ExpandSpecialInstrsPass() {
54 return new R600ExpandSpecialInstrsPass();
5555 }
5656
5757 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
123123 public:
124124 static char ID;
125125
126 R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
126 R600VectorRegMerger() : MachineFunctionPass(ID),
127127 TII(nullptr) { }
128128
129129 void getAnalysisUsage(AnalysisUsage &AU) const override {
395395 return false;
396396 }
397397
398 llvm::FunctionPass *llvm::createR600VectorRegMerger(TargetMachine &tm) {
399 return new R600VectorRegMerger(tm);
400 }
398 llvm::FunctionPass *llvm::createR600VectorRegMerger() {
399 return new R600VectorRegMerger();
400 }
3535
3636 public:
3737 static char ID;
38 R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
38 R600Packetizer() : MachineFunctionPass(ID) {}
3939
4040 void getAnalysisUsage(AnalysisUsage &AU) const override {
4141 AU.setPreservesCFG();
403403
404404 } // end anonymous namespace
405405
406 llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
407 return new R600Packetizer(tm);
406 llvm::FunctionPass *llvm::createR600Packetizer() {
407 return new R600Packetizer();
408408 }
9696 public:
9797 static char ID;
9898
99 SILoadStoreOptimizer() : MachineFunctionPass(ID) {}
100
101 SILoadStoreOptimizer(const TargetMachine &TM_) : MachineFunctionPass(ID) {
99 SILoadStoreOptimizer() : MachineFunctionPass(ID) {
102100 initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
103101 }
104102
128126
129127 char &llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID;
130128
131 FunctionPass *llvm::createSILoadStoreOptimizerPass(TargetMachine &TM) {
132 return new SILoadStoreOptimizer(TM);
129 FunctionPass *llvm::createSILoadStoreOptimizerPass() {
130 return new SILoadStoreOptimizer();
133131 }
134132
135133 static void moveInstsAfter(MachineBasicBlock::iterator I,
470470 if (TM->Options.ThreadModel == ThreadModel::Single)
471471 addPass(createLowerAtomicPass());
472472 else
473 addPass(createAtomicExpandPass(TM));
473 addPass(createAtomicExpandPass());
474474
475475 // Cmpxchg instructions are often used with a subsequent comparison to
476476 // determine whether it succeeded. We can exploit existing control-flow in
485485
486486 // Match interleaved memory accesses to ldN/stN intrinsics.
487487 if (TM->getOptLevel() != CodeGenOpt::None)
488 addPass(createInterleavedAccessPass(TM));
488 addPass(createInterleavedAccessPass());
489489 }
490490
491491 bool ARMPassConfig::addPreISel() {
251251 TargetPassConfig::addIRPasses();
252252 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
253253
254 addPass(createAtomicExpandPass(TM));
254 addPass(createAtomicExpandPass());
255255 if (!NoOpt) {
256256 if (EnableLoopPrefetch)
257257 addPass(createLoopDataPrefetchPass());
2222 class ModulePass;
2323 class FunctionPass;
2424
25 ModulePass *createMipsOs16Pass(MipsTargetMachine &TM);
26 ModulePass *createMips16HardFloatPass(MipsTargetMachine &TM);
25 ModulePass *createMipsOs16Pass();
26 ModulePass *createMips16HardFloatPass();
2727
28 FunctionPass *createMipsModuleISelDagPass(MipsTargetMachine &TM);
29 FunctionPass *createMipsOptimizePICCallPass(MipsTargetMachine &TM);
30 FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
28 FunctionPass *createMipsModuleISelDagPass();
29 FunctionPass *createMipsOptimizePICCallPass();
30 FunctionPass *createMipsDelaySlotFillerPass();
3131 FunctionPass *createMipsHazardSchedule();
32 FunctionPass *createMipsLongBranchPass(MipsTargetMachine &TM);
32 FunctionPass *createMipsLongBranchPass();
3333 FunctionPass *createMipsConstantIslandPass();
3434 FunctionPass *createMicroMipsSizeReductionPass();
3535 } // end namespace llvm;
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "MipsTargetMachine.h"
14 #include "llvm/CodeGen/TargetPassConfig.h"
1415 #include "llvm/IR/Module.h"
1516 #include "llvm/IR/Value.h"
1617 #include "llvm/Support/Debug.h"
2728 public:
2829 static char ID;
2930
30 Mips16HardFloat(MipsTargetMachine &TM_) : ModulePass(ID), TM(TM_) {}
31 Mips16HardFloat() : ModulePass(ID) {}
3132
3233 StringRef getPassName() const override { return "MIPS16 Hard Float Pass"; }
3334
35 void getAnalysisUsage(AnalysisUsage &AU) const override {
36 AU.addRequired();
37 ModulePass::getAnalysisUsage(AU);
38 }
39
3440 bool runOnModule(Module &M) override;
35
36 protected:
37 const MipsTargetMachine &TM;
3841 };
3942
4043 static void EmitInlineAsm(LLVMContext &C, BasicBlock *BB, StringRef AsmText) {
519522 // during call lowering but it should be moved here in the future.
520523 //
521524 bool Mips16HardFloat::runOnModule(Module &M) {
525 auto &TM = static_cast(
526 getAnalysis().getTM());
522527 DEBUG(errs() << "Run on Module Mips16HardFloat\n");
523528 bool Modified = false;
524529 for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
540545 }
541546
542547
543 ModulePass *llvm::createMips16HardFloatPass(MipsTargetMachine &TM) {
544 return new Mips16HardFloat(TM);
545 }
548 ModulePass *llvm::createMips16HardFloatPass() {
549 return new Mips16HardFloat();
550 }
210210
211211 class Filler : public MachineFunctionPass {
212212 public:
213 Filler(TargetMachine &tm)
214 : MachineFunctionPass(ID), TM(tm) { }
213 Filler() : MachineFunctionPass(ID), TM(nullptr) {}
215214
216215 StringRef getPassName() const override { return "Mips Delay Slot Filler"; }
217216
218217 bool runOnMachineFunction(MachineFunction &F) override {
218 TM = &F.getTarget();
219219 bool Changed = false;
220220 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
221221 FI != FE; ++FI)
289289
290290 bool terminateSearch(const MachineInstr &Candidate) const;
291291
292 TargetMachine &TM;
292 const TargetMachine *TM;
293293
294294 static char ID;
295295 };
609609 Changed = true;
610610
611611 // Delay slot filling is disabled at -O0.
612 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
612 if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None)) {
613613 bool Filled = false;
614614
615615 if (MipsCompactBranchPolicy.getValue() != CB_Always ||
909909
910910 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
911911 /// slots in Mips MachineFunctions
912 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
913 return new Filler(tm);
914 }
912 FunctionPass *llvm::createMipsDelaySlotFillerPass() { return new Filler(); }
7474 public:
7575 static char ID;
7676
77 MipsLongBranch(TargetMachine &tm)
78 : MachineFunctionPass(ID), TM(tm), IsPIC(TM.isPositionIndependent()),
79 ABI(static_cast(TM).getABI()) {}
77 MipsLongBranch()
78 : MachineFunctionPass(ID), ABI(MipsABIInfo::Unknown()) {}
8079
8180 StringRef getPassName() const override { return "Mips Long Branch"; }
8281
9594 MachineBasicBlock *MBBOpnd);
9695 void expandToLongBranch(MBBInfo &Info);
9796
98 const TargetMachine &TM;
9997 MachineFunction *MF;
10098 SmallVector MBBInfos;
10199 bool IsPIC;
468466 static_cast(F.getSubtarget());
469467 const MipsInstrInfo *TII =
470468 static_cast(STI.getInstrInfo());
469
470
471 const TargetMachine& TM = F.getTarget();
472 IsPIC = TM.isPositionIndependent();
473 ABI = static_cast(TM).getABI();
474
471475 LongBranchSeqSize =
472476 !IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
473477
540544
541545 /// createMipsLongBranchPass - Returns a pass that converts branches to long
542546 /// branches.
543 FunctionPass *llvm::createMipsLongBranchPass(MipsTargetMachine &tm) {
544 return new MipsLongBranch(tm);
545 }
547 FunctionPass *llvm::createMipsLongBranchPass() { return new MipsLongBranch(); }
99
1010 #include "Mips.h"
1111 #include "MipsTargetMachine.h"
12 #include "llvm/CodeGen/TargetPassConfig.h"
1213 #include "llvm/Support/Debug.h"
1314 #include "llvm/Support/raw_ostream.h"
1415
2122 public:
2223 static char ID;
2324
24 explicit MipsModuleDAGToDAGISel(MipsTargetMachine &TM_)
25 : MachineFunctionPass(ID), TM(TM_) {}
25 MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) {}
2626
2727 // Pass Name
2828 StringRef getPassName() const override {
2929 return "MIPS DAG->DAG Pattern Instruction Selection";
3030 }
3131
32 void getAnalysisUsage(AnalysisUsage &AU) const override {
33 AU.addRequired();
34 MachineFunctionPass::getAnalysisUsage(AU);
35 }
36
3237 bool runOnMachineFunction(MachineFunction &MF) override;
33
34 protected:
35 MipsTargetMachine &TM;
3638 };
3739
3840 char MipsModuleDAGToDAGISel::ID = 0;
4042
4143 bool MipsModuleDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
4244 DEBUG(errs() << "In MipsModuleDAGToDAGISel::runMachineFunction\n");
45 auto &TPC = getAnalysis();
46 auto &TM = TPC.getTM();
4347 TM.resetSubtarget(&MF);
4448 return false;
4549 }
4650
47 llvm::FunctionPass *llvm::createMipsModuleISelDagPass(MipsTargetMachine &TM) {
48 return new MipsModuleDAGToDAGISel(TM);
51 llvm::FunctionPass *llvm::createMipsModuleISelDagPass() {
52 return new MipsModuleDAGToDAGISel();
4953 }
5858
5959 class OptimizePICCall : public MachineFunctionPass {
6060 public:
61 OptimizePICCall(TargetMachine &tm) : MachineFunctionPass(ID) {}
61 OptimizePICCall() : MachineFunctionPass(ID) {}
6262
6363 StringRef getPassName() const override { return "Mips OptimizePICCall"; }
6464
296296 }
297297
298298 /// Return an OptimizeCall object.
299 FunctionPass *llvm::createMipsOptimizePICCallPass(MipsTargetMachine &TM) {
300 return new OptimizePICCall(TM);
301 }
299 FunctionPass *llvm::createMipsOptimizePICCallPass() {
300 return new OptimizePICCall();
301 }
154154 return modified;
155155 }
156156
157 ModulePass *llvm::createMipsOs16Pass(MipsTargetMachine &TM) {
158 return new MipsOs16;
159 }
157 ModulePass *llvm::createMipsOs16Pass() { return new MipsOs16(); }
222222
223223 void MipsPassConfig::addIRPasses() {
224224 TargetPassConfig::addIRPasses();
225 addPass(createAtomicExpandPass(&getMipsTargetMachine()));
225 addPass(createAtomicExpandPass());
226226 if (getMipsSubtarget().os16())
227 addPass(createMipsOs16Pass(getMipsTargetMachine()));
227 addPass(createMipsOs16Pass());
228228 if (getMipsSubtarget().inMips16HardFloat())
229 addPass(createMips16HardFloatPass(getMipsTargetMachine()));
229 addPass(createMips16HardFloatPass());
230230 }
231231 // Install an instruction selector pass using
232232 // the ISelDag to gen Mips code.
233233 bool MipsPassConfig::addInstSelector() {
234 addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
234 addPass(createMipsModuleISelDagPass());
235235 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
236236 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
237237 return false;
238238 }
239239
240240 void MipsPassConfig::addPreRegAlloc() {
241 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
241 addPass(createMipsOptimizePICCallPass());
242242 }
243243
244244 TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
258258 // machine code is emitted. return true if -print-machineinstrs should
259259 // print out the code after the passes.
260260 void MipsPassConfig::addPreEmitPass() {
261 MipsTargetMachine &TM = getMipsTargetMachine();
262261 addPass(createMicroMipsSizeReductionPass());
263262
264263 // The delay slot filler pass can potientially create forbidden slot (FS)
265264 // hazards for MIPSR6 which the hazard schedule pass (HSP) will fix. Any
266265 // (new) pass that creates compact branches after the HSP must handle FS
267266 // hazards itself or be pipelined before the HSP.
268 addPass(createMipsDelaySlotFillerPass(TM));
267 addPass(createMipsDelaySlotFillerPass());
269268 addPass(createMipsHazardSchedule());
270 addPass(createMipsLongBranchPass(TM));
269 addPass(createMipsLongBranchPass());
271270 addPass(createMipsConstantIslandPass());
272271 }
321321 void PPCPassConfig::addIRPasses() {
322322 if (TM->getOptLevel() != CodeGenOpt::None)
323323 addPass(createPPCBoolRetToIntPass());
324 addPass(createAtomicExpandPass(&getPPCTargetMachine()));
324 addPass(createAtomicExpandPass());
325325
326326 // For the BG/Q (or if explicitly requested), add explicit data prefetch
327327 // intrinsics.
9595 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
9696 /// slots in Sparc MachineFunctions
9797 ///
98 FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
98 FunctionPass *llvm::createSparcDelaySlotFillerPass() {
9999 return new Filler;
100100 }
101101
2020 #include "llvm/Support/raw_ostream.h"
2121 using namespace llvm;
2222
23 LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char &ID)
24 : MachineFunctionPass(ID) {}
25
2623 LEONMachineFunctionPass::LEONMachineFunctionPass(char &ID)
2724 : MachineFunctionPass(ID) {}
2825
7168 //
7269 char InsertNOPLoad::ID = 0;
7370
74 InsertNOPLoad::InsertNOPLoad(TargetMachine &tm)
75 : LEONMachineFunctionPass(tm, ID) {}
71 InsertNOPLoad::InsertNOPLoad() : LEONMachineFunctionPass(ID) {}
7672
7773 bool InsertNOPLoad::runOnMachineFunction(MachineFunction &MF) {
7874 Subtarget = &MF.getSubtarget();
113109 //
114110 char FixFSMULD::ID = 0;
115111
116 FixFSMULD::FixFSMULD(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
112 FixFSMULD::FixFSMULD() : LEONMachineFunctionPass(ID) {}
117113
118114 bool FixFSMULD::runOnMachineFunction(MachineFunction &MF) {
119115 Subtarget = &MF.getSubtarget();
202198 //
203199 char ReplaceFMULS::ID = 0;
204200
205 ReplaceFMULS::ReplaceFMULS(TargetMachine &tm)
206 : LEONMachineFunctionPass(tm, ID) {}
201 ReplaceFMULS::ReplaceFMULS() : LEONMachineFunctionPass(ID) {}
207202
208203 bool ReplaceFMULS::runOnMachineFunction(MachineFunction &MF) {
209204 Subtarget = &MF.getSubtarget();
286281
287282 char DetectRoundChange::ID = 0;
288283
289 DetectRoundChange::DetectRoundChange(TargetMachine &tm)
290 : LEONMachineFunctionPass(tm, ID) {}
284 DetectRoundChange::DetectRoundChange() : LEONMachineFunctionPass(ID) {}
291285
292286 bool DetectRoundChange::runOnMachineFunction(MachineFunction &MF) {
293287 Subtarget = &MF.getSubtarget();
337331 //
338332 char FixAllFDIVSQRT::ID = 0;
339333
340 FixAllFDIVSQRT::FixAllFDIVSQRT(TargetMachine &tm)
341 : LEONMachineFunctionPass(tm, ID) {}
334 FixAllFDIVSQRT::FixAllFDIVSQRT() : LEONMachineFunctionPass(ID) {}
342335
343336 bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) {
344337 Subtarget = &MF.getSubtarget();
3131 std::vector UsedRegisters;
3232
3333 protected:
34 LEONMachineFunctionPass(TargetMachine &tm, char &ID);
3534 LEONMachineFunctionPass(char &ID);
3635
3736 int GetRegIndexForOperand(MachineInstr &MI, int OperandIndex);
4746 public:
4847 static char ID;
4948
50 InsertNOPLoad(TargetMachine &tm);
49 InsertNOPLoad();
5150 bool runOnMachineFunction(MachineFunction &MF) override;
5251
5352 StringRef getPassName() const override {
6160 public:
6261 static char ID;
6362
64 FixFSMULD(TargetMachine &tm);
63 FixFSMULD();
6564 bool runOnMachineFunction(MachineFunction &MF) override;
6665
6766 StringRef getPassName() const override {
7372 public:
7473 static char ID;
7574
76 ReplaceFMULS(TargetMachine &tm);
75 ReplaceFMULS();
7776 bool runOnMachineFunction(MachineFunction &MF) override;
7877
7978 StringRef getPassName() const override {
8887 public:
8988 static char ID;
9089
91 DetectRoundChange(TargetMachine &tm);
90 DetectRoundChange();
9291 bool runOnMachineFunction(MachineFunction &MF) override;
9392
9493 StringRef getPassName() const override {
101100 public:
102101 static char ID;
103102
104 FixAllFDIVSQRT(TargetMachine &tm);
103 FixAllFDIVSQRT();
105104 bool runOnMachineFunction(MachineFunction &MF) override;
106105
107106 StringRef getPassName() const override {
2727 class MachineInstr;
2828
2929 FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
30 FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
30 FunctionPass *createSparcDelaySlotFillerPass();
3131
3232 void LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
3333 MCInst &OutMI,
131131 }
132132
133133 void SparcPassConfig::addIRPasses() {
134 addPass(createAtomicExpandPass(&getSparcTargetMachine()));
134 addPass(createAtomicExpandPass());
135135
136136 TargetPassConfig::addIRPasses();
137137 }
142142 }
143143
144144 void SparcPassConfig::addPreEmitPass(){
145 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
145 addPass(createSparcDelaySlotFillerPass());
146146
147147 if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
148148 {
149 addPass(new InsertNOPLoad(getSparcTargetMachine()));
149 addPass(new InsertNOPLoad());
150150 }
151151 if (this->getSparcTargetMachine().getSubtargetImpl()->fixFSMULD())
152152 {
153 addPass(new FixFSMULD(getSparcTargetMachine()));
153 addPass(new FixFSMULD());
154154 }
155155 if (this->getSparcTargetMachine().getSubtargetImpl()->replaceFMULS())
156156 {
157 addPass(new ReplaceFMULS(getSparcTargetMachine()));
157 addPass(new ReplaceFMULS());
158158 }
159159 if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
160 addPass(new DetectRoundChange(getSparcTargetMachine()));
160 addPass(new DetectRoundChange());
161161 }
162162 if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
163163 {
164 addPass(new FixAllFDIVSQRT(getSparcTargetMachine()));
164 addPass(new FixAllFDIVSQRT());
165165 }
166166 }
167167
172172 else
173173 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
174174 // control specifically what gets lowered.
175 addPass(createAtomicExpandPass(TM));
175 addPass(createAtomicExpandPass());
176176
177177 // Fix function bitcasts, as WebAssembly requires caller and callee signatures
178178 // to match.
379379 }
380380
381381 void X86PassConfig::addIRPasses() {
382 addPass(createAtomicExpandPass(&getX86TargetMachine()));
382 addPass(createAtomicExpandPass());
383383
384384 TargetPassConfig::addIRPasses();
385385
386386 if (TM->getOptLevel() != CodeGenOpt::None)
387 addPass(createInterleavedAccessPass(TM));
387 addPass(createInterleavedAccessPass());
388388 }
389389
390390 bool X86PassConfig::addInstSelector() {
7373 }
7474
7575 void XCorePassConfig::addIRPasses() {
76 addPass(createAtomicExpandPass(&getXCoreTargetMachine()));
76 addPass(createAtomicExpandPass());
7777
7878 TargetPassConfig::addIRPasses();
7979 }
0 ; RUN: not opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s
1
2 ; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass without a target triple set?
33
44 ; CHECK-LABEL: Pass Arguments:
55 ; CHECK-NEXT: Target Library Information
6 ; CHECK-NEXT: Target Pass Configuration
67 ; CHECK-NEXT: Target Transform Information
7 ; CHECK-NEXT: Target Pass Configuration
88 ; CHECK-NEXT: Type-Based Alias Analysis
99 ; CHECK-NEXT: Scoped NoAlias Alias Analysis
1010 ; CHECK-NEXT: Assumption Cache Tracker
355355 }
356356
357357 Pass *P;
358 if (PI->getTargetMachineCtor())
359 P = PI->getTargetMachineCtor()(&TPC.getTM());
360 else if (PI->getNormalCtor())
358 if (PI->getNormalCtor())
361359 P = PI->getNormalCtor()();
362360 else {
363361 errs() << argv0 << ": cannot create pass: " << PI->getPassName() << "\n";
2323 #include "llvm/Analysis/TargetTransformInfo.h"
2424 #include "llvm/Bitcode/BitcodeWriterPass.h"
2525 #include "llvm/CodeGen/CommandFlags.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
2627 #include "llvm/IR/DataLayout.h"
2728 #include "llvm/IR/DebugInfo.h"
2829 #include "llvm/IR/IRPrintingPasses.h"
578579 NoOutput = true;
579580 }
580581
582 if (TM) {
583 // FIXME: We should dyn_cast this when supported.
584 auto <M = static_cast(*TM);
585 Pass *TPC = LTM.createPassConfig(Passes);
586 Passes.add(TPC);
587 }
588
581589 // Create a new optimization pass for each one specified on the command line
582590 for (unsigned i = 0; i < PassList.size(); ++i) {
583591 if (StandardLinkOpts &&
618626
619627 const PassInfo *PassInf = PassList[i];
620628 Pass *P = nullptr;
621 if (PassInf->getTargetMachineCtor())
622 P = PassInf->getTargetMachineCtor()(TM.get());
623 else if (PassInf->getNormalCtor())
629 if (PassInf->getNormalCtor())
624630 P = PassInf->getNormalCtor()();
625631 else
626632 errs() << argv[0] << ": cannot create pass: "