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Merging r266825: ------------------------------------------------------------------------ r266825 | nhaehnle | 2016-04-19 14:58:22 -0700 (Tue, 19 Apr 2016) | 12 lines AMDGPU: Guard VOPC instructions against incorrect commute Summary: The added testcase, which triggered this, was derived from a shader-db case via bugpoint. A separate question is why scalar branching wasn't used. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19208 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271767 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
2 changed file(s) with 53 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
916916 MachineOperand &Src1 = MI->getOperand(Src1Idx);
917917
918918
919 if (isVOP2(*MI)) {
919 if (isVOP2(*MI) || isVOPC(*MI)) {
920920 const MCInstrDesc &InstrDesc = MI->getDesc();
921 // For VOP2 instructions, any operand type is valid to use for src0. Make
922 // sure we can use the src1 as src0.
921 // For VOP2 and VOPC instructions, any operand type is valid to use for
922 // src0. Make sure we can use the src0 as src1.
923923 //
924924 // We could be stricter here and only allow commuting if there is a reason
925925 // to do so. i.e. if both operands are VGPRs there is no real benefit,
0 ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
1 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
2
3 target triple = "amdgcn--"
4
5 ; CHECK-LABEL: {{^}}main:
6 ;
7 ; Test for compilation only. This generated an invalid machine instruction
8 ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
9 ; of which were in SGPRs.
10 define float @main(i32 %v) #2 {
11 main_body:
12 %d1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 960)
13 %d2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 976)
14 br i1 undef, label %ENDIF56, label %IF57
15
16 IF57: ; preds = %ENDIF
17 %v.1 = mul i32 %v, 2
18 br label %ENDIF56
19
20 ENDIF56: ; preds = %IF57, %ENDIF
21 %v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ]
22 %d1.i = bitcast float %d1 to i32
23 %cc1 = icmp eq i32 %d1.i, 0
24 br i1 %cc1, label %ENDIF59, label %IF60
25
26 IF60: ; preds = %ENDIF56
27 %v.3 = mul i32 %v.2, 2
28 br label %ENDIF59
29
30 ENDIF59: ; preds = %IF60, %ENDIF56
31 %v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ]
32 %d2.i = bitcast float %d2 to i32
33 %cc2 = icmp eq i32 %d2.i, 0
34 br i1 %cc2, label %ENDIF62, label %IF63
35
36 IF63: ; preds = %ENDIF59
37 unreachable
38
39 ENDIF62: ; preds = %ENDIF59
40 %r = bitcast i32 %v.4 to float
41 ret float %r
42 }
43
44 ; Function Attrs: nounwind readnone
45 declare float @llvm.SI.load.const(<16 x i8>, i32) #0
46
47 attributes #0 = { nounwind readnone }
48 attributes #1 = { readnone }
49 attributes #2 = { "ShaderType"="1" }