llvm.org GIT mirror llvm / ad9769a
R600/SI: Use a custom encoding method for simm16 in SOPP branch instructions This allows us to explicitly define the type of fixup that is needed, so we can distinguish this from future fixup types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213527 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
6 changed file(s) with 89 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
88 //===----------------------------------------------------------------------===//
99
1010 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
11 #include "MCTargetDesc/AMDGPUFixupKinds.h"
1112 #include "llvm/ADT/StringRef.h"
1213 #include "llvm/MC/MCAsmBackend.h"
1314 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCFixupKindInfo.h"
1416 #include "llvm/MC/MCObjectWriter.h"
1517 #include "llvm/MC/MCValue.h"
1618 #include "llvm/Support/TargetRegistry.h"
5759 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
5860 return true;
5961 }
62
63 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
6064 };
6165
6266 } //End anonymous namespace
7579 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
7680 assert(Fixup.getKind() == FK_PCRel_4);
7781 *Dst = (Value - 4) / 4;
82 }
83
84 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
85 MCFixupKind Kind) const {
86 const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
87 // name offset bits flags
88 { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
89 };
90
91 if (Kind < FirstTargetFixupKind)
92 return MCAsmBackend::getFixupKindInfo(Kind);
93
94 return Infos[Kind - FirstTargetFixupKind];
7895 }
7996
8097 //===----------------------------------------------------------------------===//
0 //===-- AMDGPUFixupKinds.h - AMDGPU Specific Fixup Entries ------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #ifndef LLVM_AMDGPUFIXUPKINDS_H
10 #define LLVM_AMDGPUFIXUPKINDS_H
11
12 #include "llvm/MC/MCFixup.h"
13
14 namespace llvm {
15 namespace AMDGPU {
16 enum Fixups {
17 /// 16-bit PC relative fixup for SOPP branch instructions.
18 fixup_si_sopp_br = FirstTargetFixupKind,
19
20 // Marker
21 LastTargetFixupKind,
22 NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
23 };
24 }
25 }
26
27 #endif // LLVM_AMDGPUFIXUPKINDS_H
3636 const MCSubtargetInfo &STI) const {
3737 return 0;
3838 }
39
40 virtual unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
41 SmallVectorImpl &Fixups,
42 const MCSubtargetInfo &STI) const {
43 return 0;
44 }
3945 };
4046
4147 } // End namespace llvm
1414
1515 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
1616 #include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
17 #include "MCTargetDesc/AMDGPUFixupKinds.h"
1718 #include "llvm/MC/MCCodeEmitter.h"
1819 #include "llvm/MC/MCContext.h"
1920 #include "llvm/MC/MCFixup.h"
6162 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
6263 SmallVectorImpl &Fixups,
6364 const MCSubtargetInfo &STI) const override;
65
66 /// \brief Use a fixup to encode the simm16 field for SOPP branch
67 /// instructions.
68 unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
69 SmallVectorImpl &Fixups,
70 const MCSubtargetInfo &STI) const override;
6471 };
6572
6673 } // End anonymous namespace
168175 }
169176 }
170177
178 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
179 SmallVectorImpl &Fixups,
180 const MCSubtargetInfo &STI) const {
181 const MCOperand &MO = MI.getOperand(OpNo);
182
183 if (MO.isExpr()) {
184 const MCExpr *Expr = MO.getExpr();
185 MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
186 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
187 return 0;
188 }
189
190 return getMachineOpValue(MI, MO, Fixups, STI);
191 }
192
171193 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
172194 const MCOperand &MO,
173195 SmallVectorImpl &Fixups,
175197 if (MO.isReg())
176198 return MRI.getEncodingValue(MO.getReg());
177199
178 if (MO.isExpr()) {
179 const MCExpr *Expr = MO.getExpr();
180 MCFixupKind Kind = MCFixupKind(FK_PCRel_4);
181 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
182 return 0;
183 }
184
185200 // Figure out the operand number, needed for isSrcOperand check
186201 unsigned OpNo = 0;
187202 for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
141141 return false;
142142 }]>;
143143
144 //===----------------------------------------------------------------------===//
145 // Custom Operands
146 //===----------------------------------------------------------------------===//
147
144148 def FRAMEri32 : Operand {
145149 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
150 }
151
152 def sopp_brtarget : Operand {
153 let EncoderMethod = "getSOPPBrEncoding";
154 let OperandType = "OPERAND_PCREL";
146155 }
147156
148157 //===----------------------------------------------------------------------===//
377377
378378 let isBranch = 1 in {
379379 def S_BRANCH : SOPP <
380 0x00000002, (ins brtarget:$simm16), "S_BRANCH $simm16",
380 0x00000002, (ins sopp_brtarget:$simm16), "S_BRANCH $simm16",
381381 [(br bb:$simm16)]> {
382382 let isBarrier = 1;
383383 }
384384
385385 let DisableEncoding = "$scc" in {
386386 def S_CBRANCH_SCC0 : SOPP <
387 0x00000004, (ins brtarget:$simm16, SCCReg:$scc),
387 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
388388 "S_CBRANCH_SCC0 $simm16", []
389389 >;
390390 def S_CBRANCH_SCC1 : SOPP <
391 0x00000005, (ins brtarget:$simm16, SCCReg:$scc),
391 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
392392 "S_CBRANCH_SCC1 $simm16",
393393 []
394394 >;
395395 } // End DisableEncoding = "$scc"
396396
397397 def S_CBRANCH_VCCZ : SOPP <
398 0x00000006, (ins brtarget:$simm16, VCCReg:$vcc),
398 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
399399 "S_CBRANCH_VCCZ $simm16",
400400 []
401401 >;
402402 def S_CBRANCH_VCCNZ : SOPP <
403 0x00000007, (ins brtarget:$simm16, VCCReg:$vcc),
403 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
404404 "S_CBRANCH_VCCNZ $simm16",
405405 []
406406 >;
407407
408408 let DisableEncoding = "$exec" in {
409409 def S_CBRANCH_EXECZ : SOPP <
410 0x00000008, (ins brtarget:$simm16, EXECReg:$exec),
410 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),
411411 "S_CBRANCH_EXECZ $simm16",
412412 []
413413 >;
414414 def S_CBRANCH_EXECNZ : SOPP <
415 0x00000009, (ins brtarget:$simm16, EXECReg:$exec),
415 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),
416416 "S_CBRANCH_EXECNZ $simm16",
417417 []
418418 >;