llvm.org GIT mirror llvm / ad934b8
Clean up LiveVariables and change how it deals with partial updates and kills. This also eliminate the horrible check which scan forward to the end of the basic block. It should be faster and more accurate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82676 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
5 changed file(s) with 176 addition(s) and 215 deletion(s). Raw diff Collapse all Expand all
149149
150150 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
151151 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
152 SmallVector &Defs,
153 SmallVector &SuperDefs);
152 SmallVector &Defs);
154153 void UpdatePhysRegDefs(MachineInstr *MI, SmallVector &Defs);
155 void UpdateSuperRegDefs(MachineInstr *MI, SmallVector &Defs);
156154
157155 /// FindLastPartialDef - Return the last partial def of the specified register.
158156 /// Also returns the sub-registers that're defined by the instruction.
159157 MachineInstr *FindLastPartialDef(unsigned Reg,
160158 SmallSet &PartDefRegs);
161
162 /// hasRegisterUseBelow - Return true if the specified register is used after
163 /// the current instruction and before its next definition.
164 bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
165 MachineBasicBlock *MBB);
166159
167160 /// analyzePHINodes - Gather information about the PHI nodes in here. In
168161 /// particular, we want to map the variable information of a virtual
264264 PhysRegUse[SubReg] = MI;
265265 }
266266
267 /// hasRegisterUseBelow - Return true if the specified register is used after
268 /// the current instruction and before it's next definition.
269 bool LiveVariables::hasRegisterUseBelow(unsigned Reg,
270 MachineBasicBlock::iterator I,
271 MachineBasicBlock *MBB) {
272 if (I == MBB->end())
267 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
268 MachineInstr *LastDef = PhysRegDef[Reg];
269 MachineInstr *LastUse = PhysRegUse[Reg];
270 if (!LastDef && !LastUse)
273271 return false;
274272
275 // First find out if there are any uses / defs below.
276 bool hasDistInfo = true;
277 unsigned CurDist = DistanceMap[I];
278 SmallVector Uses;
279 SmallVector Defs;
280 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
281 RE = MRI->reg_end(); RI != RE; ++RI) {
282 MachineOperand &UDO = RI.getOperand();
283 MachineInstr *UDMI = &*RI;
284 if (UDMI->getParent() != MBB)
285 continue;
286 DenseMap::iterator DI = DistanceMap.find(UDMI);
287 bool isBelow = false;
288 if (DI == DistanceMap.end()) {
289 // Must be below if it hasn't been assigned a distance yet.
290 isBelow = true;
291 hasDistInfo = false;
292 } else if (DI->second > CurDist)
293 isBelow = true;
294 if (isBelow) {
295 if (UDO.isUse())
296 Uses.push_back(UDMI);
297 if (UDO.isDef())
298 Defs.push_back(UDMI);
299 }
300 }
301
302 if (Uses.empty())
303 // No uses below.
304 return false;
305 else if (!Uses.empty() && Defs.empty())
306 // There are uses below but no defs below.
307 return true;
308 // There are both uses and defs below. We need to know which comes first.
309 if (!hasDistInfo) {
310 // Complete DistanceMap for this MBB. This information is computed only
311 // once per MBB.
312 ++I;
313 ++CurDist;
314 for (MachineBasicBlock::iterator E = MBB->end(); I != E; ++I, ++CurDist)
315 DistanceMap.insert(std::make_pair(I, CurDist));
316 }
317
318 unsigned EarliestUse = DistanceMap[Uses[0]];
319 for (unsigned i = 1, e = Uses.size(); i != e; ++i) {
320 unsigned Dist = DistanceMap[Uses[i]];
321 if (Dist < EarliestUse)
322 EarliestUse = Dist;
323 }
324 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
325 unsigned Dist = DistanceMap[Defs[i]];
326 if (Dist < EarliestUse)
327 // The register is defined before its first use below.
328 return false;
329 }
330 return true;
331 }
332
333 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
334 if (!PhysRegUse[Reg] && !PhysRegDef[Reg])
335 return false;
336
337 MachineInstr *LastRefOrPartRef = PhysRegUse[Reg]
338 ? PhysRegUse[Reg] : PhysRegDef[Reg];
273 MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
339274 unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
340275 // The whole register is used.
341276 // AL =
354289 // AX = AL
355290 // = AL
356291 // AX =
292 MachineInstr *LastPartDef = 0;
293 unsigned LastPartDefDist = 0;
357294 SmallSet PartUses;
358295 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
359296 unsigned SubReg = *SubRegs; ++SubRegs) {
297 MachineInstr *Def = PhysRegDef[SubReg];
298 if (Def && Def != LastDef) {
299 // There was a def of this sub-register in between. This is a partial
300 // def, keep track of the last one.
301 unsigned Dist = DistanceMap[Def];
302 if (Dist > LastPartDefDist) {
303 LastPartDefDist = Dist;
304 LastPartDef = Def;
305 }
306 continue;
307 }
360308 if (MachineInstr *Use = PhysRegUse[SubReg]) {
361309 PartUses.insert(SubReg);
362310 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
369317 }
370318 }
371319
372 if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI)
373 // If the last reference is the last def, then it's not used at all.
374 // That is, unless we are currently processing the last reference itself.
375 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
376
377 // Partial uses. Mark register def dead and add implicit def of
378 // sub-registers which are used.
379 // EAX = op AL
380 // That is, EAX def is dead but AL def extends pass it.
381 // Enable this after live interval analysis is fixed to improve codegen!
382 else if (!PhysRegUse[Reg]) {
320 if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
321 if (LastPartDef)
322 // The last partial def kills the register.
323 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
324 true/*IsImp*/, true/*IsKill*/));
325 else
326 // If the last reference is the last def, then it's not used at all.
327 // That is, unless we are currently processing the last reference itself.
328 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
329 } else if (!PhysRegUse[Reg]) {
330 // Partial uses. Mark register def dead and add implicit def of
331 // sub-registers which are used.
332 // EAX = op AL
333 // That is, EAX def is dead but AL def extends pass it.
383334 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
384335 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
385336 unsigned SubReg = *SubRegs; ++SubRegs) {
386 if (PartUses.count(SubReg)) {
387 bool NeedDef = true;
388 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
389 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
390 if (MO) {
391 NeedDef = false;
392 assert(!MO->isDead());
393 }
337 if (!PartUses.count(SubReg))
338 continue;
339 bool NeedDef = true;
340 if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
341 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
342 if (MO) {
343 NeedDef = false;
344 assert(!MO->isDead());
394345 }
395 if (NeedDef)
396 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
397 true, true));
398 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
399 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
400 PartUses.erase(*SS);
401 }
402 }
403 }
404 else
346 }
347 if (NeedDef)
348 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
349 true/*IsDef*/, true/*IsImp*/));
350 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
351 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
352 PartUses.erase(*SS);
353 }
354 } else
405355 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
406356 return true;
407357 }
408358
409359 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
410 SmallVector &Defs,
411 SmallVector &SuperDefs) {
360 SmallVector &Defs) {
412361 // What parts of the register are previously defined?
413362 SmallSet Live;
414363 if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
424373 // AL =
425374 // AH =
426375 // = AX
376 if (Live.count(SubReg))
377 continue;
427378 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
428379 Live.insert(SubReg);
429380 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
434385
435386 // Start from the largest piece, find the last time any part of the register
436387 // is referenced.
437 if (!HandlePhysRegKill(Reg, MI)) {
438 // Only some of the sub-registers are used.
439 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
440 unsigned SubReg = *SubRegs; ++SubRegs) {
441 if (!Live.count(SubReg))
442 // Skip if this sub-register isn't defined.
443 continue;
444 if (HandlePhysRegKill(SubReg, MI)) {
445 Live.erase(SubReg);
446 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
447 Live.erase(*SS);
448 }
449 }
450 assert(Live.empty() && "Not all defined registers are killed / dead?");
451 }
452
453 if (MI) {
454 // Does this extend the live range of a super-register?
455 SmallSet Processed;
456 for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
457 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
458 if (Processed.count(SuperReg))
459 continue;
460 MachineInstr *LastRef = PhysRegUse[SuperReg]
461 ? PhysRegUse[SuperReg] : PhysRegDef[SuperReg];
462 if (LastRef && LastRef != MI) {
463 // The larger register is previously defined. Now a smaller part is
464 // being re-defined. Treat it as read/mod/write if there are uses
465 // below.
466 // EAX =
467 // AX = EAX, EAX
468 // ...
469 // = EAX
470 SuperDefs.push_back(SuperReg);
471 Processed.insert(SuperReg);
472 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS)
473 Processed.insert(*SS);
474 }
475 }
476
477 // Remember this def.
478 Defs.push_back(Reg);
479 }
388 HandlePhysRegKill(Reg, MI);
389 // Only some of the sub-registers are used.
390 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
391 unsigned SubReg = *SubRegs; ++SubRegs) {
392 if (!Live.count(SubReg))
393 // Skip if this sub-register isn't defined.
394 continue;
395 HandlePhysRegKill(SubReg, MI);
396 }
397
398 if (MI)
399 Defs.push_back(Reg); // Remember this def.
480400 }
481401
482402 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
509429 };
510430 }
511431
512 void LiveVariables::UpdateSuperRegDefs(MachineInstr *MI,
513 SmallVector &SuperDefs) {
514 // This instruction has defined part of some registers. If there are no
515 // more uses below MI, then the last use / def becomes kill / dead.
516 if (SuperDefs.empty())
517 return;
518
519 RegSorter RS(TRI);
520 std::sort(SuperDefs.begin(), SuperDefs.end(), RS);
521 SmallSet Processed;
522 for (unsigned j = 0, ee = SuperDefs.size(); j != ee; ++j) {
523 unsigned SuperReg = SuperDefs[j];
524 if (!Processed.insert(SuperReg))
525 continue;
526 if (hasRegisterUseBelow(SuperReg, MI, MI->getParent())) {
527 // Previous use / def is not the last use / dead def. It's now
528 // partially re-defined.
529 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
530 true/*IsImp*/,true/*IsKill*/));
531 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
532 true/*IsImp*/));
533 PhysRegDef[SuperReg] = MI;
534 PhysRegUse[SuperReg] = NULL;
535 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
536 Processed.insert(*SS);
537 PhysRegDef[*SS] = MI;
538 PhysRegUse[*SS] = NULL;
539 }
540 } else {
541 // Previous use / def is kill / dead. It's not being re-defined.
542 HandlePhysRegKill(SuperReg, MI);
543 PhysRegDef[SuperReg] = 0;
544 PhysRegUse[SuperReg] = NULL;
545 for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
546 Processed.insert(*SS);
547 if (PhysRegDef[*SS] == MI)
548 continue; // This instruction may have defined it.
549 PhysRegDef[*SS] = MI;
550 PhysRegUse[*SS] = NULL;
551 }
552 }
553 }
554 SuperDefs.clear();
555 }
556
557432 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
558433 MF = &mf;
559434 MRI = &mf.getRegInfo();
587462
588463 // Mark live-in registers as live-in.
589464 SmallVector Defs;
590 SmallVector SuperDefs;
591465 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
592466 EE = MBB->livein_end(); II != EE; ++II) {
593467 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
594468 "Cannot have a live-in virtual register!");
595 HandlePhysRegDef(*II, 0, Defs, SuperDefs);
596 UpdatePhysRegDefs(0, Defs);
597 SuperDefs.clear();
469 HandlePhysRegDef(*II, 0, Defs);
598470 }
599471
600472 // Loop over all of the instructions, processing them.
640512 unsigned MOReg = DefRegs[i];
641513 if (TargetRegisterInfo::isVirtualRegister(MOReg))
642514 HandleVirtRegDef(MOReg, MI);
643 else if (!ReservedRegisters[MOReg]) {
644 HandlePhysRegDef(MOReg, MI, Defs, SuperDefs);
645 }
646 }
647
648 UpdateSuperRegDefs(MI, SuperDefs);
515 else if (!ReservedRegisters[MOReg])
516 HandlePhysRegDef(MOReg, MI, Defs);
517 }
649518 UpdatePhysRegDefs(MI, Defs);
650519 }
651520
684553 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
685554 // available at the end of the basic block.
686555 for (unsigned i = 0; i != NumRegs; ++i)
687 if (PhysRegDef[i] || PhysRegUse[i]) {
688 HandlePhysRegDef(i, 0, Defs, SuperDefs);
689 UpdatePhysRegDefs(0, Defs);
690 SuperDefs.clear();
691 }
556 if (PhysRegDef[i] || PhysRegUse[i])
557 HandlePhysRegDef(i, 0, Defs);
692558
693559 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
694560 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
265265 }
266266 }
267267 return false;
268 }
269
270 static void
271 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
272 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
273 i != e; ++i) {
274 MachineOperand &MO = MI->getOperand(i);
275 if (MO.isReg() && MO.isImplicit())
276 NewMI->addOperand(MO);
277 }
268278 }
269279
270280 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
415425 ++UI;
416426 if (JoinedCopies.count(UseMI))
417427 continue;
418 MachineInstrIndex UseIdx = li_->getInstructionIndex(UseMI);
428 MachineInstrIndex UseIdx= li_->getUseIndex(li_->getInstructionIndex(UseMI));
419429 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
420430 if (ULR == IntA.end() || ULR->valno != AValNo)
421431 continue;
426436 if (Extended)
427437 UseMO.setIsKill(false);
428438 else
429 BKills.push_back(li_->getNextSlot(li_->getUseIndex(UseIdx)));
439 BKills.push_back(li_->getNextSlot(UseIdx));
430440 }
431441 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
432442 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
723733 }
724734 }
725735
736 TransferImplicitOps(CopyMI, NewMI);
726737 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
727738 CopyMI->eraseFromParent();
728739 ReMatCopies.insert(CopyMI);
None ; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 56
0 ; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 59
11 ; PR2568
22
33 @g_3 = external global i16 ; [#uses=1]
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10
1
2 ; rdar://7247745
3
4 %struct._lck_mtx_ = type { %union.anon }
5 %struct._lck_rw_t_internal_ = type <{ i16, i8, i8, i32, i32, i32 }>
6 %struct.anon = type { i64, i64, [2 x i8], i8, i8, i32 }
7 %struct.memory_object = type { i32, i32, %struct.memory_object_pager_ops* }
8 %struct.memory_object_control = type { i32, i32, %struct.vm_object* }
9 %struct.memory_object_pager_ops = type { void (%struct.memory_object*)*, void (%struct.memory_object*)*, i32 (%struct.memory_object*, %struct.memory_object_control*, i32)*, i32 (%struct.memory_object*)*, i32 (%struct.memory_object*, i64, i32, i32, i32*)*, i32 (%struct.memory_object*, i64, i32, i64*, i32*, i32, i32, i32)*, i32 (%struct.memory_object*, i64, i32)*, i32 (%struct.memory_object*, i64, i64, i32)*, i32 (%struct.memory_object*, i64, i64, i32)*, i32 (%struct.memory_object*, i32)*, i32 (%struct.memory_object*)*, i8* }
10 %struct.queue_entry = type { %struct.queue_entry*, %struct.queue_entry* }
11 %struct.upl = type { %struct._lck_mtx_, i32, i32, %struct.vm_object*, i64, i32, i64, %struct.vm_object*, i32, i8* }
12 %struct.upl_page_info = type <{ i32, i8, [3 x i8] }>
13 %struct.vm_object = type { %struct.queue_entry, %struct._lck_rw_t_internal_, i64, %struct.vm_page*, i32, i32, i32, i32, %struct.vm_object*, %struct.vm_object*, i64, %struct.memory_object*, i64, %struct.memory_object_control*, i32, i16, i16, [2 x i8], i8, i8, %struct.queue_entry, %struct.queue_entry, i64, i32, i32, i32, i8*, i64, i8, i8, [2 x i8], %struct.queue_entry }
14 %struct.vm_page = type { %struct.queue_entry, %struct.queue_entry, %struct.vm_page*, %struct.vm_object*, i64, [2 x i8], i8, i8, i32, i8, i8, i8, i8, i32 }
15 %union.anon = type { %struct.anon }
16
17 declare i64 @OSAddAtomic64(i64, i64*) noredzone noimplicitfloat
18
19 define i32 @upl_commit_range(%struct.upl* %upl, i32 %offset, i32 %size, i32 %flags, %struct.upl_page_info* %page_list, i32 %count, i32* nocapture %empty) nounwind noredzone noimplicitfloat {
20 entry:
21 br i1 undef, label %if.then, label %if.end
22
23 if.end: ; preds = %entry
24 br i1 undef, label %if.end143, label %if.then136
25
26 if.then136: ; preds = %if.end
27 unreachable
28
29 if.end143: ; preds = %if.end
30 br i1 undef, label %if.else155, label %if.then153
31
32 if.then153: ; preds = %if.end143
33 br label %while.cond
34
35 if.else155: ; preds = %if.end143
36 unreachable
37
38 while.cond: ; preds = %if.end1039, %if.then153
39 br i1 undef, label %if.then1138, label %while.body
40
41 while.body: ; preds = %while.cond
42 br i1 undef, label %if.end260, label %if.then217
43
44 if.then217: ; preds = %while.body
45 br i1 undef, label %if.end260, label %if.then230
46
47 if.then230: ; preds = %if.then217
48 br i1 undef, label %if.then246, label %if.end260
49
50 if.then246: ; preds = %if.then230
51 br label %if.end260
52
53 if.end260: ; preds = %if.then246, %if.then230, %if.then217, %while.body
54 br i1 undef, label %if.end296, label %if.then266
55
56 if.then266: ; preds = %if.end260
57 unreachable
58
59 if.end296: ; preds = %if.end260
60 br i1 undef, label %if.end1039, label %if.end306
61
62 if.end306: ; preds = %if.end296
63 br i1 undef, label %if.end796, label %if.then616
64
65 if.then616: ; preds = %if.end306
66 br i1 undef, label %commit_next_page, label %do.body716
67
68 do.body716: ; preds = %if.then616
69 %call721 = call i64 @OSAddAtomic64(i64 1, i64* undef) nounwind noredzone noimplicitfloat ; [#uses=0]
70 call void asm sideeffect "movq\090x0($0),%rdi\0A\09movq\090x8($0),%rsi\0A\09.section __DATA, __data\0A\09.globl __dtrace_probeDOLLAR${:uid}4794___vminfo____pgrec\0A\09__dtrace_probeDOLLAR${:uid}4794___vminfo____pgrec:.quad 1f\0A\09.text\0A\091:nop\0A\09nop\0A\09nop\0A\09", "r,~{memory},~{di},~{si},~{dirflag},~{fpsr},~{flags}"(i64* undef) nounwind
71 br label %commit_next_page
72
73 if.end796: ; preds = %if.end306
74 unreachable
75
76 commit_next_page: ; preds = %do.body716, %if.then616
77 br i1 undef, label %if.end1039, label %if.then1034
78
79 if.then1034: ; preds = %commit_next_page
80 br label %if.end1039
81
82 if.end1039: ; preds = %if.then1034, %commit_next_page, %if.end296
83 br label %while.cond
84
85 if.then1138: ; preds = %while.cond
86 unreachable
87
88 if.then: ; preds = %entry
89 ret i32 4
90 }