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MIR Serialization: Serialize the virtual register definitions. The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Lorenz 5 years ago
5 changed file(s) with 141 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
7979
8080 namespace llvm {
8181 namespace yaml {
82
83 struct VirtualRegisterDefinition {
84 unsigned ID;
85 StringValue Class;
86 // TODO: Serialize the virtual register hints.
87 };
88
89 template <> struct MappingTraits {
90 static void mapping(IO &YamlIO, VirtualRegisterDefinition &Reg) {
91 YamlIO.mapRequired("id", Reg.ID);
92 YamlIO.mapRequired("class", Reg.Class);
93 }
94
95 static const bool flow = true;
96 };
8297
8398 struct MachineBasicBlock {
8499 unsigned ID;
108123 } // end namespace yaml
109124 } // end namespace llvm
110125
126 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::VirtualRegisterDefinition)
111127 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineBasicBlock)
112128
113129 namespace llvm {
168184 bool IsSSA = false;
169185 bool TracksRegLiveness = false;
170186 bool TracksSubRegLiveness = false;
171 // TODO: Serialize virtual register definitions.
187 std::vector VirtualRegisters;
172188 // TODO: Serialize the various register masks.
173189 // TODO: Serialize live in registers.
174190 // Frame information
186202 YamlIO.mapOptional("isSSA", MF.IsSSA);
187203 YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
188204 YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
205 YamlIO.mapOptional("registers", MF.VirtualRegisters);
189206 YamlIO.mapOptional("frameInfo", MF.FrameInfo);
190207 YamlIO.mapOptional("body", MF.BasicBlocks);
191208 }
4848 LLVMContext &Context;
4949 StringMap> Functions;
5050 SlotMapping IRSlots;
51 /// Maps from register class names to register classes.
52 StringMap Names2RegClasses;
5153
5254 public:
5355 MIRParserImpl(std::unique_ptr Contents, StringRef Filename,
99101 const yaml::MachineBasicBlock &YamlMBB,
100102 const PerFunctionMIParsingState &PFS);
101103
102 bool initializeRegisterInfo(MachineRegisterInfo &RegInfo,
104 bool initializeRegisterInfo(const MachineFunction &MF,
105 MachineRegisterInfo &RegInfo,
103106 const yaml::MachineFunction &YamlMF);
104107
105108 bool initializeFrameInfo(MachineFrameInfo &MFI,
116119
117120 /// Create an empty function with the given name.
118121 void createDummyFunction(StringRef Name, Module &M);
122
123 void initNames2RegClasses(const MachineFunction &MF);
124
125 /// Check if the given identifier is a name of a register class.
126 ///
127 /// Return null if the name isn't a register class.
128 const TargetRegisterClass *getRegClass(const MachineFunction &MF,
129 StringRef Name);
119130 };
120131
121132 } // end namespace llvm
246257 MF.setAlignment(YamlMF.Alignment);
247258 MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
248259 MF.setHasInlineAsm(YamlMF.HasInlineAsm);
249 if (initializeRegisterInfo(MF.getRegInfo(), YamlMF))
260 if (initializeRegisterInfo(MF, MF.getRegInfo(), YamlMF))
250261 return true;
251262 if (initializeFrameInfo(*MF.getFrameInfo(), YamlMF.FrameInfo))
252263 return true;
317328 }
318329
319330 bool MIRParserImpl::initializeRegisterInfo(
320 MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF) {
331 const MachineFunction &MF, MachineRegisterInfo &RegInfo,
332 const yaml::MachineFunction &YamlMF) {
321333 assert(RegInfo.isSSA());
322334 if (!YamlMF.IsSSA)
323335 RegInfo.leaveSSA();
325337 if (!YamlMF.TracksRegLiveness)
326338 RegInfo.invalidateLiveness();
327339 RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
340
341 // Parse the virtual register information.
342 for (const auto &VReg : YamlMF.VirtualRegisters) {
343 const auto *RC = getRegClass(MF, VReg.Class.Value);
344 if (!RC)
345 return error(VReg.Class.SourceRange.Start,
346 Twine("use of undefined register class '") +
347 VReg.Class.Value + "'");
348 // TODO: create the mapping from IDs to registers so that the virtual
349 // register references can be parsed correctly.
350 RegInfo.createVirtualRegister(RC);
351 }
328352 return false;
329353 }
330354
394418 Error.getFixIts());
395419 }
396420
421 void MIRParserImpl::initNames2RegClasses(const MachineFunction &MF) {
422 if (!Names2RegClasses.empty())
423 return;
424 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
425 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; ++I) {
426 const auto *RC = TRI->getRegClass(I);
427 Names2RegClasses.insert(
428 std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC));
429 }
430 }
431
432 const TargetRegisterClass *MIRParserImpl::getRegClass(const MachineFunction &MF,
433 StringRef Name) {
434 initNames2RegClasses(MF);
435 auto RegClassInfo = Names2RegClasses.find(Name);
436 if (RegClassInfo == Names2RegClasses.end())
437 return nullptr;
438 return RegClassInfo->getValue();
439 }
440
397441 MIRParser::MIRParser(std::unique_ptr Impl)
398442 : Impl(std::move(Impl)) {}
399443
4141
4242 void print(const MachineFunction &MF);
4343
44 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
44 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
45 const TargetRegisterInfo *TRI);
4546 void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
4647 void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
4748 const MachineBasicBlock &MBB);
9495 YamlMF.Alignment = MF.getAlignment();
9596 YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
9697 YamlMF.HasInlineAsm = MF.hasInlineAsm();
97 convert(YamlMF, MF.getRegInfo());
98 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
9899 convert(YamlMF.FrameInfo, *MF.getFrameInfo());
99100
100101 int I = 0;
116117 }
117118
118119 void MIRPrinter::convert(yaml::MachineFunction &MF,
119 const MachineRegisterInfo &RegInfo) {
120 const MachineRegisterInfo &RegInfo,
121 const TargetRegisterInfo *TRI) {
120122 MF.IsSSA = RegInfo.isSSA();
121123 MF.TracksRegLiveness = RegInfo.tracksLiveness();
122124 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
125
126 // Print the virtual register definitions.
127 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
128 unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
129 yaml::VirtualRegisterDefinition VReg;
130 VReg.ID = I;
131 VReg.Class =
132 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
133 MF.VirtualRegisters.push_back(VReg);
134 }
123135 }
124136
125137 void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
0 # RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
1 # This test ensures that the MIR parser reports an error when it encounters an
2 # unknown register class.
3
4 --- |
5
6 define i32 @test(i32 %a) {
7 entry:
8 ret i32 %a
9 }
10
11 ...
12 ---
13 name: test
14 isSSA: true
15 tracksRegLiveness: true
16 registers:
17 # CHECK: [[@LINE+1]]:20: use of undefined register class 'gr3200'
18 - {id: 0, class: 'gr3200'}
19 body:
20 - id: 0
21 name: entry
22 instructions:
23 - 'RETQ %eax'
24 ...
25
0 # RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s
1 # This test ensures that the MIR parser parses virtual register definitions
2 # correctly.
3
4 --- |
5
6 define i32 @bar(i32 %a) {
7 entry:
8 %0 = icmp sle i32 %a, 10
9 br i1 %0, label %less, label %exit
10
11 less:
12 ret i32 0
13
14 exit:
15 ret i32 %a
16 }
17
18 ...
19 ---
20 name: bar
21 isSSA: true
22 tracksRegLiveness: true
23 # CHECK: registers:
24 # CHECK-NEXT: - { id: 0, class: gr32 }
25 # CHECK-NEXT: - { id: 1, class: gr32 }
26 # CHECK-NEXT: - { id: 2, class: gr32 }
27 registers:
28 - { id: 0, class: gr32 }
29 - { id: 1, class: gr32 }
30 - { id: 2, class: gr32 }
31 body:
32 - id: 0
33 ...
34