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[X86][AVX512F] Fix reg class for VMOVSSZrr/VMOVSSZrrk and VMOVSDZrr/VMOVSDZrrk Fixed -verify-machineinstrs errors in fast-isel-select-sse.ll (one of many in PR27481) The VMOVSSZrr/VMOVSSZrrk and VMOVSDZrr/VMOVSDZrrk instructions were assuming both source registers were V128X when the second is actually supposed to be FR32X/FR64X Differential Revision: https://reviews.llvm.org/D31200 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298805 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 3 years ago
2 changed file(s) with 16 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
31933193 (scalar_to_vector _.FRC:$src2))))],
31943194 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V;
31953195 def rrkz : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
3196 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
3196 (ins _.KRCWM:$mask, _.RC:$src1, _.FRC:$src2),
31973197 !strconcat(asm, "\t{$src2, $src1, $dst {${mask}} {z}|",
31983198 "$dst {${mask}} {z}, $src1, $src2}"),
31993199 [(set _.RC:$dst, (_.VT (X86selects _.KRCWM:$mask,
3200 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3200 (_.VT (OpNode _.RC:$src1,
3201 (scalar_to_vector _.FRC:$src2))),
32013202 _.ImmAllZerosV)))],
32023203 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V, EVEX_KZ;
32033204 let Constraints = "$src0 = $dst" in
32043205 def rrk : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
3205 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
3206 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1, _.FRC:$src2),
32063207 !strconcat(asm, "\t{$src2, $src1, $dst {${mask}}|",
32073208 "$dst {${mask}}, $src1, $src2}"),
32083209 [(set _.RC:$dst, (_.VT (X86selects _.KRCWM:$mask,
3209 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3210 (_.VT (OpNode _.RC:$src1,
3211 (scalar_to_vector _.FRC:$src2))),
32103212 (_.VT _.RC:$src0))))],
32113213 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V, EVEX_K;
32123214 let canFoldAsLoad = 1, isReMaterializable = 1 in
32563258 (COPY_TO_REGCLASS (!cast(InstrStr#rrk)
32573259 (COPY_TO_REGCLASS _.FRC:$src2, _.RC),
32583260 (COPY_TO_REGCLASS GR32:$mask, VK1WM),
3259 (_.VT _.RC:$src0),
3260 (COPY_TO_REGCLASS _.FRC:$src1, _.RC)),
3261 (_.VT _.RC:$src0), _.FRC:$src1),
32613262 _.RC)>;
32623263
32633264 def : Pat<(_.VT (OpNode _.RC:$src0,
32673268 (_.EltVT ZeroFP))))))),
32683269 (COPY_TO_REGCLASS (!cast(InstrStr#rrkz)
32693270 (COPY_TO_REGCLASS GR32:$mask, VK1WM),
3270 (_.VT _.RC:$src0),
3271 (COPY_TO_REGCLASS _.FRC:$src1, _.RC)),
3271 (_.VT _.RC:$src0), _.FRC:$src1),
32723272 _.RC)>;
3273
32743273 }
32753274
32763275 multiclass avx512_store_scalar_lowering
33333332
33343333 def : Pat<(f32 (X86selects VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
33353334 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
3336 VK1WM:$mask, (v4f32 (IMPLICIT_DEF)),(COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>;
3335 VK1WM:$mask, (v4f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
33373336
33383337 def : Pat<(f64 (X86selects VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
33393338 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
3340 VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR64X:$src1, VR128X)), FR64X)>;
3339 VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
33413340
33423341 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
33433342 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -fast-isel -fast-isel-abort=1 -mattr=avx | FileCheck %s --check-prefix=AVX
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefix=AVX512
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -fast-isel -fast-isel-abort=1 -mattr=avx512f | FileCheck %s --check-prefix=AVX512
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=SSE
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx | FileCheck %s --check-prefix=AVX
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=avx | FileCheck %s --check-prefix=AVX
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx512f | FileCheck %s --check-prefix=AVX512
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=avx512f | FileCheck %s --check-prefix=AVX512
77
88 ; Test all cmp predicates that can be used with SSE.
99