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[AMDGPU] Disassembler: Support for all VOP1 instructions. Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget: VGPR_32 and VReg_64 operand register classes VS_32 and VS_64 operand register classes with inline and literal constants Tests for VOP1 instructions. Patch by: skolton Reviewers: arsenm, tstellarAMD Review: http://reviews.llvm.org/D17194 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261878 91177308-0d34-0410-b5e6-96231b3b80d8 Nikolay Haustov 4 years ago
4 changed file(s) with 500 addition(s) and 70 deletion(s). Raw diff Collapse all Expand all
3838
3939 static DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
4040 uint64_t Addr, const void *Decoder) {
41 const AMDGPUDisassembler *Dis =
41 const AMDGPUDisassembler *Dis =
4242 static_cast(Decoder);
4343 return Dis->DecodeVGPR_32RegisterClass(Inst, Imm, Addr);
4444 }
4545
4646 static DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
4747 uint64_t Addr, const void *Decoder) {
48 const AMDGPUDisassembler *Dis =
48 const AMDGPUDisassembler *Dis =
4949 static_cast(Decoder);
5050 return Dis->DecodeVS_32RegisterClass(Inst, Imm, Addr);
5151 }
5252
53 static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
53 static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
5454 uint64_t Addr, const void *Decoder) {
55 // ToDo
56 return MCDisassembler::Fail;
57 }
58
59 static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
55 const AMDGPUDisassembler *Dis =
56 static_cast(Decoder);
57 return Dis->DecodeVS_64RegisterClass(Inst, Imm, Addr);
58 }
59
60 static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
6061 uint64_t Addr, const void *Decoder) {
61 // ToDo
62 return MCDisassembler::Fail;
63 }
64
65 static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm,
62 const AMDGPUDisassembler *Dis =
63 static_cast(Decoder);
64 return Dis->DecodeVReg_64RegisterClass(Inst, Imm, Addr);
65 }
66
67 static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm,
6668 uint64_t Addr, const void *Decoder) {
6769 // ToDo
6870 return MCDisassembler::Fail;
6971 }
7072
71 static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned Imm,
73 static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned Imm,
7274 uint64_t Addr, const void *Decoder) {
7375 // ToDo
7476 return MCDisassembler::Fail;
7577 }
7678
77 static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm,
79 static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm,
7880 uint64_t Addr, const void *Decoder) {
7981 // ToDo
8082 return MCDisassembler::Fail;
8183 }
8284
83 static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm,
85 static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm,
8486 uint64_t Addr, const void *Decoder) {
8587 // ToDo
8688 return MCDisassembler::Fail;
8789 }
8890
89 static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned Imm,
91 static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned Imm,
9092 uint64_t Addr, const void *Decoder) {
9193 // ToDo
9294 return MCDisassembler::Fail;
9395 }
9496
95 static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm,
97 static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm,
9698 uint64_t Addr, const void *Decoder) {
9799 // ToDo
98100 return MCDisassembler::Fail;
99101 }
100
101102
102103 #define GET_SUBTARGETINFO_ENUM
103104 #include "AMDGPUGenSubtargetInfo.inc"
111112
112113 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
113114 ArrayRef Bytes,
114 uint64_t Address,
115 uint64_t Address,
115116 raw_ostream &WS,
116117 raw_ostream &CS) const {
117118 CommentStream = &CS;
118119
119120 // ToDo: AMDGPUDisassembler supports only VI ISA.
120121 assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
122
123 HasLiteral = false;
124 this->Bytes = Bytes;
121125
122126 // Try decode 32-bit instruction
123127 if (Bytes.size() < 4) {
134138 Size = 0;
135139 return MCDisassembler::Fail;
136140 }
137 Size = 4;
141 if (HasLiteral == true) {
142 Size = 8;
143 HasLiteral = false;
144 } else {
145 Size = 4;
146 }
138147
139148 return MCDisassembler::Success;
140149 }
141150
142 DecodeStatus AMDGPUDisassembler::DecodeLitFloat(unsigned Imm, uint32_t& F) const {
151 DecodeStatus AMDGPUDisassembler::DecodeImmedFloat(unsigned Imm, uint32_t &F) const {
143152 // ToDo: case 248: 1/(2*PI) - is allowed only on VI
144 // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
153 // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
145154 // literal constant.
146155 switch(Imm) {
147156 case 240: F = FloatToBits(0.5f); return MCDisassembler::Success;
157166 }
158167 }
159168
160 DecodeStatus AMDGPUDisassembler::DecodeLitInteger(unsigned Imm,
161 int64_t& I) const {
169 DecodeStatus AMDGPUDisassembler::DecodeImmedDouble(unsigned Imm, uint64_t &D) const {
170 switch(Imm) {
171 case 240: D = DoubleToBits(0.5); return MCDisassembler::Success;
172 case 241: D = DoubleToBits(-0.5); return MCDisassembler::Success;
173 case 242: D = DoubleToBits(1.0); return MCDisassembler::Success;
174 case 243: D = DoubleToBits(-1.0); return MCDisassembler::Success;
175 case 244: D = DoubleToBits(2.0); return MCDisassembler::Success;
176 case 245: D = DoubleToBits(-2.0); return MCDisassembler::Success;
177 case 246: D = DoubleToBits(4.0); return MCDisassembler::Success;
178 case 247: D = DoubleToBits(-4.0); return MCDisassembler::Success;
179 case 248: D = 0x3fc45f306dc9c882; return MCDisassembler::Success; // 1/(2*PI)
180 default: return MCDisassembler::Fail;
181 }
182 }
183
184 DecodeStatus AMDGPUDisassembler::DecodeImmedInteger(unsigned Imm,
185 int64_t &I) const {
162186 if ((Imm >= 128) && (Imm <= 192)) {
163187 I = Imm - 128;
164188 return MCDisassembler::Success;
169193 return MCDisassembler::Fail;
170194 }
171195
172 DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,
173 unsigned& RegID) const {
174 if (Val > 255) {
175 return MCDisassembler::Fail;
176 }
177 RegID = AMDGPUMCRegisterClasses[AMDGPU::VGPR_32RegClassID].getRegister(Val);
196 DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,
197 unsigned &RegID,
198 unsigned Size) const {
199 if (Val > (256 - Size / 32)) {
200 return MCDisassembler::Fail;
201 }
202 unsigned RegClassID;
203 switch (Size) {
204 case 32: RegClassID = AMDGPU::VGPR_32RegClassID; break;
205 case 64: RegClassID = AMDGPU::VReg_64RegClassID; break;
206 case 96: RegClassID = AMDGPU::VReg_96RegClassID; break;
207 case 128: RegClassID = AMDGPU::VReg_128RegClassID; break;
208 case 256: RegClassID = AMDGPU::VReg_256RegClassID; break;
209 case 512: RegClassID = AMDGPU::VReg_512RegClassID; break;
210 default:
211 return MCDisassembler::Fail;
212 }
213
214 RegID = AMDGPUMCRegisterClasses[RegClassID].getRegister(Val);
178215 return MCDisassembler::Success;
179216 }
180217
181 DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val,
182 unsigned& RegID) const {
218 DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val,
219 unsigned &RegID,
220 unsigned Size) const {
183221 // ToDo: SI/CI have 104 SGPRs, VI - 102
184 if (Val > 101) {
185 return MCDisassembler::Fail;
186 }
187 RegID = AMDGPUMCRegisterClasses[AMDGPU::SGPR_32RegClassID].getRegister(Val);
222 unsigned RegClassID;
223
224 switch (Size) {
225 case 32:
226 if (Val > 101) {
227 return MCDisassembler::Fail;
228 }
229 RegClassID = AMDGPU::SGPR_32RegClassID;
230 break;
231 case 64:
232 if ((Val % 2 != 0) || (Val > 100)) {
233 return MCDisassembler::Fail;
234 }
235 Val /= 2;
236 RegClassID = AMDGPU::SGPR_64RegClassID;
237 break;
238 case 128:
239 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
240 // this bundle?
241 if ((Val % 4 != 0) || (Val > 96)) {
242 return MCDisassembler::Fail;
243 }
244 Val /= 4;
245 RegClassID = AMDGPU::SReg_128RegClassID;
246 break;
247 case 256:
248 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
249 // this bundle?
250 if ((Val % 4 != 0) || (Val > 92)) {
251 return MCDisassembler::Fail;
252 }
253 Val /= 4;
254 RegClassID = AMDGPU::SReg_256RegClassID;
255 break;
256 case 512:
257 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
258 // this bundle?
259 if ((Val % 4 != 0) || (Val > 84)) {
260 return MCDisassembler::Fail;
261 }
262 Val /= 4;
263 RegClassID = AMDGPU::SReg_512RegClassID;
264 break;
265 default:
266 return MCDisassembler::Fail;
267 }
268
269 RegID = AMDGPUMCRegisterClasses[RegClassID].getRegister(Val);
188270 return MCDisassembler::Success;
189271 }
190272
191 DecodeStatus AMDGPUDisassembler::DecodeSrcRegister(unsigned Val,
192 unsigned& RegID) const {
193 // ToDo: deal with out-of range registers
273 DecodeStatus AMDGPUDisassembler::DecodeSrc32Register(unsigned Val,
274 unsigned &RegID) const {
275 // ToDo: deal with out-of range registers
194276 using namespace AMDGPU;
195277 if (Val <= 101) {
196 return DecodeSgprRegister(Val, RegID);
278 return DecodeSgprRegister(Val, RegID, 32);
197279 } else if ((Val >= 256) && (Val <= 511)) {
198 return DecodeVgprRegister(Val - 256, RegID);
280 return DecodeVgprRegister(Val - 256, RegID, 32);
199281 } else {
200282 switch(Val) {
201283 case 102: RegID = getMCReg(FLAT_SCR_LO, STI); return MCDisassembler::Success;
238320 return MCDisassembler::Fail;
239321 }
240322
241 DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,
242 unsigned Imm,
323 DecodeStatus AMDGPUDisassembler::DecodeSrc64Register(unsigned Val,
324 unsigned &RegID) const {
325 // ToDo: deal with out-of range registers
326 using namespace AMDGPU;
327 if (Val <= 101) {
328 return DecodeSgprRegister(Val, RegID, 64);
329 } else if ((Val >= 256) && (Val <= 511)) {
330 return DecodeVgprRegister(Val - 256, RegID, 64);
331 } else {
332 switch(Val) {
333 case 102: RegID = getMCReg(FLAT_SCR, STI); return MCDisassembler::Success;
334 case 106: RegID = getMCReg(VCC, STI); return MCDisassembler::Success;
335 case 126: RegID = getMCReg(EXEC, STI); return MCDisassembler::Success;
336 default: return MCDisassembler::Fail;
337 }
338 }
339 return MCDisassembler::Fail;
340 }
341
342 DecodeStatus AMDGPUDisassembler::DecodeLiteralConstant(MCInst &Inst,
343 uint64_t &Literal) const {
344 // For now all literal constants are supposed to be unsigned integer
345 // ToDo: deal with signed/unsigned 64-bit integer constants
346 // ToDo: deal with float/double constants
347 if (Bytes.size() < 8) {
348 return MCDisassembler::Fail;
349 }
350 Literal =
351 0 | (Bytes[7] << 24) | (Bytes[6] << 16) | (Bytes[5] << 8) | (Bytes[4] << 0);
352 return MCDisassembler::Success;
353 }
354
355 DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst,
356 unsigned Imm,
243357 uint64_t Addr) const {
244358 unsigned RegID;
245359 if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {
249363 return MCDisassembler::Fail;
250364 }
251365
252 DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
253 unsigned Imm,
254 uint64_t Addr) const {
255 // ToDo: different opcodes allow different formats og this operands
366 DecodeStatus AMDGPUDisassembler::DecodeVSRegisterClass(MCInst &Inst,
367 unsigned Imm,
368 uint64_t Addr,
369 bool Is32) const {
370 // ToDo: different opcodes allow different formats of this operands
256371 if ((Imm >= 128) && (Imm <= 208)) {
257372 // immediate integer
258373 int64_t Val;
259 if (DecodeLitInteger(Imm, Val) == MCDisassembler::Success) {
374 if (DecodeImmedInteger(Imm, Val) == MCDisassembler::Success) {
260375 Inst.addOperand(MCOperand::createImm(Val));
261376 return MCDisassembler::Success;
262377 }
263378 } else if ((Imm >= 240) && (Imm <= 248)) {
264 // immediate float
265 uint32_t Val;
266 if (DecodeLitFloat(Imm, Val) == MCDisassembler::Success) {
379 // immediate float/double
380 uint64_t Val;
381 DecodeStatus status;
382 if (Is32) {
383 uint32_t Val32;
384 status = DecodeImmedFloat(Imm, Val32);
385 Val = static_cast(Val32);
386 } else {
387 status = DecodeImmedDouble(Imm, Val);
388 }
389 if (status == MCDisassembler::Success) {
267390 Inst.addOperand(MCOperand::createImm(Val));
268391 return MCDisassembler::Success;
269392 }
272395 // ToDo: implement LDS direct read
273396 } else if (Imm == 255) {
274397 // literal constant
275 } else if ((Imm == 125) ||
276 ((Imm >= 209) && (Imm <= 239)) ||
277 (Imm == 249) ||
278 (Imm == 250) ||
398 HasLiteral = true;
399 uint64_t Literal;
400 if (DecodeLiteralConstant(Inst, Literal) == MCDisassembler::Success) {
401 Inst.addOperand(MCOperand::createImm(Literal));
402 return MCDisassembler::Success;
403 }
404 return MCDisassembler::Fail;
405 } else if ((Imm == 125) ||
406 ((Imm >= 209) && (Imm <= 239)) ||
407 (Imm == 249) ||
408 (Imm == 250) ||
279409 (Imm >= 512)) {
280410 // reserved
281411 return MCDisassembler::Fail;
282412 } else {
283413 // register
284414 unsigned RegID;
285 if (DecodeSrcRegister(Imm, RegID) == MCDisassembler::Success) {
415 DecodeStatus status = Is32 ? DecodeSrc32Register(Imm, RegID)
416 : DecodeSrc64Register(Imm, RegID);
417 if (status == MCDisassembler::Success) {
286418 Inst.addOperand(MCOperand::createReg(RegID));
287419 return MCDisassembler::Success;
288420 }
289421 }
290422 return MCDisassembler::Fail;
291423 }
424
425 DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst,
426 unsigned Imm,
427 uint64_t Addr) const {
428 return DecodeVSRegisterClass(Inst, Imm, Addr, true);
429 }
430
431 DecodeStatus AMDGPUDisassembler::DecodeVS_64RegisterClass(MCInst &Inst,
432 unsigned Imm,
433 uint64_t Addr) const {
434 return DecodeVSRegisterClass(Inst, Imm, Addr, false);
435 }
436
437 DecodeStatus AMDGPUDisassembler::DecodeVReg_64RegisterClass(llvm::MCInst &Inst,
438 unsigned Imm,
439 uint64_t Addr) const {
440 unsigned RegID;
441 if (DecodeVgprRegister(Imm, RegID, 64) == MCDisassembler::Success) {
442 Inst.addOperand(MCOperand::createReg(RegID));
443 return MCDisassembler::Success;
444 }
445 return MCDisassembler::Fail;
446 }
447
448
292449
293450 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
294451 const MCSubtargetInfo &STI,
2424 class MCSubtargetInfo;
2525
2626 class AMDGPUDisassembler : public MCDisassembler {
27 private:
28 /// true if 32-bit literal constant is placed after instruction
29 mutable bool HasLiteral;
30 mutable ArrayRef Bytes;
31
2732 public:
2833 AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
29 MCDisassembler(STI, Ctx) {}
34 MCDisassembler(STI, Ctx), HasLiteral(false) {}
3035
3136 ~AMDGPUDisassembler() {}
3237
3439 ArrayRef Bytes, uint64_t Address,
3540 raw_ostream &WS, raw_ostream &CS) const override;
3641
37 /// Decode inline float value in VSrc field
38 DecodeStatus DecodeLitFloat(unsigned Imm, uint32_t& F) const;
39 /// Decode inline integer value in VSrc field
40 DecodeStatus DecodeLitInteger(unsigned Imm, int64_t& I) const;
42 /// Decode inline float value in SRC field
43 DecodeStatus DecodeImmedFloat(unsigned Imm, uint32_t &F) const;
44 /// Decode inline double value in SRC field
45 DecodeStatus DecodeImmedDouble(unsigned Imm, uint64_t &D) const;
46 /// Decode inline integer value in SRC field
47 DecodeStatus DecodeImmedInteger(unsigned Imm, int64_t &I) const;
4148 /// Decode VGPR register
42 DecodeStatus DecodeVgprRegister(unsigned Val, unsigned& RegID) const;
49 DecodeStatus DecodeVgprRegister(unsigned Val, unsigned &RegID,
50 unsigned Size = 32) const;
4351 /// Decode SGPR register
44 DecodeStatus DecodeSgprRegister(unsigned Val, unsigned& RegID) const;
45 /// Decode register in VSrc field
46 DecodeStatus DecodeSrcRegister(unsigned Val, unsigned& RegID) const;
52 DecodeStatus DecodeSgprRegister(unsigned Val, unsigned &RegID,
53 unsigned Size = 32) const;
54 /// Decode 32-bit register in SRC field
55 DecodeStatus DecodeSrc32Register(unsigned Val, unsigned &RegID) const;
56 /// Decode 64-bit register in SRC field
57 DecodeStatus DecodeSrc64Register(unsigned Val, unsigned &RegID) const;
4758
48 DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
59 /// Decode literal constant after instruction
60 DecodeStatus DecodeLiteralConstant(MCInst &Inst, uint64_t &Literal) const;
61
62 DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
63 uint64_t Addr) const;
64
65 DecodeStatus DecodeVSRegisterClass(MCInst &Inst, unsigned Imm,
66 uint64_t Addr, bool Is32) const;
67
68 DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
4969 uint64_t Addr) const;
5070
51 DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
71 DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm,
72 uint64_t Addr) const;
73
74 DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm,
5275 uint64_t Addr) const;
5376 };
5477 } // namespace llvm
5578
56 #endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
79 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16651665 }
16661666
16671667 class VOP3_C_Real_vi op, dag outs, dag ins, string asm, string opName,
1668 bit HasMods = 0, bit VOP3Only = 0> :
1668 bit HasMods = 0, bit VOP3Only = 0> :
16691669 VOP3Common ,
16701670 VOP3ce_vi ,
16711671 SIMCInstr {
0 # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s
1
2 # CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
3 0x00 0x00 0x00 0x7e
4
5 # CHECK: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
6 0x00 0x6a 0x00 0x7e
7
8 # CHECK: v_mov_b32_e32 v2, v1 ; encoding: [0x01,0x03,0x04,0x7e]
9 0x01 0x03 0x04 0x7e
10
11 # CHECK: v_mov_b32_e32 v1, 0.5 ; encoding: [0xf0,0x02,0x02,0x7e]
12 0xf0 0x02 0x02 0x7e
13
14 # CHECK: v_mov_b32_e32 v15, s100 ; encoding: [0x64,0x02,0x1e,0x7e]
15 0x64 0x02 0x1e 0x7e
16
17 # CHECK: v_mov_b32_e32 v90, flat_scratch_lo ; encoding: [0x66,0x02,0xb4,0x7e]
18 0x66 0x02 0xb4 0x7e
19
20 # CHECK: v_mov_b32_e32 v150, vcc_lo ; encoding: [0x6a,0x02,0x2c,0x7f]
21 0x6a 0x02 0x2c 0x7f
22
23 # CHECK: v_mov_b32_e32 v199, exec_lo ; encoding: [0x7e,0x02,0x8e,0x7f]
24 0x7e 0x02 0x8e 0x7f
25
26 # CHECK: v_mov_b32_e32 v222, m0 ; encoding: [0x7c,0x02,0xbc,0x7f]
27 0x7c 0x02 0xbc 0x7f
28
29 # CHECK: v_mov_b32_e32 v255, -13 ; encoding: [0xcd,0x02,0xfe,0x7f]
30 0xcd 0x02 0xfe 0x7f
31
32 # CHECK: v_cvt_f32_i32_e32 v153, s98 ; encoding: [0x62,0x0a,0x32,0x7f]
33 0x62 0x0a 0x32 0x7f
34
35 # CHECK: v_cvt_f32_u32_e32 v33, -4.0 ; encoding: [0xf7,0x0c,0x42,0x7e]
36 0xf7 0x0c 0x42 0x7e
37
38 # CHECK: v_cvt_i32_f64_e32 v2, s[0:1] ; encoding: [0x00,0x06,0x04,0x7e]
39 0x00 0x06 0x04 0x7e
40
41 # CHECK: v_cvt_u32_f32_e32 v123, vcc_hi ; encoding: [0x6b,0x0e,0xf6,0x7e]
42 0x6b 0x0e 0xf6 0x7e
43
44 # CHECK: v_cvt_i32_f32_e32 v123, flat_scratch_lo ; encoding: [0x66,0x10,0xf6,0x7e]
45 0x66 0x10 0xf6 0x7e
46
47 # CHECK: v_cvt_rpi_i32_f32_e32 v123, s101 ; encoding: [0x65,0x18,0xf6,0x7e]
48 0x65 0x18 0xf6 0x7e
49
50 # CHECK: v_cvt_flr_i32_f32_e32 v123, -4.0 ; encoding: [0xf7,0x1a,0xf6,0x7e]
51 0xf7 0x1a 0xf6 0x7e
52
53 # CHECK: v_cvt_f32_f64_e32 v123, vcc ; encoding: [0x6a,0x1e,0xf6,0x7e]
54 0x6a 0x1e 0xf6 0x7e
55
56 # CHECK: v_cvt_u32_f64_e32 v123, exec ; encoding: [0x7e,0x2a,0xf6,0x7e]
57 0x7e 0x2a 0xf6 0x7e
58
59 # CHECK: v_fract_f32_e32 v123, m0 ; encoding: [0x7c,0x36,0xf6,0x7e]
60 0x7c 0x36 0xf6 0x7e
61
62 # CHECK: v_trunc_f32_e32 v123, exec_lo ; encoding: [0x7e,0x38,0xf6,0x7e]
63 0x7e 0x38 0xf6 0x7e
64
65 # CHECK: v_ceil_f32_e32 v123, exec_hi ; encoding: [0x7f,0x3a,0xf6,0x7e]
66 0x7f 0x3a 0xf6 0x7e
67
68 # CHECK: v_rndne_f32_e32 v123, 0 ; encoding: [0x80,0x3c,0xf6,0x7e]
69 0x80 0x3c 0xf6 0x7e
70
71 # CHECK: v_floor_f32_e32 v123, -0.5 ; encoding: [0xf1,0x3e,0xf6,0x7e]
72 0xf1 0x3e 0xf6 0x7e
73
74 # CHECK: v_exp_f32_e32 v123, 1.0 ; encoding: [0xf2,0x40,0xf6,0x7e]
75 0xf2 0x40 0xf6 0x7e
76
77 # CHECK: v_log_f32_e32 v123, -1.0 ; encoding: [0xf3,0x42,0xf6,0x7e]
78 0xf3 0x42 0xf6 0x7e
79
80 # CHECK: v_rcp_f32_e32 v123, 2.0 ; encoding: [0xf4,0x44,0xf6,0x7e]
81 0xf4 0x44 0xf6 0x7e
82
83 # CHECK: v_rcp_iflag_f32_e32 v123, -2.0 ; encoding: [0xf5,0x46,0xf6,0x7e]
84 0xf5 0x46 0xf6 0x7e
85
86 # CHECK: v_rsq_f32_e32 v123, 4.0 ; encoding: [0xf6,0x48,0xf6,0x7e]
87 0xf6 0x48 0xf6 0x7e
88
89 # CHECK: v_sqrt_f32_e32 v123, v12 ; encoding: [0x0c,0x4f,0xf6,0x7e]
90 0x0c 0x4f 0xf6 0x7e
91
92 # CHECK: v_sin_f32_e32 v123, v12 ; encoding: [0x0c,0x53,0xf6,0x7e]
93 0x0c 0x53 0xf6 0x7e
94
95 # CHECK: v_cos_f32_e32 v123, v12 ; encoding: [0x0c,0x55,0xf6,0x7e]
96 0x0c 0x55 0xf6 0x7e
97
98 # CHECK: v_not_b32_e32 v123, v12 ; encoding: [0x0c,0x57,0xf6,0x7e]
99 0x0c 0x57 0xf6 0x7e
100
101 # CHECK: v_bfrev_b32_e32 v123, v12 ; encoding: [0x0c,0x59,0xf6,0x7e]
102 0x0c 0x59 0xf6 0x7e
103
104 # CHECK: v_ffbh_u32_e32 v123, v12 ; encoding: [0x0c,0x5b,0xf6,0x7e]
105 0x0c 0x5b 0xf6 0x7e
106
107 # CHECK: v_ffbl_b32_e32 v123, v12 ; encoding: [0x0c,0x5d,0xf6,0x7e]
108 0x0c 0x5d 0xf6 0x7e
109
110 # CHECK: v_ffbh_i32_e32 v123, v12 ; encoding: [0x0c,0x5f,0xf6,0x7e]
111 0x0c 0x5f 0xf6 0x7e
112
113 # CHECK: v_frexp_exp_i32_f64_e32 v123, 2.0 ; encoding: [0xf4,0x60,0xf6,0x7e]
114 0xf4 0x60 0xf6 0x7e
115
116 # CHECK: v_frexp_exp_i32_f32_e32 v123, s33 ; encoding: [0x21,0x66,0xf6,0x7e]
117 0x21 0x66 0xf6 0x7e
118
119 # CHECK: v_frexp_mant_f32_e32 v123, s33 ; encoding: [0x21,0x68,0xf6,0x7e]
120 0x21 0x68 0xf6 0x7e
121
122 # CHECK: v_movreld_b32_e32 v123, s33 ; encoding: [0x21,0x6c,0xf6,0x7e]
123 0x21 0x6c 0xf6 0x7e
124
125 # CHECK: v_movrels_b32_e32 v123, s33 ; encoding: [0x21,0x6e,0xf6,0x7e]
126 0x21 0x6e 0xf6 0x7e
127
128 # CHECK: v_movrelsd_b32_e32 v123, s33 ; encoding: [0x21,0x70,0xf6,0x7e]
129 0x21 0x70 0xf6 0x7e
130
131 # CHECK: v_cvt_f16_f32_e32 v123, flat_scratch_hi ; encoding: [0x67,0x14,0xf6,0x7e]
132 0x67 0x14 0xf6 0x7e
133
134 # CHECK: v_cvt_f32_f16_e32 v123, s55 ; encoding: [0x37,0x16,0xf6,0x7e]
135 0x37 0x16 0xf6 0x7e
136
137 # CHECK: v_cvt_off_f32_i4_e32 v123, v12 ; encoding: [0x0c,0x1d,0xf6,0x7e]
138 0x0c 0x1d 0xf6 0x7e
139
140 # CHECK: v_cvt_f32_ubyte0_e32 v123, v12 ; encoding: [0x0c,0x23,0xf6,0x7e]
141 0x0c 0x23 0xf6 0x7e
142
143 # CHECK: v_cvt_f32_ubyte1_e32 v123, v12 ; encoding: [0x0c,0x25,0xf6,0x7e]
144 0x0c 0x25 0xf6 0x7e
145
146 # CHECK: v_cvt_f32_ubyte2_e32 v123, v12 ; encoding: [0x0c,0x27,0xf6,0x7e]
147 0x0c 0x27 0xf6 0x7e
148
149 # CHECK: v_cvt_f32_ubyte3_e32 v123, v12 ; encoding: [0x0c,0x29,0xf6,0x7e]
150 0x0c 0x29 0xf6 0x7e
151
152 # CHECK: v_cvt_f64_i32_e32 v[222:223], 1.0 ; encoding: [0xf2,0x08,0xbc,0x7f]
153 0xf2 0x08 0xbc 0x7f
154
155 # CHECK: v_cvt_f64_i32_e32 v[222:223], exec_hi ; encoding: [0x7f,0x08,0xbc,0x7f]
156 0x7f 0x08 0xbc 0x7f
157
158 # CHECK: v_cvt_f64_f32_e32 v[222:223], s33 ; encoding: [0x21,0x20,0xbc,0x7f]
159 0x21 0x20 0xbc 0x7f
160
161 # CHECK: v_cvt_f64_u32_e32 v[222:223], s33 ; encoding: [0x21,0x2c,0xbc,0x7f]
162 0x21 0x2c 0xbc 0x7f
163
164 # CHECK: v_rcp_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x4a,0xbc,0x7f]
165 0x16 0x4a 0xbc 0x7f
166
167 # CHECK: v_rsq_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x4c,0xbc,0x7f]
168 0x16 0x4c 0xbc 0x7f
169
170 # CHECK: v_sqrt_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x50,0xbc,0x7f]
171 0x16 0x50 0xbc 0x7f
172
173 # CHECK: v_frexp_mant_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x62,0xbc,0x7f]
174 0x16 0x62 0xbc 0x7f
175
176 # CHECK: v_fract_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x64,0xbc,0x7f]
177 0x16 0x64 0xbc 0x7f
178
179 # CHECK: v_cvt_f16_u16_e32 v123, 23 ; encoding: [0x97,0x72,0xf6,0x7e]
180 0x97 0x72 0xf6 0x7e
181
182 # CHECK: v_cvt_f16_i16_e32 v123, vcc_hi ; encoding: [0x6b,0x74,0xf6,0x7e]
183 0x6b 0x74 0xf6 0x7e
184
185 # CHECK: v_cvt_u16_f16_e32 v123, m0 ; encoding: [0x7c,0x76,0xf6,0x7e]
186 0x7c 0x76 0xf6 0x7e
187
188 # CHECK: v_cvt_i16_f16_e32 v123, exec_lo ; encoding: [0x7e,0x78,0xf6,0x7e]
189 0x7e 0x78 0xf6 0x7e
190
191 # CHECK: v_rcp_f16_e32 v123, 1.0 ; encoding: [0xf2,0x7a,0xf6,0x7e]
192 0xf2 0x7a 0xf6 0x7e
193
194 # CHECK: v_sqrt_f16_e32 v123, 4.0 ; encoding: [0xf6,0x7c,0xf6,0x7e]
195 0xf6 0x7c 0xf6 0x7e
196
197 # CHECK: v_rsq_f16_e32 v123, -1.0 ; encoding: [0xf3,0x7e,0xf6,0x7e]
198 0xf3 0x7e 0xf6 0x7e
199
200 # CHECK: v_log_f16_e32 v123, s33 ; encoding: [0x21,0x80,0xf6,0x7e]
201 0x21 0x80 0xf6 0x7e
202
203 # CHECK: v_exp_f16_e32 v123, v12 ; encoding: [0x0c,0x83,0xf6,0x7e]
204 0x0c 0x83 0xf6 0x7e
205
206 # CHECK: v_frexp_mant_f16_e32 v123, v12 ; encoding: [0x0c,0x85,0xf6,0x7e]
207 0x0c 0x85 0xf6 0x7e
208
209 # CHECK: v_frexp_exp_i16_f16_e32 v123, v12 ; encoding: [0x0c,0x87,0xf6,0x7e]
210 0x0c 0x87 0xf6 0x7e
211
212 # CHECK: v_floor_f16_e32 v123, v12 ; encoding: [0x0c,0x89,0xf6,0x7e]
213 0x0c 0x89 0xf6 0x7e
214
215 # CHECK: v_ceil_f16_e32 v123, v12 ; encoding: [0x0c,0x8b,0xf6,0x7e]
216 0x0c 0x8b 0xf6 0x7e
217
218 # CHECK: v_trunc_f16_e32 v123, s33 ; encoding: [0x21,0x8c,0xf6,0x7e]
219 0x21 0x8c 0xf6 0x7e
220
221 # CHECK: v_rndne_f16_e32 v123, s33 ; encoding: [0x21,0x8e,0xf6,0x7e]
222 0x21 0x8e 0xf6 0x7e
223
224 # CHECK: v_fract_f16_e32 v123, s33 ; encoding: [0x21,0x90,0xf6,0x7e]
225 0x21 0x90 0xf6 0x7e
226
227 # CHECK: v_sin_f16_e32 v123, s33 ; encoding: [0x21,0x92,0xf6,0x7e]
228 0x21 0x92 0xf6 0x7e
229
230 # CHECK: v_cos_f16_e32 v123, s33 ; encoding: [0x21,0x94,0xf6,0x7e]
231 0x21 0x94 0xf6 0x7e
232
233 # CHECK: v_mov_b32_e32 v2, 0x75bcd15 ; encoding: [0xff,0x02,0x04,0x7e,0x15,0xcd,0x5b,0x07]
234 0xff 0x02 0x04 0x7e 0x15 0xcd 0x5b 0x07
235
236 # CHECK: v_cvt_f32_u32_e32 v33, 0x4236b732 ; encoding: [0xff,0x0c,0x42,0x7e,0x32,0xb7,0x36,0x42]
237 0xff 0x0c 0x42 0x7e 0x32 0xb7 0x36 0x42
238
239 # CHECK: v_cvt_i32_f64_e32 v2, 0x4236b732 ; encoding: [0xff,0x06,0x04,0x7e,0x32,0xb7,0x36,0x42]
240 0xff 0x06 0x04 0x7e 0x32 0xb7 0x36 0x42
241
242 # CHECK: v_cvt_f16_u16_e32 v123, 0x3ade68b1 ; encoding: [0xff,0x72,0xf6,0x7e,0xb1,0x68,0xde,0x3a]
243 0xff 0x72 0xf6 0x7e 0xb1 0x68 0xde 0x3a
244
245 # CHECK: v_cvt_f16_i16_e32 v123, 0x21c2 ; encoding: [0xff,0x74,0xf6,0x7e,0xc2,0x21,0x00,0x00]
246 0xff 0x74 0xf6 0x7e 0xc2 0x21 0x00 0x00
247
248 # CHECK: v_cvt_u16_f16_e32 v123, 0x3f200000 ; encoding: [0xff,0x76,0xf6,0x7e,0x00,0x00,0x20,0x3f]
249 0xff 0x76 0xf6 0x7e 0x00 0x00 0x20 0x3f