llvm.org GIT mirror llvm / acad68d
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8 James Molloy 8 years ago
11 changed file(s) with 216 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
9393 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
9494 "Supports Multiprocessing extension">;
9595
96 // M-series ISA?
97 def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
98 "Is microcontroller profile ('M' series)">;
99
96100 // ARM ISAs.
97101 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
98102 "Support ARM v4T instructions">;
184188
185189 // V6M Processors.
186190 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
187 FeatureDB]>;
191 FeatureDB, FeatureMClass]>;
188192
189193 // V6T2 Processors.
190194 def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
207211 // V7M Processors.
208212 def : ProcNoItin<"cortex-m3", [HasV7Ops,
209213 FeatureThumb2, FeatureNoARM, FeatureDB,
210 FeatureHWDiv]>;
214 FeatureHWDiv, FeatureMClass]>;
211215
212216 // V7EM Processors.
213217 def : ProcNoItin<"cortex-m4", [HasV7Ops,
214218 FeatureThumb2, FeatureNoARM, FeatureDB,
215219 FeatureHWDiv, FeatureDSPThumb2,
216220 FeatureT2XtPk, FeatureVFP2,
217 FeatureVFPOnlySP]>;
221 FeatureVFPOnlySP, FeatureMClass]>;
218222
219223 //===----------------------------------------------------------------------===//
220224 // Register File Description
204204 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
205205 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
206206 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
207 def IsMClass : Predicate<"Subtarget->isMClass()">,
208 AssemblerPredicate<"FeatureMClass">;
209 def IsARClass : Predicate<"!Subtarget->isMClass()">,
210 AssemblerPredicate<"!FeatureMClass">;
207211 def IsARM : Predicate<"!Subtarget->isThumb()">,
208212 AssemblerPredicate<"!ModeThumb">;
209213 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
35393539 // Move between special register and ARM core register -- for disassembly only
35403540 //
35413541 // Move to ARM core register from Special Register
3542 def t2MRS : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []> {
3542
3543 // A/R class MRS.
3544 //
3545 // A/R class can only move from CPSR or SPSR.
3546 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>,
3547 Requires<[IsThumb2,IsARClass]> {
35433548 bits<4> Rd;
35443549 let Inst{31-12} = 0b11110011111011111000;
35453550 let Inst{11-8} = Rd;
35463551 let Inst{7-0} = 0b0000;
35473552 }
35483553
3549 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS GPR:$Rd, pred:$p)>;
3550
3551 def t2MRSsys:T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []> {
3554 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
3555
3556 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>,
3557 Requires<[IsThumb2,IsARClass]> {
35523558 bits<4> Rd;
35533559 let Inst{31-12} = 0b11110011111111111000;
35543560 let Inst{11-8} = Rd;
35553561 let Inst{7-0} = 0b0000;
35563562 }
35573563
3564 // M class MRS.
3565 //
3566 // This MRS has a mask field in bits 7-0 and can take more values than
3567 // the A/R class (a full msr_mask).
3568 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary,
3569 "mrs", "\t$Rd, $mask", []>,
3570 Requires<[IsThumb2,IsMClass]> {
3571 bits<4> Rd;
3572 bits<8> mask;
3573 let Inst{31-12} = 0b11110011111011111000;
3574 let Inst{11-8} = Rd;
3575 let Inst{19-16} = 0b1111;
3576 let Inst{7-0} = mask;
3577 }
3578
3579
35583580 // Move from ARM core register to Special Register
3581 //
3582 // A/R class MSR.
35593583 //
35603584 // No need to have both system and application versions, the encodings are the
35613585 // same and the assembly parser has no way to distinguish between them. The mask
35623586 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
35633587 // the mask with the fields to be accessed in the special register.
3564 def t2MSR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3565 NoItinerary, "msr", "\t$mask, $Rn", []> {
3588 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn),
3589 NoItinerary, "msr", "\t$mask, $Rn", []>,
3590 Requires<[IsThumb2,IsARClass]> {
35663591 bits<5> mask;
35673592 bits<4> Rn;
35683593 let Inst{31-21} = 0b11110011100;
35723597 let Inst{11-8} = mask{3-0};
35733598 let Inst{7-0} = 0;
35743599 }
3600
3601 // M class MSR.
3602 //
3603 // Move from ARM core register to Special Register
3604 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn),
3605 NoItinerary, "msr", "\t$SYSm, $Rn", []>,
3606 Requires<[IsThumb2,IsMClass]> {
3607 bits<8> SYSm;
3608 bits<4> Rn;
3609 let Inst{31-21} = 0b11110011100;
3610 let Inst{20} = 0b0;
3611 let Inst{19-16} = Rn;
3612 let Inst{15-12} = 0b1000;
3613 let Inst{7-0} = SYSm;
3614 }
3615
35753616
35763617 //===----------------------------------------------------------------------===//
35773618 // Move between coprocessor and ARM core register
5454 , InThumbMode(false)
5555 , InNaClMode(false)
5656 , HasThumb2(false)
57 , IsMClass(false)
5758 , NoARM(false)
5859 , PostRAScheduler(false)
5960 , IsR9Reserved(ReserveR9)
7474
7575 /// HasThumb2 - True if Thumb2 instructions are supported.
7676 bool HasThumb2;
77
78 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
79 /// v6m, v7m for example.
80 bool IsMClass;
7781
7882 /// NoARM - True if subtarget does not support ARM mode execution.
7983 bool NoARM;
223227 bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
224228 bool isThumb2() const { return InThumbMode && HasThumb2; }
225229 bool hasThumb2() const { return HasThumb2; }
230 bool isMClass() const { return IsMClass; }
231 bool isARClass() const { return !IsMClass; }
226232
227233 bool isR9Reserved() const { return IsR9Reserved; }
228234
113113 bool hasV6Ops() const {
114114 return STI.getFeatureBits() & ARM::HasV6Ops;
115115 }
116 bool hasV7Ops() const {
117 return STI.getFeatureBits() & ARM::HasV7Ops;
118 }
116119 void SwitchMode() {
117120 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
118121 setAvailableFeatures(FB);
122 }
123 bool isMClass() const {
124 return STI.getFeatureBits() & ARM::FeatureMClass;
119125 }
120126
121127 /// @name Auto-generated Match Functions
20742080 const AsmToken &Tok = Parser.getTok();
20752081 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
20762082 StringRef Mask = Tok.getString();
2083
2084 if (isMClass()) {
2085 // See ARMv6-M 10.1.1
2086 unsigned FlagsVal = StringSwitch(Mask)
2087 .Case("apsr", 0)
2088 .Case("iapsr", 1)
2089 .Case("eapsr", 2)
2090 .Case("xpsr", 3)
2091 .Case("ipsr", 5)
2092 .Case("epsr", 6)
2093 .Case("iepsr", 7)
2094 .Case("msp", 8)
2095 .Case("psp", 9)
2096 .Case("primask", 16)
2097 .Case("basepri", 17)
2098 .Case("basepri_max", 18)
2099 .Case("faultmask", 19)
2100 .Case("control", 20)
2101 .Default(~0U);
2102
2103 if (FlagsVal == ~0U)
2104 return MatchOperand_NoMatch;
2105
2106 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2107 // basepri, basepri_max and faultmask only valid for V7m.
2108 return MatchOperand_NoMatch;
2109
2110 Parser.Lex(); // Eat identifier token.
2111 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2112 return MatchOperand_Success;
2113 }
20772114
20782115 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
20792116 size_t Start = 0, Next = Mask.find('_');
619619 const MCOperand &Op = MI->getOperand(OpNum);
620620 unsigned SpecRegRBit = Op.getImm() >> 4;
621621 unsigned Mask = Op.getImm() & 0xf;
622
623 if (getAvailableFeatures() & ARM::FeatureMClass) {
624 switch (Op.getImm()) {
625 default: assert(0 && "Unexpected mask value!");
626 case 0: O << "apsr"; return;
627 case 1: O << "iapsr"; return;
628 case 2: O << "eapsr"; return;
629 case 3: O << "xpsr"; return;
630 case 5: O << "ipsr"; return;
631 case 6: O << "epsr"; return;
632 case 7: O << "iepsr"; return;
633 case 8: O << "msp"; return;
634 case 9: O << "psp"; return;
635 case 16: O << "primask"; return;
636 case 17: O << "basepri"; return;
637 case 18: O << "basepri_max"; return;
638 case 19: O << "faultmask"; return;
639 case 20: O << "control"; return;
640 }
641 }
622642
623643 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
624644 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
5555 unsigned SubVer = TT[Idx];
5656 if (SubVer >= '7' && SubVer <= '9') {
5757 if (Len >= Idx+2 && TT[Idx+1] == 'm') {
58 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv
59 ARMArchFeature = "+v7,+noarm,+db,+hwdiv";
58 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
59 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
6060 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
6161 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
62 // FeatureT2XtPk
63 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk";
62 // FeatureT2XtPk, FeatureMClass
63 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
6464 } else
6565 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
6666 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
6767 } else if (SubVer == '6') {
6868 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
6969 ARMArchFeature = "+v6t2";
70 else if (Len >= Idx+2 && TT[Idx+1] == 'm')
71 // v6m: FeatureNoARM, FeatureMClass
72 ARMArchFeature = "+v6t2,+noarm,+mclass";
7073 else
7174 ARMArchFeature = "+v6";
7275 } else if (SubVer == '5') {
0 @ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s
1 .syntax unified
2 .globl _func
3
4 @ Check that the assembler can handle the documented syntax from the ARM ARM.
5 @ These tests test instruction encodings specific to v7m & v7m (FeatureMClass).
6
7 @------------------------------------------------------------------------------
8 @ MRS
9 @------------------------------------------------------------------------------
10
11 mrs r0, apsr
12 mrs r0, iapsr
13 mrs r0, eapsr
14 mrs r0, xpsr
15 mrs r0, ipsr
16 mrs r0, epsr
17 mrs r0, iepsr
18 mrs r0, msp
19 mrs r0, psp
20 mrs r0, primask
21 mrs r0, basepri
22 mrs r0, basepri_max
23 mrs r0, faultmask
24 mrs r0, control
25
26 @ CHECK: mrs r0, apsr @ encoding: [0xef,0xf3,0x00,0x80]
27 @ CHECK: mrs r0, iapsr @ encoding: [0xef,0xf3,0x01,0x80]
28 @ CHECK: mrs r0, eapsr @ encoding: [0xef,0xf3,0x02,0x80]
29 @ CHECK: mrs r0, xpsr @ encoding: [0xef,0xf3,0x03,0x80]
30 @ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80]
31 @ CHECK: mrs r0, epsr @ encoding: [0xef,0xf3,0x06,0x80]
32 @ CHECK: mrs r0, iepsr @ encoding: [0xef,0xf3,0x07,0x80]
33 @ CHECK: mrs r0, msp @ encoding: [0xef,0xf3,0x08,0x80]
34 @ CHECK: mrs r0, psp @ encoding: [0xef,0xf3,0x09,0x80]
35 @ CHECK: mrs r0, primask @ encoding: [0xef,0xf3,0x10,0x80]
36 @ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80]
37 @ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80]
38 @ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80]
39 @ CHECK: mrs r0, control @ encoding: [0xef,0xf3,0x14,0x80]
40
41 @------------------------------------------------------------------------------
42 @ MSR
43 @------------------------------------------------------------------------------
44
45 msr apsr, r0
46 msr iapsr, r0
47 msr eapsr, r0
48 msr xpsr, r0
49 msr ipsr, r0
50 msr epsr, r0
51 msr iepsr, r0
52 msr msp, r0
53 msr psp, r0
54 msr primask, r0
55 msr basepri, r0
56 msr basepri_max, r0
57 msr faultmask, r0
58 msr control, r0
59
60 @ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x80]
61 @ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x80]
62 @ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x80]
63 @ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x80]
64 @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80]
65 @ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x80]
66 @ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x80]
67 @ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x80]
68 @ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x80]
69 @ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x80]
70 @ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x80]
71 @ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x80]
72 @ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x80]
73 @ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x80]
0 # RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 | FileCheck %s
1
2 # CHECK: msr primask, r0
3 0x80 0xf3 0x10 0x80
4
5 # CHECK: mrs r0, primask
6 0xef 0xf3 0x10 0x80
294294
295295 # CHECK: pldw [r11, r12, lsl #2]
296296 0x3b 0xf8 0x2c 0xf0
297
298 # CHECK: msr CPSR_fc, r0
299 0x80 0xf3 0x00 0x89
300
301 # CHECK: mrs r0, apsr
302 0xef 0xf3 0x00 0x80