llvm.org GIT mirror llvm / aca5793
[ARM] Add a batch of MVE floating-point instructions. Summary: This includes floating-point basic arithmetic (add/sub/multiply), complex add/multiply, unary negation and absolute value, rounding to integer value, and conversion to/from integer formats. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364013 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
5 changed file(s) with 1077 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
139139 ops, !strconcat(cstr, vpred.vpred_constraint), pattern> {
140140 let Inst{31-29} = 0b111;
141141 let Inst{27-26} = 0b11;
142 }
143
144 class MVE_f
145 string suffix, string ops, vpred_ops vpred, string cstr,
146 list pattern=[]>
147 : MVE_p {
148 let Predicates = [HasMVEFloat];
142149 }
143150
144151 class MVE_MI_with_pred
18921899
18931900 // end of MVE Integer instructions
18941901
1902 // start of MVE Floating Point instructions
1903
1904 class MVE_float
1905 vpred_ops vpred, string cstr, list pattern=[]>
1906 : MVE_f {
1907 bits<4> Qm;
1908
1909 let Inst{12} = 0b0;
1910 let Inst{6} = 0b1;
1911 let Inst{5} = Qm{3};
1912 let Inst{3-1} = Qm{2-0};
1913 let Inst{0} = 0b0;
1914 }
1915
1916 class MVE_VRINT op, string suffix, bits<2> size,
1917 list pattern=[]>
1918 : MVE_float
1919 (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
1920 bits<4> Qd;
1921
1922 let Inst{28} = 0b1;
1923 let Inst{25-23} = 0b111;
1924 let Inst{22} = Qd{3};
1925 let Inst{21-20} = 0b11;
1926 let Inst{19-18} = size;
1927 let Inst{17-16} = 0b10;
1928 let Inst{15-13} = Qd{2-0};
1929 let Inst{11-10} = 0b01;
1930 let Inst{9-7} = op{2-0};
1931 let Inst{4} = 0b0;
1932
1933 }
1934
1935 multiclass MVE_VRINT_ops size, list pattern=[]> {
1936 def N : MVE_VRINT<"n", 0b000, suffix, size, pattern>;
1937 def X : MVE_VRINT<"x", 0b001, suffix, size, pattern>;
1938 def A : MVE_VRINT<"a", 0b010, suffix, size, pattern>;
1939 def Z : MVE_VRINT<"z", 0b011, suffix, size, pattern>;
1940 def M : MVE_VRINT<"m", 0b101, suffix, size, pattern>;
1941 def P : MVE_VRINT<"p", 0b111, suffix, size, pattern>;
1942 }
1943
1944 defm MVE_VRINTf16 : MVE_VRINT_ops<"f16", 0b01>;
1945 defm MVE_VRINTf32 : MVE_VRINT_ops<"f32", 0b10>;
1946
1947 class MVEFloatArithNeon
1948 dag oops, dag iops, string ops,
1949 vpred_ops vpred, string cstr, list pattern=[]>
1950 : MVE_float {
1951 let Inst{20} = size;
1952 let Inst{16} = 0b0;
1953 }
1954
1955 class MVE_VMUL_fp pattern=[]>
1956 : MVEFloatArithNeon<"vmul", suffix, size, (outs MQPR:$Qd),
1957 (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm", vpred_r, "",
1958 pattern> {
1959 bits<4> Qd;
1960 bits<4> Qn;
1961
1962 let Inst{28} = 0b1;
1963 let Inst{25-23} = 0b110;
1964 let Inst{22} = Qd{3};
1965 let Inst{21} = 0b0;
1966 let Inst{19-17} = Qn{2-0};
1967 let Inst{15-13} = Qd{2-0};
1968 let Inst{12-8} = 0b01101;
1969 let Inst{7} = Qn{3};
1970 let Inst{4} = 0b1;
1971 }
1972
1973 def MVE_VMULf32 : MVE_VMUL_fp<"f32", 0b0>;
1974 def MVE_VMULf16 : MVE_VMUL_fp<"f16", 0b1>;
1975
1976 class MVE_VCMLA pattern=[]>
1977 : MVEFloatArithNeon<"vcmla", suffix, size, (outs MQPR:$Qd),
1978 (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
1979 "$Qd, $Qn, $Qm, $rot", vpred_n, "$Qd = $Qd_src", pattern> {
1980 bits<4> Qd;
1981 bits<4> Qn;
1982 bits<2> rot;
1983
1984 let Inst{28} = 0b1;
1985 let Inst{25} = 0b0;
1986 let Inst{24-23} = rot;
1987 let Inst{22} = Qd{3};
1988 let Inst{21} = 0b1;
1989 let Inst{19-17} = Qn{2-0};
1990 let Inst{15-13} = Qd{2-0};
1991 let Inst{12-8} = 0b01000;
1992 let Inst{7} = Qn{3};
1993 let Inst{4} = 0b0;
1994 }
1995
1996 def MVE_VCMLAf16 : MVE_VCMLA<"f16", 0b0>;
1997 def MVE_VCMLAf32 : MVE_VCMLA<"f32", 0b1>;
1998
1999 class MVE_VADDSUBFMA_fp
2000 bit bit_8, bit bit_21, dag iops=(ins),
2001 vpred_ops vpred=vpred_r, string cstr="",
2002 list pattern=[]>
2003 : MVEFloatArithNeon
2004 !con(iops, (ins MQPR:$Qn, MQPR:$Qm)), "$Qd, $Qn, $Qm",
2005 vpred, cstr, pattern> {
2006 bits<4> Qd;
2007 bits<4> Qn;
2008
2009 let Inst{28} = 0b0;
2010 let Inst{25-23} = 0b110;
2011 let Inst{22} = Qd{3};
2012 let Inst{21} = bit_21;
2013 let Inst{19-17} = Qn{2-0};
2014 let Inst{15-13} = Qd{2-0};
2015 let Inst{11-9} = 0b110;
2016 let Inst{8} = bit_8;
2017 let Inst{7} = Qn{3};
2018 let Inst{4} = bit_4;
2019 }
2020
2021 def MVE_VFMAf32 : MVE_VADDSUBFMA_fp<"vfma", "f32", 0b0, 0b1, 0b0, 0b0,
2022 (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
2023 def MVE_VFMAf16 : MVE_VADDSUBFMA_fp<"vfma", "f16", 0b1, 0b1, 0b0, 0b0,
2024 (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
2025
2026 def MVE_VFMSf32 : MVE_VADDSUBFMA_fp<"vfms", "f32", 0b0, 0b1, 0b0, 0b1,
2027 (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
2028 def MVE_VFMSf16 : MVE_VADDSUBFMA_fp<"vfms", "f16", 0b1, 0b1, 0b0, 0b1,
2029 (ins MQPR:$Qd_src), vpred_n, "$Qd = $Qd_src">;
2030
2031 def MVE_VADDf32 : MVE_VADDSUBFMA_fp<"vadd", "f32", 0b0, 0b0, 0b1, 0b0>;
2032 def MVE_VADDf16 : MVE_VADDSUBFMA_fp<"vadd", "f16", 0b1, 0b0, 0b1, 0b0>;
2033
2034 def MVE_VSUBf32 : MVE_VADDSUBFMA_fp<"vsub", "f32", 0b0, 0b0, 0b1, 0b1>;
2035 def MVE_VSUBf16 : MVE_VADDSUBFMA_fp<"vsub", "f16", 0b1, 0b0, 0b1, 0b1>;
2036
2037 class MVE_VCADD pattern=[]>
2038 : MVEFloatArithNeon<"vcadd", suffix, size, (outs MQPR:$Qd),
2039 (ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
2040 "$Qd, $Qn, $Qm, $rot", vpred_r, "", pattern> {
2041 bits<4> Qd;
2042 bits<4> Qn;
2043 bit rot;
2044
2045 let Inst{28} = 0b1;
2046 let Inst{25} = 0b0;
2047 let Inst{24} = rot;
2048 let Inst{23} = 0b1;
2049 let Inst{22} = Qd{3};
2050 let Inst{21} = 0b0;
2051 let Inst{19-17} = Qn{2-0};
2052 let Inst{15-13} = Qd{2-0};
2053 let Inst{12-8} = 0b01000;
2054 let Inst{7} = Qn{3};
2055 let Inst{4} = 0b0;
2056 }
2057
2058 def MVE_VCADDf16 : MVE_VCADD<"f16", 0b0>;
2059 def MVE_VCADDf32 : MVE_VCADD<"f32", 0b1>;
2060
2061 class MVE_VABD_fp
2062 : MVE_float<"vabd", suffix, (outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
2063 "$Qd, $Qn, $Qm", vpred_r, ""> {
2064 bits<4> Qd;
2065 bits<4> Qn;
2066
2067 let Inst{28} = 0b1;
2068 let Inst{25-23} = 0b110;
2069 let Inst{22} = Qd{3};
2070 let Inst{21} = 0b1;
2071 let Inst{20} = size;
2072 let Inst{19-17} = Qn{2-0};
2073 let Inst{16} = 0b0;
2074 let Inst{15-13} = Qd{2-0};
2075 let Inst{11-8} = 0b1101;
2076 let Inst{7} = Qn{3};
2077 let Inst{4} = 0b0;
2078 }
2079
2080 def MVE_VABDf32 : MVE_VABD_fp<"f32", 0b0>;
2081 def MVE_VABDf16 : MVE_VABD_fp<"f16", 0b1>;
2082
2083 class MVE_VCVT_fix
2084 Operand imm_operand_type, list pattern=[]>
2085 : MVE_float<"vcvt", suffix,
2086 (outs MQPR:$Qd), (ins MQPR:$Qm, imm_operand_type:$imm6),
2087 "$Qd, $Qm, $imm6", vpred_r, "", pattern> {
2088 bits<4> Qd;
2089 bits<6> imm6;
2090
2091 let Inst{28} = U;
2092 let Inst{25-23} = 0b111;
2093 let Inst{22} = Qd{3};
2094 let Inst{21} = 0b1;
2095 let Inst{19-16} = imm6{3-0};
2096 let Inst{15-13} = Qd{2-0};
2097 let Inst{11-10} = 0b11;
2098 let Inst{9} = fsi;
2099 let Inst{8} = op;
2100 let Inst{7} = 0b0;
2101 let Inst{4} = 0b1;
2102
2103 let DecoderMethod = "DecodeMVEVCVTt1fp";
2104 }
2105
2106 class MVE_VCVT_imm_asmop : AsmOperandClass {
2107 let PredicateMethod = "isImmediate<1," # Bits # ">";
2108 let DiagnosticString =
2109 "MVE fixed-point immediate operand must be between 1 and " # Bits;
2110 let Name = "MVEVcvtImm" # Bits;
2111 let RenderMethod = "addImmOperands";
2112 }
2113 class MVE_VCVT_imm: Operand {
2114 let ParserMatchClass = MVE_VCVT_imm_asmop;
2115 let EncoderMethod = "getNEONVcvtImm32OpValue";
2116 let DecoderMethod = "DecodeVCVTImmOperand";
2117 }
2118
2119 class MVE_VCVT_fix_f32
2120 : MVE_VCVT_fix> {
2121 let Inst{20} = imm6{4};
2122 }
2123 class MVE_VCVT_fix_f16
2124 : MVE_VCVT_fix> {
2125 let Inst{20} = 0b1;
2126 }
2127
2128 def MVE_VCVTf16s16_fix : MVE_VCVT_fix_f16<"f16.s16", 0b0, 0b0>;
2129 def MVE_VCVTs16f16_fix : MVE_VCVT_fix_f16<"s16.f16", 0b0, 0b1>;
2130 def MVE_VCVTf16u16_fix : MVE_VCVT_fix_f16<"f16.u16", 0b1, 0b0>;
2131 def MVE_VCVTu16f16_fix : MVE_VCVT_fix_f16<"u16.f16", 0b1, 0b1>;
2132 def MVE_VCVTf32s32_fix : MVE_VCVT_fix_f32<"f32.s32", 0b0, 0b0>;
2133 def MVE_VCVTs32f32_fix : MVE_VCVT_fix_f32<"s32.f32", 0b0, 0b1>;
2134 def MVE_VCVTf32u32_fix : MVE_VCVT_fix_f32<"f32.u32", 0b1, 0b0>;
2135 def MVE_VCVTu32f32_fix : MVE_VCVT_fix_f32<"u32.f32", 0b1, 0b1>;
2136
2137 class MVE_VCVT_fp_int_anpm size, bit op, string anpm,
2138 bits<2> rm, list pattern=[]>
2139 : MVE_float
2140 (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
2141 bits<4> Qd;
2142
2143 let Inst{28} = 0b1;
2144 let Inst{25-23} = 0b111;
2145 let Inst{22} = Qd{3};
2146 let Inst{21-20} = 0b11;
2147 let Inst{19-18} = size;
2148 let Inst{17-16} = 0b11;
2149 let Inst{15-13} = Qd{2-0};
2150 let Inst{12-10} = 0b000;
2151 let Inst{9-8} = rm;
2152 let Inst{7} = op;
2153 let Inst{4} = 0b0;
2154 }
2155
2156 multiclass MVE_VCVT_fp_int_anpm_multi size, bit op,
2157 list pattern=[]> {
2158 def a : MVE_VCVT_fp_int_anpm;
2159 def n : MVE_VCVT_fp_int_anpm;
2160 def p : MVE_VCVT_fp_int_anpm;
2161 def m : MVE_VCVT_fp_int_anpm;
2162 }
2163
2164 // This defines instructions such as MVE_VCVTu16f16a, with an explicit
2165 // rounding-mode suffix on the mnemonic. The class below will define
2166 // the bare MVE_VCVTu16f16 (with implied rounding toward zero).
2167 defm MVE_VCVTs16f16 : MVE_VCVT_fp_int_anpm_multi<"s16.f16", 0b01, 0b0>;
2168 defm MVE_VCVTu16f16 : MVE_VCVT_fp_int_anpm_multi<"u16.f16", 0b01, 0b1>;
2169 defm MVE_VCVTs32f32 : MVE_VCVT_fp_int_anpm_multi<"s32.f32", 0b10, 0b0>;
2170 defm MVE_VCVTu32f32 : MVE_VCVT_fp_int_anpm_multi<"u32.f32", 0b10, 0b1>;
2171
2172 class MVE_VCVT_fp_int size, bits<2> op,
2173 list pattern=[]>
2174 : MVE_float<"vcvt", suffix, (outs MQPR:$Qd),
2175 (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
2176 bits<4> Qd;
2177
2178 let Inst{28} = 0b1;
2179 let Inst{25-23} = 0b111;
2180 let Inst{22} = Qd{3};
2181 let Inst{21-20} = 0b11;
2182 let Inst{19-18} = size;
2183 let Inst{17-16} = 0b11;
2184 let Inst{15-13} = Qd{2-0};
2185 let Inst{12-9} = 0b0011;
2186 let Inst{8-7} = op;
2187 let Inst{4} = 0b0;
2188 }
2189
2190 // The unsuffixed VCVT for float->int implicitly rounds toward zero,
2191 // which I reflect here in the llvm instruction names
2192 def MVE_VCVTs16f16z : MVE_VCVT_fp_int<"s16.f16", 0b01, 0b10>;
2193 def MVE_VCVTu16f16z : MVE_VCVT_fp_int<"u16.f16", 0b01, 0b11>;
2194 def MVE_VCVTs32f32z : MVE_VCVT_fp_int<"s32.f32", 0b10, 0b10>;
2195 def MVE_VCVTu32f32z : MVE_VCVT_fp_int<"u32.f32", 0b10, 0b11>;
2196 // Whereas VCVT for int->float rounds to nearest
2197 def MVE_VCVTf16s16n : MVE_VCVT_fp_int<"f16.s16", 0b01, 0b00>;
2198 def MVE_VCVTf16u16n : MVE_VCVT_fp_int<"f16.u16", 0b01, 0b01>;
2199 def MVE_VCVTf32s32n : MVE_VCVT_fp_int<"f32.s32", 0b10, 0b00>;
2200 def MVE_VCVTf32u32n : MVE_VCVT_fp_int<"f32.u32", 0b10, 0b01>;
2201
2202 class MVE_VABSNEG_fp size, bit negate,
2203 list pattern=[]>
2204 : MVE_float
2205 (ins MQPR:$Qm), "$Qd, $Qm", vpred_r, "", pattern> {
2206 bits<4> Qd;
2207
2208 let Inst{28} = 0b1;
2209 let Inst{25-23} = 0b111;
2210 let Inst{22} = Qd{3};
2211 let Inst{21-20} = 0b11;
2212 let Inst{19-18} = size;
2213 let Inst{17-16} = 0b01;
2214 let Inst{15-13} = Qd{2-0};
2215 let Inst{11-8} = 0b0111;
2216 let Inst{7} = negate;
2217 let Inst{4} = 0b0;
2218 }
2219
2220 def MVE_VABSf16 : MVE_VABSNEG_fp<"vabs", "f16", 0b01, 0b0>;
2221 def MVE_VABSf32 : MVE_VABSNEG_fp<"vabs", "f32", 0b10, 0b0>;
2222
2223 def MVE_VNEGf16 : MVE_VABSNEG_fp<"vneg", "f16", 0b01, 0b1>;
2224 def MVE_VNEGf32 : MVE_VABSNEG_fp<"vneg", "f32", 0b10, 0b1>;
2225
2226 class MVE_VMAXMINNMA
2227 list pattern=[]>
2228 : MVE_f<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
2229 NoItinerary, iname, suffix, "$Qd, $Qm", vpred_n, "$Qd = $Qd_src",
2230 pattern> {
2231 bits<4> Qd;
2232 bits<4> Qm;
2233
2234 let Inst{28} = size;
2235 let Inst{25-23} = 0b100;
2236 let Inst{22} = Qd{3};
2237 let Inst{21-16} = 0b111111;
2238 let Inst{15-13} = Qd{2-0};
2239 let Inst{12} = bit_12;
2240 let Inst{11-6} = 0b111010;
2241 let Inst{5} = Qm{3};
2242 let Inst{4} = 0b0;
2243 let Inst{3-1} = Qm{2-0};
2244 let Inst{0} = 0b1;
2245 }
2246
2247 def MVE_VMAXNMAf32 : MVE_VMAXMINNMA<"vmaxnma", "f32", 0b0, 0b0>;
2248 def MVE_VMAXNMAf16 : MVE_VMAXMINNMA<"vmaxnma", "f16", 0b1, 0b0>;
2249
2250 def MVE_VMINNMAf32 : MVE_VMAXMINNMA<"vminnma", "f32", 0b0, 0b1>;
2251 def MVE_VMINNMAf16 : MVE_VMAXMINNMA<"vminnma", "f16", 0b1, 0b1>;
2252
2253 // end of MVE Floating Point instructions
2254
18952255 class MVE_VPT size, dag iops, string asm, list pattern=[]>
18962256 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
18972257 bits<3> fc;
59635963 Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
59645964 Mnemonic == "vmvne" || Mnemonic == "vorne" ||
59655965 Mnemonic == "vnege" || Mnemonic == "vnegt" ||
5966 Mnemonic == "vmule" || Mnemonic == "vmult" ||
5967 Mnemonic == "vrintne" ||
59665968 Mnemonic.startswith("vq")))) {
59675969 unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
59685970 if (CC != ~0U) {
60076009 if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
60086010 Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
60096011 Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
6010 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt") {
6012 Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vcvt") {
60116013 unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
60126014 if (CC != ~0U) {
60136015 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
63146316 OperandVector &Operands) {
63156317 // VRINT{Z, X} have a predicate operand in VFP, but not in NEON
63166318 unsigned RegIdx = 3;
6317 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx") &&
6319 if ((((Mnemonic == "vrintz" || Mnemonic == "vrintx") && !hasMVE()) ||
6320 Mnemonic == "vrintr") &&
63186321 (static_cast(*Operands[2]).getToken() == ".f32" ||
63196322 static_cast(*Operands[2]).getToken() == ".f16")) {
63206323 if (static_cast(*Operands[3]).isToken() &&
65636566 // definition in tblgen. Since these instructions may also have the
65646567 // scalar predication operand we do not add the vector one and leave until
65656568 // now to fix it up.
6566 if (CanAcceptVPTPredicationCode && Mnemonic != "vmov") {
6569 if (CanAcceptVPTPredicationCode && Mnemonic != "vmov" &&
6570 !(Mnemonic.startswith("vcvt") && Mnemonic != "vcvta" &&
6571 Mnemonic != "vcvtn" && Mnemonic != "vcvtp" && Mnemonic != "vcvtm")) {
65676572 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
65686573 CarrySetting);
65696574 Operands.push_back(ARMOperand::CreateVPTPred(
66616666 ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
66626667 Operands.insert(Operands.begin(),
66636668 ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
6669 } else if (Mnemonic == "vcvt" && PredicationCode == ARMCC::NE &&
6670 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6671 // Another nasty hack to deal with the ambiguity between vcvt with scalar
6672 // predication 'ne' and vcvtn with vector predication 'e'. As above we
6673 // can only distinguish between the two after we have parsed their
6674 // operands.
6675 Operands.erase(Operands.begin() + 1);
6676 Operands.erase(Operands.begin());
6677 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6678 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
6679 Mnemonic.size() - 1 + CarrySetting);
6680 Operands.insert(Operands.begin(),
6681 ARMOperand::CreateVPTPred(ARMVCC::Else, PLoc));
6682 Operands.insert(Operands.begin(),
6683 ARMOperand::CreateToken(StringRef("vcvtn"), MLoc));
66646684 }
66656685 // For vmov instructions, as mentioned earlier, we did not add the vector
66666686 // predication code, since these may contain operands that require
66676687 // special parsing. So now we have to see if they require vector
66686688 // predication and replace the scalar one with the vector predication
66696689 // operand if that is the case.
6670 else if (Mnemonic == "vmov") {
6690 else if (Mnemonic == "vmov" ||
6691 (Mnemonic.startswith("vcvt") && !Mnemonic.startswith("vcvta") &&
6692 !Mnemonic.startswith("vcvtn") && !Mnemonic.startswith("vcvtp") &&
6693 !Mnemonic.startswith("vcvtm"))) {
66716694 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
6695 // We could not split the vector predicate off vcvt because it might
6696 // have been the scalar vcvtt instruction. Now we know its a vector
6697 // instruction, we still need to check whether its the vector
6698 // predicated vcvt with 'Then' predication or the vector vcvtt. We can
6699 // distinguish the two based on the suffixes, if it is any of
6700 // ".f16.f32", ".f32.f16", ".f16.f64" or ".f64.f16" then it is the vcvtt.
6701 if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) {
6702 auto Sz1 = static_cast(*Operands[2]);
6703 auto Sz2 = static_cast(*Operands[3]);
6704 if (!(Sz1.isToken() && Sz1.getToken().startswith(".f") &&
6705 Sz2.isToken() && Sz2.getToken().startswith(".f"))) {
6706 Operands.erase(Operands.begin());
6707 SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
6708 VPTPredicationCode = ARMVCC::Then;
6709
6710 Mnemonic = Mnemonic.substr(0, 4);
6711 Operands.insert(Operands.begin(),
6712 ARMOperand::CreateToken(Mnemonic, MLoc));
6713 }
6714 }
66726715 Operands.erase(Operands.begin() + 1);
66736716 SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
66746717 Mnemonic.size() + CarrySetting);
373373 uint64_t Address, const void *Decoder);
374374 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
375375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
377 uint64_t Address, const void *Decoder);
376378 static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
377379 unsigned Val,
378380 uint64_t Address,
504506 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
505507 uint64_t Address,
506508 const void *Decoder);
509 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
510 uint64_t Address, const void *Decoder);
507511 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
508512 uint64_t Address,
509513 const void *Decoder);
60006004 return MCDisassembler::Success;
60016005 }
60026006
6007 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
6008 uint64_t Address, const void *Decoder) {
6009 DecodeStatus S = MCDisassembler::Success;
6010
6011 unsigned DecodedVal = 64 - Val;
6012
6013 switch (Inst.getOpcode()) {
6014 case ARM::MVE_VCVTf16s16_fix:
6015 case ARM::MVE_VCVTs16f16_fix:
6016 case ARM::MVE_VCVTf16u16_fix:
6017 case ARM::MVE_VCVTu16f16_fix:
6018 if (DecodedVal > 16)
6019 return MCDisassembler::Fail;
6020 case ARM::MVE_VCVTf32s32_fix:
6021 case ARM::MVE_VCVTs32f32_fix:
6022 case ARM::MVE_VCVTf32u32_fix:
6023 case ARM::MVE_VCVTu32f32_fix:
6024 if (DecodedVal > 32)
6025 return MCDisassembler::Fail;
6026 }
6027
6028 Inst.addOperand(MCOperand::createImm(64 - Val));
6029
6030 return S;
6031 }
6032
60036033 static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) {
60046034 switch (Opcode) {
60056035 case ARM::VSTR_P0_off:
61336163
61346164 return S;
61356165 }
6166
6167 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
6168 const void *Decoder) {
6169 DecodeStatus S = MCDisassembler::Success;
6170 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
6171 fieldFromInstruction(Insn, 13, 3));
6172 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) |
6173 fieldFromInstruction(Insn, 1, 3));
6174 unsigned imm6 = fieldFromInstruction(Insn, 16, 6);
6175
6176 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6177 return MCDisassembler::Fail;
6178 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6179 return MCDisassembler::Fail;
6180 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
6181 return MCDisassembler::Fail;
6182
6183 return S;
6184 }
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
1 # RUN: | FileCheck --check-prefix=CHECK-NOFP %s
2 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
3 # RUN: | FileCheck --check-prefix=CHECK %s
4 # RUN: FileCheck --check-prefix=ERROR < %t %s
5
6 # CHECK: vrintn.f16 q1, q0 @ encoding: [0xb6,0xff,0x40,0x24]
7 # CHECK-NOFP-NOT: vrintn.f16 q1, q0 @ encoding: [0xb6,0xff,0x40,0x24]
8 vrintn.f16 q1, q0
9
10 # CHECK: vrintn.f32 q0, q4 @ encoding: [0xba,0xff,0x48,0x04]
11 # CHECK-NOFP-NOT: vrintn.f32 q0, q4 @ encoding: [0xba,0xff,0x48,0x04]
12 vrintn.f32 q0, q4
13
14 # CHECK: vrinta.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x05]
15 # CHECK-NOFP-NOT: vrinta.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x05]
16 vrinta.f16 q0, q1
17
18 # CHECK: vrinta.f32 q1, q3 @ encoding: [0xba,0xff,0x46,0x25]
19 # CHECK-NOFP-NOT: vrinta.f32 q1, q3 @ encoding: [0xba,0xff,0x46,0x25]
20 vrinta.f32 q1, q3
21
22 # CHECK: vrintm.f16 q0, q5 @ encoding: [0xb6,0xff,0xca,0x06]
23 # CHECK-NOFP-NOT: vrintm.f16 q0, q5 @ encoding: [0xb6,0xff,0xca,0x06]
24 vrintm.f16 q0, q5
25
26 # CHECK: vrintm.f32 q0, q4 @ encoding: [0xba,0xff,0xc8,0x06]
27 # CHECK-NOFP-NOT: vrintm.f32 q0, q4 @ encoding: [0xba,0xff,0xc8,0x06]
28 vrintm.f32 q0, q4
29
30 # CHECK: vrintp.f16 q1, q0 @ encoding: [0xb6,0xff,0xc0,0x27]
31 # CHECK-NOFP-NOT: vrintp.f16 q1, q0 @ encoding: [0xb6,0xff,0xc0,0x27]
32 vrintp.f16 q1, q0
33
34 # CHECK: vrintp.f32 q0, q1 @ encoding: [0xba,0xff,0xc2,0x07]
35 # CHECK-NOFP-NOT: vrintp.f32 q0, q1 @ encoding: [0xba,0xff,0xc2,0x07]
36 vrintp.f32 q0, q1
37
38 # CHECK: vrintx.f16 q1, q2 @ encoding: [0xb6,0xff,0xc4,0x24]
39 # CHECK-NOFP-NOT: vrintx.f16 q1, q2 @ encoding: [0xb6,0xff,0xc4,0x24]
40 vrintx.f16 q1, q2
41
42 # CHECK: vrintx.f32 q1, q1 @ encoding: [0xba,0xff,0xc2,0x24]
43 # CHECK-NOFP-NOT: vrintx.f32 q1, q1 @ encoding: [0xba,0xff,0xc2,0x24]
44 vrintx.f32 q1, q1
45
46 # CHECK: vrintz.f16 q1, q6 @ encoding: [0xb6,0xff,0xcc,0x25]
47 # CHECK-NOFP-NOT: vrintz.f16 q1, q6 @ encoding: [0xb6,0xff,0xcc,0x25]
48 vrintz.f16 q1, q6
49
50 # CHECK: vrintz.f32 q1, q0 @ encoding: [0xba,0xff,0xc0,0x25]
51 # CHECK-NOFP-NOT: vrintz.f32 q1, q0 @ encoding: [0xba,0xff,0xc0,0x25]
52 vrintz.f32 q1, q0
53
54 # CHECK: vrintr.f32 s0, s1 @ encoding: [0xb6,0xee,0x60,0x0a]
55 # CHECK-NOFP-NOT: vrintr.f32 s0, s1 @ encoding: [0xb6,0xee,0x60,0x0a]
56 vrintr.f32.f32 s0, s1
57
58 # CHECK: vrintr.f64 d0, d1 @ encoding: [0xb6,0xee,0x41,0x0b]
59 # CHECK-NOFP-NOT: vrintr.f64 d0, d1 @ encoding: [0xb6,0xee,0x41,0x0b]
60 vrintr.f64.f64 d0, d1
61
62 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
63 vrintr.f32.f32 q0, q1
64
65 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
66 vrintr.f64 q0, q1
67
68 # CHECK: vmul.f16 q2, q1, q3 @ encoding: [0x12,0xff,0x56,0x4d]
69 # CHECK-NOFP-NOT: vmul.f16 q2, q1, q3 @ encoding: [0x12,0xff,0x56,0x4d]
70 vmul.f16 q2, q1, q3
71
72 # CHECK: vmul.f32 q0, q0, q5 @ encoding: [0x00,0xff,0x5a,0x0d]
73 # CHECK-NOFP-NOT: vmul.f32 q0, q0, q5 @ encoding: [0x00,0xff,0x5a,0x0d]
74 vmul.f32 q0, q0, q5
75
76 # CHECK: vcmla.f16 q3, q2, q1, #0 @ encoding: [0x24,0xfc,0x42,0x68]
77 # CHECK-NOFP-NOT: vcmla.f16 q3, q2, q1, #0 @ encoding: [0x24,0xfc,0x42,0x68]
78 vcmla.f16 q3, q2, q1, #0
79
80 # CHECK: vcmla.f16 q0, q0, q5, #90 @ encoding: [0xa0,0xfc,0x4a,0x08]
81 # CHECK-NOFP-NOT: vcmla.f16 q0, q0, q5, #90 @ encoding: [0xa0,0xfc,0x4a,0x08]
82 vcmla.f16 q0, q0, q5, #90
83
84 # CHECK: vcmla.f16 q3, q7, q2, #180 @ encoding: [0x2e,0xfd,0x44,0x68]
85 # CHECK-NOFP-NOT: vcmla.f16 q3, q7, q2, #180 @ encoding: [0x2e,0xfd,0x44,0x68]
86 vcmla.f16 q3, q7, q2, #180
87
88 # CHECK: vcmla.f16 q2, q7, q6, #270 @ encoding: [0xae,0xfd,0x4c,0x48]
89 # CHECK-NOFP-NOT: vcmla.f16 q2, q7, q6, #270 @ encoding: [0xae,0xfd,0x4c,0x48]
90 vcmla.f16 q2, q7, q6, #270
91
92 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 0, 90, 180 or 270
93 vcmla.f16 q3, q2, q1, #200
94
95 # CHECK: vcmla.f32 q2, q6, q6, #0 @ encoding: [0x3c,0xfc,0x4c,0x48]
96 # CHECK-NOFP-NOT: vcmla.f32 q2, q6, q6, #0 @ encoding: [0x3c,0xfc,0x4c,0x48]
97 vcmla.f32 q2, q6, q6, #0
98
99 # CHECK: vcmla.f32 q7, q1, q3, #90 @ encoding: [0xb2,0xfc,0x46,0xe8]
100 # CHECK-NOFP-NOT: vcmla.f32 q7, q1, q3, #90 @ encoding: [0xb2,0xfc,0x46,0xe8]
101 vcmla.f32 q7, q1, q3, #90
102
103 # CHECK: vcmla.f32 q4, q5, q3, #180 @ encoding: [0x3a,0xfd,0x46,0x88]
104 # CHECK-NOFP-NOT: vcmla.f32 q4, q5, q3, #180 @ encoding: [0x3a,0xfd,0x46,0x88]
105 vcmla.f32 q4, q5, q3, #180
106
107 # CHECK: vcmla.f32 q3, q2, q7, #270 @ encoding: [0xb4,0xfd,0x4e,0x68]
108 # CHECK-NOFP-NOT: vcmla.f32 q3, q2, q7, #270 @ encoding: [0xb4,0xfd,0x4e,0x68]
109 vcmla.f32 q3, q2, q7, #270
110
111 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 0, 90, 180 or 270
112 vcmla.f32 q3, q2, q1, #16
113
114 # CHECK: vfma.f16 q0, q2, q3 @ encoding: [0x14,0xef,0x56,0x0c]
115 # CHECK-NOFP-NOT: vfma.f16 q0, q2, q3 @ encoding: [0x14,0xef,0x56,0x0c]
116 vfma.f16 q0, q2, q3
117
118 # CHECK: vfma.f32 q0, q3, q7 @ encoding: [0x06,0xef,0x5e,0x0c]
119 # CHECK-NOFP-NOT: vfma.f32 q0, q3, q7 @ encoding: [0x06,0xef,0x5e,0x0c]
120 vfma.f32 q0, q3, q7
121
122 # CHECK: vfms.f16 q0, q2, q5 @ encoding: [0x34,0xef,0x5a,0x0c]
123 # CHECK-NOFP-NOT: vfms.f16 q0, q2, q5 @ encoding: [0x34,0xef,0x5a,0x0c]
124 vfms.f16 q0, q2, q5
125
126 # CHECK: vfms.f32 q1, q1, q2 @ encoding: [0x22,0xef,0x54,0x2c]
127 # CHECK-NOFP-NOT: vfms.f32 q1, q1, q2 @ encoding: [0x22,0xef,0x54,0x2c]
128 vfms.f32 q1, q1, q2
129
130 # CHECK: vadd.f16 q0, q0, q5 @ encoding: [0x10,0xef,0x4a,0x0d]
131 # CHECK-NOFP-NOT: vadd.f16 q0, q0, q5 @ encoding: [0x10,0xef,0x4a,0x0d]
132 vadd.f16 q0, q0, q5
133
134 # CHECK: vadd.f32 q1, q3, q0 @ encoding: [0x06,0xef,0x40,0x2d]
135 # CHECK-NOFP-NOT: vadd.f32 q1, q3, q0 @ encoding: [0x06,0xef,0x40,0x2d]
136 vadd.f32 q1, q3, q0
137
138 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
139 vaddeq.f32 q0, q1, q2
140
141 # CHECK: vadd.f32 q0, q1, q2 @ encoding: [0x02,0xef,0x44,0x0d]
142 # CHECK-NOFP-NOT: vadd.f32 q0, q1, q2 @ encoding: [0x02,0xef,0x44,0x0d]
143 vadd.f32 q0, q1, q2
144
145 # CHECK: vcadd.f16 q2, q1, q7, #90 @ encoding: [0x82,0xfc,0x4e,0x48]
146 # CHECK-NOFP-NOT: vcadd.f16 q2, q1, q7, #90 @ encoding: [0x82,0xfc,0x4e,0x48]
147 vcadd.f16 q2, q1, q7, #90
148
149 # CHECK: vcadd.f16 q2, q5, q7, #270 @ encoding: [0x8a,0xfd,0x4e,0x48]
150 # CHECK-NOFP-NOT: vcadd.f16 q2, q5, q7, #270 @ encoding: [0x8a,0xfd,0x4e,0x48]
151 vcadd.f16 q2, q5, q7, #270
152
153 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
154 vcadd.f16 q2, q5, q7, #180
155
156 # CHECK: vcadd.f32 q0, q4, q7, #90 @ encoding: [0x98,0xfc,0x4e,0x08]
157 # CHECK-NOFP-NOT: vcadd.f32 q0, q4, q7, #90 @ encoding: [0x98,0xfc,0x4e,0x08]
158 vcadd.f32 q0, q4, q7, #90
159
160 # CHECK: vcadd.f32 q2, q2, q3, #270 @ encoding: [0x94,0xfd,0x46,0x48]
161 # CHECK-NOFP-NOT: vcadd.f32 q2, q2, q3, #270 @ encoding: [0x94,0xfd,0x46,0x48]
162 vcadd.f32 q2, q2, q3, #270
163
164 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: complex rotation must be 90 or 270
165 vcadd.f32 q2, q5, q7, #0
166
167 # CHECK: vabd.f16 q0, q0, q6 @ encoding: [0x30,0xff,0x4c,0x0d]
168 # CHECK-NOFP-NOT: vabd.f16 q0, q0, q6 @ encoding: [0x30,0xff,0x4c,0x0d]
169 vabd.f16 q0, q0, q6
170
171 # CHECK: vabd.f32 q0, q1, q4 @ encoding: [0x22,0xff,0x48,0x0d]
172 # CHECK-NOFP-NOT: vabd.f32 q0, q1, q4 @ encoding: [0x22,0xff,0x48,0x0d]
173 vabd.f32 q0, q1, q4
174
175 # CHECK: vcvt.f16.s16 q1, q7, #1 @ encoding: [0xbf,0xef,0x5e,0x2c]
176 # CHECK-NOFP-NOT: vcvt.f16.s16 q1, q7, #1 @ encoding: [0xbf,0xef,0x5e,0x2c]
177 vcvt.f16.s16 q1, q7, #1
178
179 # CHECK: vcvt.f16.s16 q1, q7, #16 @ encoding: [0xb0,0xef,0x5e,0x2c]
180 # CHECK-NOFP-NOT: vcvt.f16.s16 q1, q7, #16 @ encoding: [0xb0,0xef,0x5e,0x2c]
181 vcvt.f16.s16 q1, q7, #16
182
183 # CHECK: vcvt.f16.s16 q1, q7, #11 @ encoding: [0xb5,0xef,0x5e,0x2c]
184 # CHECK-NOFP-NOT: vcvt.f16.s16 q1, q7, #11 @ encoding: [0xb5,0xef,0x5e,0x2c]
185 vcvt.f16.s16 q1, q7, #11
186
187 # CHECK: vcvt.s16.f16 q1, q1, #3 @ encoding: [0xbd,0xef,0x52,0x2d]
188 # CHECK-NOFP-NOT: vcvt.s16.f16 q1, q1, #3 @ encoding: [0xbd,0xef,0x52,0x2d]
189 vcvt.s16.f16 q1, q1, #3
190
191 # CHECK: vcvt.f16.u16 q2, q1, #10 @ encoding: [0xb6,0xff,0x52,0x4c]
192 # CHECK-NOFP-NOT: vcvt.f16.u16 q2, q1, #10 @ encoding: [0xb6,0xff,0x52,0x4c]
193 vcvt.f16.u16 q2, q1, #10
194
195 # CHECK: vcvt.u16.f16 q0, q0, #3 @ encoding: [0xbd,0xff,0x50,0x0d]
196 # CHECK-NOFP-NOT: vcvt.u16.f16 q0, q0, #3 @ encoding: [0xbd,0xff,0x50,0x0d]
197 vcvt.u16.f16 q0, q0, #3
198
199 # CHECK: vcvt.f32.s32 q1, q7, #1 @ encoding: [0xbf,0xef,0x5e,0x2e]
200 # CHECK-NOFP-NOT: vcvt.f32.s32 q1, q7, #1 @ encoding: [0xbf,0xef,0x5e,0x2e]
201 vcvt.f32.s32 q1, q7, #1
202
203 # CHECK: vcvt.f32.s32 q1, q7, #32 @ encoding: [0xa0,0xef,0x5e,0x2e]
204 # CHECK-NOFP-NOT: vcvt.f32.s32 q1, q7, #32 @ encoding: [0xa0,0xef,0x5e,0x2e]
205 vcvt.f32.s32 q1, q7, #32
206
207 # CHECK: vcvt.f32.s32 q1, q7, #6 @ encoding: [0xba,0xef,0x5e,0x2e]
208 # CHECK-NOFP-NOT: vcvt.f32.s32 q1, q7, #6 @ encoding: [0xba,0xef,0x5e,0x2e]
209 vcvt.f32.s32 q1, q7, #6
210
211 # CHECK: vcvt.s32.f32 q1, q0, #21 @ encoding: [0xab,0xef,0x50,0x2f]
212 # CHECK-NOFP-NOT: vcvt.s32.f32 q1, q0, #21 @ encoding: [0xab,0xef,0x50,0x2f]
213 vcvt.s32.f32 q1, q0, #21
214
215 # CHECK: vcvt.f32.u32 q1, q4, #4 @ encoding: [0xbc,0xff,0x58,0x2e]
216 # CHECK-NOFP-NOT: vcvt.f32.u32 q1, q4, #4 @ encoding: [0xbc,0xff,0x58,0x2e]
217 vcvt.f32.u32 q1, q4, #4
218
219 # CHECK: vcvt.u32.f32 q1, q5, #8 @ encoding: [0xb8,0xff,0x5a,0x2f]
220 # CHECK-NOFP-NOT: vcvt.u32.f32 q1, q5, #8 @ encoding: [0xb8,0xff,0x5a,0x2f]
221 vcvt.u32.f32 q1, q5, #8
222
223 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: MVE fixed-point immediate operand must be between 1 and 16
224 vcvt.f16.s16 q0, q1, #-1
225
226 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: MVE fixed-point immediate operand must be between 1 and 16
227 vcvt.f16.s16 q0, q1, #0
228
229 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: MVE fixed-point immediate operand must be between 1 and 16
230 vcvt.f16.s16 q0, q1, #17
231
232 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: MVE fixed-point immediate operand must be between 1 and 32
233 vcvt.f32.s32 q0, q1, #-1
234
235 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: MVE fixed-point immediate operand must be between 1 and 32
236 vcvt.f32.s32 q0, q1, #0
237
238 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: MVE fixed-point immediate operand must be between 1 and 32
239 vcvt.f32.s32 q0, q1, #33
240
241 # CHECK: vcvt.f16.s16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x06]
242 # CHECK-NOFP-NOT: vcvt.f16.s16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x06]
243 vcvt.f16.s16 q0, q1
244
245 # CHECK: vcvt.f16.u16 q0, q4 @ encoding: [0xb7,0xff,0xc8,0x06]
246 # CHECK-NOFP-NOT: vcvt.f16.u16 q0, q4 @ encoding: [0xb7,0xff,0xc8,0x06]
247 vcvt.f16.u16 q0, q4
248
249 # CHECK: vcvt.s16.f16 q0, q0 @ encoding: [0xb7,0xff,0x40,0x07]
250 # CHECK-NOFP-NOT: vcvt.s16.f16 q0, q0 @ encoding: [0xb7,0xff,0x40,0x07]
251 vcvt.s16.f16 q0, q0
252
253 # CHECK: vcvt.u16.f16 q0, q0 @ encoding: [0xb7,0xff,0xc0,0x07]
254 # CHECK-NOFP-NOT: vcvt.u16.f16 q0, q0 @ encoding: [0xb7,0xff,0xc0,0x07]
255 vcvt.u16.f16 q0, q0
256
257 # CHECK: vcvt.f32.s32 q0, q0 @ encoding: [0xbb,0xff,0x40,0x06]
258 # CHECK-NOFP-NOT: vcvt.f32.s32 q0, q0 @ encoding: [0xbb,0xff,0x40,0x06]
259 vcvt.f32.s32 q0, q0
260
261 # CHECK: vcvt.f32.u32 q0, q0 @ encoding: [0xbb,0xff,0xc0,0x06]
262 # CHECK-NOFP-NOT: vcvt.f32.u32 q0, q0 @ encoding: [0xbb,0xff,0xc0,0x06]
263 vcvt.f32.u32 q0, q0
264
265 # CHECK: vcvt.s32.f32 q0, q0 @ encoding: [0xbb,0xff,0x40,0x07]
266 # CHECK-NOFP-NOT: vcvt.s32.f32 q0, q0 @ encoding: [0xbb,0xff,0x40,0x07]
267 vcvt.s32.f32 q0, q0
268
269 # CHECK: vcvt.u32.f32 q0, q2 @ encoding: [0xbb,0xff,0xc4,0x07]
270 # CHECK-NOFP-NOT: vcvt.u32.f32 q0, q2 @ encoding: [0xbb,0xff,0xc4,0x07]
271 vcvt.u32.f32 q0, q2
272
273 # CHECK: vcvta.s16.f16 q0, q7 @ encoding: [0xb7,0xff,0x4e,0x00]
274 # CHECK-NOFP-NOT: vcvta.s16.f16 q0, q7 @ encoding: [0xb7,0xff,0x4e,0x00]
275 vcvta.s16.f16 q0, q7
276
277 # CHECK: vcvta.s32.f32 s2, s3 @ encoding: [0xbc,0xfe,0xe1,0x1a]
278 # CHECK-NOFP-NOT: vcvta.s32.f32 s2, s3 @ encoding: [0xbc,0xfe,0xe1,0x1a]
279 vcvta.s32.f32 s2, s3
280
281 # CHECK: vcvta.s16.f16 q0, q7 @ encoding: [0xb7,0xff,0x4e,0x00]
282 # CHECK-NOFP-NOT: vcvta.s16.f16 q0, q7 @ encoding: [0xb7,0xff,0x4e,0x00]
283 vcvta.s16.f16 q0, q7
284
285 # CHECK: vcvtn.u32.f32 q7, q6 @ encoding: [0xbb,0xff,0xcc,0xe1]
286 # CHECK-NOFP-NOT: vcvtn.u32.f32 q7, q6 @ encoding: [0xbb,0xff,0xcc,0xe1]
287 vcvtn.u32.f32 q7, q6
288
289 # CHECK: vcvtp.s32.f32 q0, q7 @ encoding: [0xbb,0xff,0x4e,0x02]
290 # CHECK-NOFP-NOT: vcvtp.s32.f32 q0, q7 @ encoding: [0xbb,0xff,0x4e,0x02]
291 vcvtp.s32.f32 q0, q7
292
293 # CHECK: vcvtm.u32.f32 q1, q4 @ encoding: [0xbb,0xff,0xc8,0x23]
294 # CHECK-NOFP-NOT: vcvtm.u32.f32 q1, q4 @ encoding: [0xbb,0xff,0xc8,0x23]
295 vcvtm.u32.f32 q1, q4
296
297 # CHECK: vneg.f16 q0, q7 @ encoding: [0xb5,0xff,0xce,0x07]
298 # CHECK-NOFP-NOT: vneg.f16 q0, q7 @ encoding: [0xb5,0xff,0xce,0x07]
299 vneg.f16 q0, q7
300
301 # CHECK: vneg.f32 q0, q2 @ encoding: [0xb9,0xff,0xc4,0x07]
302 # CHECK-NOFP-NOT: vneg.f32 q0, q2 @ encoding: [0xb9,0xff,0xc4,0x07]
303 vneg.f32 q0, q2
304
305 # CHECK: vabs.f16 q0, q2 @ encoding: [0xb5,0xff,0x44,0x07]
306 # CHECK-NOFP-NOT: vabs.f16 q0, q2 @ encoding: [0xb5,0xff,0x44,0x07]
307 vabs.f16 q0, q2
308
309 # CHECK: vabs.f32 q0, q0 @ encoding: [0xb9,0xff,0x40,0x07]
310 # CHECK-NOFP-NOT: vabs.f32 q0, q0 @ encoding: [0xb9,0xff,0x40,0x07]
311 vabs.f32 q0, q0
312
313 # CHECK: vmaxnma.f16 q1, q1 @ encoding: [0x3f,0xfe,0x83,0x2e]
314 # CHECK-NOFP-NOT: vmaxnma.f16 q1, q1 @ encoding: [0x3f,0xfe,0x83,0x2e]
315 vmaxnma.f16 q1, q1
316
317 # CHECK: vmaxnma.f32 q2, q6 @ encoding: [0x3f,0xee,0x8d,0x4e]
318 # CHECK-NOFP-NOT: vmaxnma.f32 q2, q6 @ encoding: [0x3f,0xee,0x8d,0x4e]
319 vmaxnma.f32 q2, q6
320
321 # CHECK: vminnma.f16 q0, q2 @ encoding: [0x3f,0xfe,0x85,0x1e]
322 # CHECK-NOFP-NOT: vminnma.f16 q0, q2 @ encoding: [0x3f,0xfe,0x85,0x1e]
323 vminnma.f16 q0, q2
324
325 # CHECK: vminnma.f32 q0, q1 @ encoding: [0x3f,0xee,0x83,0x1e]
326 # CHECK-NOFP-NOT: vminnma.f32 q0, q1 @ encoding: [0x3f,0xee,0x83,0x1e]
327 vminnma.f32 q0, q1
328
329 it eq
330 vaddeq.f32 s0, s1
331 # CHECK: it eq @ encoding: [0x08,0xbf]
332 # CHECK: vaddeq.f32 s0, s0, s1 @ encoding: [0x30,0xee,0x20,0x0a]
333 # CHECK-NOFP-NOT: vaddeq.f32 s0, s0, s1 @ encoding: [0x30,0xee,0x20,0x0a]
334
335 vpst
336 vaddt.f16 q0, q1, q2
337 # CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
338 # CHECK: vaddt.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0d]
339 # CHECK-NOFP-NOT: vaddt.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x0d]
340
341 vpste
342 vcvtmt.u32.f32 q0, q1
343 vcvtne.s32.f32 q0, q1
344 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
345 # CHECK: vtmt.u32.f32 q0, q1 @ encoding: [0xbb,0xff,0xc2,0x03]
346 # CHECK-NOFP-NOT: vtmt.u32.f32 q0, q1 @ encoding: [0xbb,0xff,0xc2,0x03]
347 # CHECK: vcvtne.s32.f32 q0, q1 @ encoding: [0xbb,0xff,0x42,0x01]
348 # CHECK-NOFP-NOT: vcvtne.s32.f32 q0, q1 @ encoding: [0xbb,0xff,0x42,0x01]
349
350 it ne
351 vcvtne.s32.f32 s0, s1
352 # CHECK: it ne @ encoding: [0x18,0xbf]
353 # CHECK: vcvtne.s32.f32 s0, s1 @ encoding: [0xbd,0xee,0xe0,0x0a]
354 # CHECK-NOFP-NOT: vcvtne.s32.f32 s0, s1 @ encoding: [0xbd,0xee,0xe0,0x0a]
355
356 it ge
357 vcvttge.f64.f16 d3, s1
358 # CHECK: it ge @ encoding: [0xa8,0xbf]
359 # CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
360 # CHECK-NOFP-NOT: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
361
362 # ----------------------------------------------------------------------
363 # The following tests have to go last because of the NOFP-NOT checks inside the
364 # VPT block.
365
366 vpte.f32 lt, q3, r1
367 vcvtt.u32.f32 q2, q0
368 vcvte.u32.f32 q1, q0
369 # CHECK: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xc1,0x9f]
370 # CHECK-NOFP-NOT: vpte.f32 lt, q3, r1 @ encoding: [0x77,0xee,0xe1,0x8f]
371 # CHECK: vcvtt.u32.f32 q2, q0 @ encoding: [0xbb,0xff,0xc0,0x47]
372 # CHECK-NOFP-NOT: vcvtt.u32.f32 q2, q0 @ encoding: [0xbb,0xff,0xc0,0x47]
373 # CHECK: vcvte.u32.f32 q1, q0 @ encoding: [0xbb,0xff,0xc0,0x27]
374 # CHECK-NOFP-NOT: vcvte.u32.f32 q1, q0 @ encoding: [0xbb,0xff,0xc0,0x27]
375
376 ite eq
377 vcvteq.u32.f32 s0, s1
378 vcvtne.f32.u32 s0, s1
379 # CHECK: ite eq @ encoding: [0x0c,0xbf]
380 # CHECK: vcvteq.u32.f32 s0, s1 @ encoding: [0xbc,0xee,0xe0,0x0a]
381 # CHECK-NOFP-NOT: vcvteq.u32.f32 s0, s1 @ encoding: [0xbc,0xee,0xe0,0x0a]
382 # CHECK: vcvtne.f32.u32 s0, s1 @ encoding: [0xb8,0xee,0x60,0x0a]
383 # CHECK-NOFP-NOT: vcvtne.f32.u32 s0, s1 @ encoding: [0xb8,0xee,0x60,0x0a]
384
385 vpste
386 vmult.f16 q0, q1, q2
387 vmule.f16 q0, q1, q2
388 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
389 # CHECK: vmult.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d]
390 # CHECK-NOFP-NOT: vmult.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d]
391 # CHECK: vmule.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d]
392 # CHECK-NOFP-NOT: vmule.f16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x0d]
393
394 ite eq
395 vmuleq.f64 d0, d0, d1
396 vmulne.f64 d1, d0, d2
397 # CHECK: ite eq @ encoding: [0x0c,0xbf]
398 # CHECK: vmuleq.f64 d0, d0, d1 @ encoding: [0x20,0xee,0x01,0x0b]
399 # CHECK-NOFP-NOT: vmuleq.f64 d0, d0, d1 @ encoding: [0x20,0xee,0x01,0x0b]
400 # CHECK: vmulne.f64 d1, d0, d2 @ encoding: [0x20,0xee,0x02,0x1b]
401 # CHECK-NOFP-NOT: vmulne.f64 d1, d0, d2 @ encoding: [0x20,0xee,0x02,0x1b]
402
403 it eq
404 vnegeq.f32 s0, s1
405 # CHECK: it eq @ encoding: [0x08,0xbf]
406 # CHECK: vnegeq.f32 s0, s1 @ encoding: [0xb1,0xee,0x60,0x0a]
407 # CHECK-NOFP-NOT: vnegeq.f32 s0, s1 @ encoding: [0xb1,0xee,0x60,0x0a]
408
409 itt eq
410 vnmuleq.f32 s0, s1, s2
411 vmuleq.f32 s0, s1, s2
412 # CHECK: itt eq @ encoding: [0x04,0xbf]
413 # CHECK: vnmuleq.f32 s0, s1, s2 @ encoding: [0x20,0xee,0xc1,0x0a]
414 # CHECK-NOFP-NOT: vnmuleq.f32 s0, s1, s2 @ encoding: [0x20,0xee,0xc1,0x0a]
415 # CHECK: vmuleq.f32 s0, s1, s2 @ encoding: [0x20,0xee,0x81,0x0a]
416 # CHECK-NOFP-NOT: vmuleq.f32 s0, s1, s2 @ encoding: [0x20,0xee,0x81,0x0a]
417
418 vpste
419 vrintnt.f16 q0, q1
420 vrintne.f32 q0, q1
421 # CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
422 # CHECK: vrintnt.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x04]
423 # CHECK-NOFP-NOT: vrintnt.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x04]
424 # CHECK: vrintne.f32 q0, q1 @ encoding: [0xba,0xff,0x42,0x04]
425 # CHECK-NOFP-NOT: vrintne.f32 q0, q1 @ encoding: [0xba,0xff,0x42,0x04]
0 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
1 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
2 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
3
4 # CHECK: vrintn.f16 q1, q0 @ encoding: [0xb6,0xff,0x40,0x24]
5 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
6 [0xb6,0xff,0x40,0x24]
7
8 # CHECK: vrintn.f32 q0, q4 @ encoding: [0xba,0xff,0x48,0x04]
9 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
10 [0xba,0xff,0x48,0x04]
11
12 # CHECK: vrinta.f16 q0, q1 @ encoding: [0xb6,0xff,0x42,0x05]
13 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
14 [0xb6,0xff,0x42,0x05]
15
16 # CHECK: vrinta.f32 q1, q3 @ encoding: [0xba,0xff,0x46,0x25]
17 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
18 [0xba,0xff,0x46,0x25]
19
20 # CHECK: vrintm.f16 q0, q5 @ encoding: [0xb6,0xff,0xca,0x06]
21 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
22 [0xb6,0xff,0xca,0x06]
23
24 # CHECK: vrintm.f32 q0, q4 @ encoding: [0xba,0xff,0xc8,0x06]
25 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
26 [0xba,0xff,0xc8,0x06]
27
28 # CHECK: vrintp.f16 q1, q0 @ encoding: [0xb6,0xff,0xc0,0x27]
29 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
30 [0xb6,0xff,0xc0,0x27]
31
32 # CHECK: vrintp.f32 q0, q1 @ encoding: [0xba,0xff,0xc2,0x07]
33 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
34 [0xba,0xff,0xc2,0x07]
35
36 # CHECK: vrintx.f16 q1, q2 @ encoding: [0xb6,0xff,0xc4,0x24]
37 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
38 [0xb6,0xff,0xc4,0x24]
39
40 # CHECK: vrintx.f32 q1, q1 @ encoding: [0xba,0xff,0xc2,0x24]
41 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
42 [0xba,0xff,0xc2,0x24]
43
44 # CHECK: vrintz.f16 q1, q6 @ encoding: [0xb6,0xff,0xcc,0x25]
45 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
46 [0xb6,0xff,0xcc,0x25]
47
48 # CHECK: vrintz.f32 q1, q0 @ encoding: [0xba,0xff,0xc0,0x25]
49 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
50 [0xba,0xff,0xc0,0x25]
51
52 # CHECK: vrintr.f32 s0, s1 @ encoding: [0xb6,0xee,0x60,0x0a]
53 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
54 [0xb6,0xee,0x60,0x0a]
55
56 # CHECK: vrintr.f64 d0, d1 @ encoding: [0xb6,0xee,0x41,0x0b]
57 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
58 [0xb6,0xee,0x41,0x0b]
59
60 # CHECK: vmul.f16 q2, q1, q3 @ encoding: [0x12,0xff,0x56,0x4d]
61 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
62 [0x12,0xff,0x56,0x4d]
63
64 # CHECK: vmul.f32 q0, q0, q5 @ encoding: [0x00,0xff,0x5a,0x0d]
65 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
66 [0x00,0xff,0x5a,0x0d]
67
68 # CHECK: vfma.f16 q0, q2, q3 @ encoding: [0x14,0xef,0x56,0x0c]
69 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
70 [0x14,0xef,0x56,0x0c]
71
72 # CHECK: vfma.f32 q0, q3, q7 @ encoding: [0x06,0xef,0x5e,0x0c]
73 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
74 [0x06,0xef,0x5e,0x0c]
75
76 # CHECK: vfms.f16 q0, q2, q5 @ encoding: [0x34,0xef,0x5a,0x0c]
77 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
78 [0x34,0xef,0x5a,0x0c]
79
80 # CHECK: vfms.f32 q1, q1, q2 @ encoding: [0x22,0xef,0x54,0x2c]
81 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
82 [0x22,0xef,0x54,0x2c]
83
84 # CHECK: vadd.f16 q0, q0, q5 @ encoding: [0x10,0xef,0x4a,0x0d]
85 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
86 [0x10,0xef,0x4a,0x0d]
87
88 # CHECK: vadd.f32 q1, q3, q0 @ encoding: [0x06,0xef,0x40,0x2d]
89 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
90 [0x06,0xef,0x40,0x2d]
91
92 # CHECK: vcadd.f16 q2, q1, q7, #90 @ encoding: [0x82,0xfc,0x4e,0x48]
93 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
94 [0x82,0xfc,0x4e,0x48]
95
96 # CHECK: vcadd.f16 q2, q5, q7, #270 @ encoding: [0x8a,0xfd,0x4e,0x48]
97 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
98 [0x8a,0xfd,0x4e,0x48]
99
100 # CHECK: vcadd.f32 q0, q4, q7, #90 @ encoding: [0x98,0xfc,0x4e,0x08]
101 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
102 [0x98,0xfc,0x4e,0x08]
103
104 # CHECK: vcadd.f32 q2, q2, q3, #270 @ encoding: [0x94,0xfd,0x46,0x48]
105 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
106 [0x94,0xfd,0x46,0x48]
107
108 # CHECK: vabd.f16 q0, q0, q6 @ encoding: [0x30,0xff,0x4c,0x0d]
109 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
110 [0x30,0xff,0x4c,0x0d]
111
112 # CHECK: vabd.f32 q0, q1, q4 @ encoding: [0x22,0xff,0x48,0x0d]
113 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
114 [0x22,0xff,0x48,0x0d]
115
116 # CHECK: vcvt.f16.s16 q0, q1 @ encoding: [0xb7,0xff,0x42,0x06]
117 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
118 [0xb7,0xff,0x42,0x06]
119
120 # CHECK: vcvt.f16.u16 q0, q4 @ encoding: [0xb7,0xff,0xc8,0x06]
121 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
122 [0xb7,0xff,0xc8,0x06]
123
124 # CHECK: vcvt.s16.f16 q0, q0 @ encoding: [0xb7,0xff,0x40,0x07]
125 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
126 [0xb7,0xff,0x40,0x07]
127
128 # CHECK: vcvt.u16.f16 q0, q0 @ encoding: [0xb7,0xff,0xc0,0x07]
129 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
130 [0xb7,0xff,0xc0,0x07]
131
132 # CHECK: vcvt.f32.s32 q0, q0 @ encoding: [0xbb,0xff,0x40,0x06]
133 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
134 [0xbb,0xff,0x40,0x06]
135
136 # CHECK: vcvt.f32.u32 q0, q0 @ encoding: [0xbb,0xff,0xc0,0x06]
137 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
138 [0xbb,0xff,0xc0,0x06]
139
140 # CHECK: vcvt.s32.f32 q0, q0 @ encoding: [0xbb,0xff,0x40,0x07]
141 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
142 [0xbb,0xff,0x40,0x07]
143
144 # CHECK: vcvt.u32.f32 q0, q2 @ encoding: [0xbb,0xff,0xc4,0x07]
145 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
146 [0xbb,0xff,0xc4,0x07]
147
148 # CHECK: vcvta.s16.f16 q0, q7 @ encoding: [0xb7,0xff,0x4e,0x00]
149 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
150 [0xb7,0xff,0x4e,0x00]
151
152 # CHECK: vcvtn.u32.f32 q7, q6 @ encoding: [0xbb,0xff,0xcc,0xe1]
153 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
154 [0xbb,0xff,0xcc,0xe1]
155
156 # CHECK: vcvtp.s32.f32 q0, q7 @ encoding: [0xbb,0xff,0x4e,0x02]
157 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
158 [0xbb,0xff,0x4e,0x02]
159
160 # CHECK: vcvtm.u32.f32 q1, q4 @ encoding: [0xbb,0xff,0xc8,0x23]
161 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
162 [0xbb,0xff,0xc8,0x23]
163
164 # CHECK: vneg.f16 q0, q7 @ encoding: [0xb5,0xff,0xce,0x07]
165 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
166 [0xb5,0xff,0xce,0x07]
167
168 # CHECK: vneg.f32 q0, q2 @ encoding: [0xb9,0xff,0xc4,0x07]
169 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
170 [0xb9,0xff,0xc4,0x07]
171
172 # CHECK: vabs.f16 q0, q2 @ encoding: [0xb5,0xff,0x44,0x07]
173 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
174 [0xb5,0xff,0x44,0x07]
175
176 # CHECK: vabs.f32 q0, q0 @ encoding: [0xb9,0xff,0x40,0x07]
177 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
178 [0xb9,0xff,0x40,0x07]
179
180 # CHECK: vmaxnma.f16 q1, q1 @ encoding: [0x3f,0xfe,0x83,0x2e]
181 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
182 [0x3f,0xfe,0x83,0x2e]
183
184 # CHECK: vmaxnma.f32 q2, q6 @ encoding: [0x3f,0xee,0x8d,0x4e]
185 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
186 [0x3f,0xee,0x8d,0x4e]
187
188 # CHECK: vminnma.f16 q0, q2 @ encoding: [0x3f,0xfe,0x85,0x1e]
189 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
190 [0x3f,0xfe,0x85,0x1e]
191
192 # CHECK: vminnma.f32 q0, q1 @ encoding: [0x3f,0xee,0x83,0x1e]
193 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
194 [0x3f,0xee,0x83,0x1e]