llvm.org GIT mirror llvm / ac8db59
Delete Reloc::Default. Having an enum member named Default is quite confusing: Is it distinct from the others? This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269988 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 3 years ago
55 changed file(s) with 319 addition(s) and 228 deletion(s). Raw diff Collapse all Expand all
4747
4848 cl::opt RelocModel(
4949 "relocation-model", cl::desc("Choose relocation model"),
50 cl::init(Reloc::Default),
5150 cl::values(
52 clEnumValN(Reloc::Default, "default",
53 "Target default relocation model"),
5451 clEnumValN(Reloc::Static, "static", "Non-relocatable code"),
5552 clEnumValN(Reloc::PIC_, "pic",
5653 "Fully relocatable, position independent code"),
5754 clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
5855 "Relocatable external references, non-relocatable code"),
5956 clEnumValEnd));
57
58 static inline Optional getRelocModel() {
59 if (RelocModel.getNumOccurrences()) {
60 Reloc::Model R = RelocModel;
61 return R;
62 }
63 return None;
64 }
6065
6166 cl::opt
6267 TMModel("thread-model",
518518 std::shared_ptr MemMgr;
519519 std::shared_ptr Resolver;
520520 TargetOptions Options;
521 Reloc::Model RelocModel;
521 Optional RelocModel;
522522 CodeModel::Model CMModel;
523523 std::string MArch;
524524 std::string MCPU;
7878
7979 void setTargetOptions(TargetOptions Options);
8080 void setDebugInfo(lto_debug_model);
81 void setCodePICModel(Reloc::Model Model) { RelocModel = Model; }
81 void setCodePICModel(Optional Model) { RelocModel = Model; }
8282
8383 /// Set the file type to be emitted (assembly or object code).
8484 /// The default is TargetMachine::CGFT_ObjectFile.
210210 bool EmitDwarfDebugInfo = false;
211211 bool ScopeRestrictionsDone = false;
212212 bool HasVerifiedInput = false;
213 Reloc::Model RelocModel = Reloc::Default;
213 Optional RelocModel;
214214 StringSet<> MustPreserveSymbols;
215215 StringSet<> AsmUndefinedRefs;
216216 StringMap ExternalSymbols;
3636 std::string MCpu;
3737 std::string MAttr;
3838 TargetOptions Options;
39 Reloc::Model RelocModel = Reloc::Default;
39 Optional RelocModel;
4040 CodeGenOpt::Level CGOptLevel = CodeGenOpt::Default;
4141
4242 std::unique_ptr create() const;
167167 }
168168
169169 /// CodeModel
170 void setCodePICModel(Reloc::Model Model) { TMBuilder.RelocModel = Model; }
170 void setCodePICModel(Optional Model) {
171 TMBuilder.RelocModel = Model;
172 }
171173
172174 /// CodeGen optimization level
173175 void setCodeGenOptLevel(CodeGenOpt::Level CGOptLevel) {
1818
1919 // Relocation model types.
2020 namespace Reloc {
21 enum Model { Default, Static, PIC_, DynamicNoPIC };
21 enum Model { Static, PIC_, DynamicNoPIC };
2222 }
2323
2424 // Code model types.
1919 #define LLVM_SUPPORT_TARGETREGISTRY_H
2020
2121 #include "llvm-c/Disassembler.h"
22 #include "llvm/ADT/Optional.h"
2223 #include "llvm/ADT/Triple.h"
2324 #include "llvm/Support/CodeGen.h"
2425 #include "llvm/Support/FormattedStream.h"
103104 StringRef Features);
104105 typedef TargetMachine *(*TargetMachineCtorTy)(
105106 const Target &T, const Triple &TT, StringRef CPU, StringRef Features,
106 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
107 CodeGenOpt::Level OL);
107 const TargetOptions &Options, Optional RM,
108 CodeModel::Model CM, CodeGenOpt::Level OL);
108109 // If it weren't for layering issues (this header is in llvm/Support, but
109110 // depends on MC?) this should take the Streamer by value rather than rvalue
110111 // reference.
358359 /// host if that does not exist.
359360 TargetMachine *
360361 createTargetMachine(StringRef TT, StringRef CPU, StringRef Features,
361 const TargetOptions &Options,
362 Reloc::Model RM = Reloc::Default,
362 const TargetOptions &Options, Optional RM,
363363 CodeModel::Model CM = CodeModel::Default,
364364 CodeGenOpt::Level OL = CodeGenOpt::Default) const {
365365 if (!TargetMachineCtorFn)
10961096 private:
10971097 static TargetMachine *Allocator(const Target &T, const Triple &TT,
10981098 StringRef CPU, StringRef FS,
1099 const TargetOptions &Options, Reloc::Model RM,
1099 const TargetOptions &Options,
1100 Optional RM,
11001101 CodeModel::Model CM, CodeGenOpt::Level OL) {
11011102 return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL);
11021103 }
473473 EngineBuilder::EngineBuilder(std::unique_ptr M)
474474 : M(std::move(M)), WhichEngine(EngineKind::Either), ErrorStr(nullptr),
475475 OptLevel(CodeGenOpt::Default), MemMgr(nullptr), Resolver(nullptr),
476 RelocModel(Reloc::Default), CMModel(CodeModel::JITDefault),
477 UseOrcMCJITReplacement(false) {
476 CMModel(CodeModel::JITDefault), UseOrcMCJITReplacement(false) {
478477 // IR module verification is enabled by default in debug builds, and disabled
479478 // by default in release builds.
480479 #ifndef NDEBUG
229229 CPU = "cyclone";
230230 }
231231
232 TargetMachine *target = march->createTargetMachine(TripleStr, CPU, FeatureStr,
233 options);
232 TargetMachine *target =
233 march->createTargetMachine(TripleStr, CPU, FeatureStr, options, None);
234234 M->setDataLayout(target->createDataLayout());
235235
236236 std::unique_ptr IRObj(
160160 TM.Options.Reciprocals.setDefaults("vec-divd", false, ExtraStepsD);
161161 }
162162
163 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
164 Optional RM) {
165 // AArch64 Darwin is always PIC.
166 if (TT.isOSDarwin())
167 return Reloc::PIC_;
168 // On ELF platforms the default static relocation model has a smart enough
169 // linker to cope with referencing external symbols defined in a shared
170 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
171 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
172 return Reloc::Static;
173 return *RM;
174 }
175
163176 /// Create an AArch64 architecture model.
164177 ///
165 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
166 StringRef CPU, StringRef FS,
167 const TargetOptions &Options,
168 Reloc::Model RM, CodeModel::Model CM,
169 CodeGenOpt::Level OL,
170 bool LittleEndian)
178 AArch64TargetMachine::AArch64TargetMachine(
179 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
180 const TargetOptions &Options, Optional RM,
181 CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian)
171182 // This nested ternary is horrible, but DL needs to be properly
172183 // initialized before TLInfo is constructed.
173184 : LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS,
174 Options, RM, CM, OL),
185 Options, getEffectiveRelocModel(TT, RM), CM, OL),
175186 TLOF(createTLOF(getTargetTriple())),
176187 Subtarget(TT, CPU, FS, *this, LittleEndian) {
177188 initReciprocals(*this, Subtarget);
234245
235246 AArch64leTargetMachine::AArch64leTargetMachine(
236247 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
237 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
238 CodeGenOpt::Level OL)
248 const TargetOptions &Options, Optional RM,
249 CodeModel::Model CM, CodeGenOpt::Level OL)
239250 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
240251
241252 void AArch64beTargetMachine::anchor() { }
242253
243254 AArch64beTargetMachine::AArch64beTargetMachine(
244255 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
245 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
246 CodeGenOpt::Level OL)
256 const TargetOptions &Options, Optional RM,
257 CodeModel::Model CM, CodeGenOpt::Level OL)
247258 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
248259
249260 namespace {
2828 public:
2929 AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
3030 StringRef FS, const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM,
31 Optional RM, CodeModel::Model CM,
3232 CodeGenOpt::Level OL, bool IsLittleEndian);
3333
3434 ~AArch64TargetMachine() override;
5555 public:
5656 AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
5757 StringRef FS, const TargetOptions &Options,
58 Reloc::Model RM, CodeModel::Model CM,
58 Optional RM, CodeModel::Model CM,
5959 CodeGenOpt::Level OL);
6060 };
6161
6666 public:
6767 AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
6868 StringRef FS, const TargetOptions &Options,
69 Reloc::Model RM, CodeModel::Model CM,
69 Optional RM, CodeModel::Model CM,
7070 CodeGenOpt::Level OL);
7171 };
7272
8989 report_fatal_error(
9090 "Only small and large code models are allowed on AArch64");
9191
92 // AArch64 Darwin is always PIC.
93 if (TT.isOSDarwin())
94 RM = Reloc::PIC_;
95 // On ELF platforms the default static relocation model has a smart enough
96 // linker to cope with referencing external symbols defined in a shared
97 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
98 else if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
99 RM = Reloc::Static;
100
10192 MCCodeGenInfo *X = new MCCodeGenInfo();
10293 X->initMCCodeGenInfo(RM, CM, OL);
10394 return X;
102102 return "";
103103 }
104104
105 static Reloc::Model getEffectiveRelocModel(Optional RM) {
106 if (!RM.hasValue())
107 return Reloc::PIC_;
108 return *RM;
109 }
110
105111 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
106112 StringRef CPU, StringRef FS,
107 TargetOptions Options, Reloc::Model RM,
113 TargetOptions Options,
114 Optional RM,
108115 CodeModel::Model CM,
109116 CodeGenOpt::Level OptLevel)
110 : LLVMTargetMachine(T, computeDataLayout(TT), TT,
111 getGPUOrDefault(TT, CPU), FS, Options, RM, CM,
112 OptLevel),
117 : LLVMTargetMachine(T, computeDataLayout(TT), TT, getGPUOrDefault(TT, CPU),
118 FS, Options, getEffectiveRelocModel(RM), CM, OptLevel),
113119 TLOF(createTLOF(getTargetTriple())),
114 Subtarget(TT, getTargetCPU(), FS, *this),
115 IntrinsicInfo() {
120 Subtarget(TT, getTargetCPU(), FS, *this), IntrinsicInfo() {
116121 setRequiresStructuredCFG(true);
117122 initAsmInfo();
118123 }
125130
126131 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
127132 StringRef CPU, StringRef FS,
128 TargetOptions Options, Reloc::Model RM,
133 TargetOptions Options,
134 Optional RM,
129135 CodeModel::Model CM, CodeGenOpt::Level OL)
130136 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
131137
135141
136142 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
137143 StringRef CPU, StringRef FS,
138 TargetOptions Options, Reloc::Model RM,
144 TargetOptions Options,
145 Optional RM,
139146 CodeModel::Model CM, CodeGenOpt::Level OL)
140147 : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
141148
3737
3838 public:
3939 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
40 StringRef FS, TargetOptions Options, Reloc::Model RM,
41 CodeModel::Model CM, CodeGenOpt::Level OL);
40 StringRef FS, TargetOptions Options,
41 Optional RM, CodeModel::Model CM,
42 CodeGenOpt::Level OL);
4243 ~AMDGPUTargetMachine();
4344
4445 const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; }
6364
6465 public:
6566 R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
66 StringRef FS, TargetOptions Options, Reloc::Model RM,
67 CodeModel::Model CM, CodeGenOpt::Level OL);
67 StringRef FS, TargetOptions Options,
68 Optional RM, CodeModel::Model CM,
69 CodeGenOpt::Level OL);
6870
6971 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
7072 };
7779
7880 public:
7981 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
80 StringRef FS, TargetOptions Options, Reloc::Model RM,
81 CodeModel::Model CM, CodeGenOpt::Level OL);
82 StringRef FS, TargetOptions Options,
83 Optional RM, CodeModel::Model CM,
84 CodeGenOpt::Level OL);
8285
8386 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
8487 };
171171 return Ret;
172172 }
173173
174 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
175 Optional RM) {
176 if (!RM.hasValue())
177 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
178 return TT.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
179 return *RM;
180 }
181
174182 /// Create an ARM architecture model.
175183 ///
176184 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
177185 StringRef CPU, StringRef FS,
178186 const TargetOptions &Options,
179 Reloc::Model RM, CodeModel::Model CM,
187 Optional RM,
188 CodeModel::Model CM,
180189 CodeGenOpt::Level OL, bool isLittle)
181190 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
182 CPU, FS, Options, RM, CM, OL),
191 CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM,
192 OL),
183193 TargetABI(computeTargetABI(TT, CPU, Options)),
184194 TLOF(createTLOF(getTargetTriple())),
185195 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
247257 ARMTargetMachine::ARMTargetMachine(const Target &T, const Triple &TT,
248258 StringRef CPU, StringRef FS,
249259 const TargetOptions &Options,
250 Reloc::Model RM, CodeModel::Model CM,
251 CodeGenOpt::Level OL, bool isLittle)
260 Optional RM,
261 CodeModel::Model CM, CodeGenOpt::Level OL,
262 bool isLittle)
252263 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
253264 initAsmInfo();
254265 if (!Subtarget.hasARMOps())
261272 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
262273 StringRef CPU, StringRef FS,
263274 const TargetOptions &Options,
264 Reloc::Model RM, CodeModel::Model CM,
275 Optional RM,
276 CodeModel::Model CM,
265277 CodeGenOpt::Level OL)
266278 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
267279
270282 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
271283 StringRef CPU, StringRef FS,
272284 const TargetOptions &Options,
273 Reloc::Model RM, CodeModel::Model CM,
285 Optional RM,
286 CodeModel::Model CM,
274287 CodeGenOpt::Level OL)
275288 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
276289
279292 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Triple &TT,
280293 StringRef CPU, StringRef FS,
281294 const TargetOptions &Options,
282 Reloc::Model RM, CodeModel::Model CM,
295 Optional RM,
296 CodeModel::Model CM,
283297 CodeGenOpt::Level OL, bool isLittle)
284298 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
285299 initAsmInfo();
290304 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, const Triple &TT,
291305 StringRef CPU, StringRef FS,
292306 const TargetOptions &Options,
293 Reloc::Model RM, CodeModel::Model CM,
307 Optional RM,
308 CodeModel::Model CM,
294309 CodeGenOpt::Level OL)
295310 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
296311
299314 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, const Triple &TT,
300315 StringRef CPU, StringRef FS,
301316 const TargetOptions &Options,
302 Reloc::Model RM, CodeModel::Model CM,
317 Optional RM,
318 CodeModel::Model CM,
303319 CodeGenOpt::Level OL)
304320 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
305321
3838 public:
3939 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
4040 StringRef FS, const TargetOptions &Options,
41 Reloc::Model RM, CodeModel::Model CM,
41 Optional RM, CodeModel::Model CM,
4242 CodeGenOpt::Level OL, bool isLittle);
4343 ~ARMBaseTargetMachine() override;
4444
6363 virtual void anchor();
6464 public:
6565 ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
66 StringRef FS, const TargetOptions &Options, Reloc::Model RM,
67 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
66 StringRef FS, const TargetOptions &Options,
67 Optional RM, CodeModel::Model CM,
68 CodeGenOpt::Level OL, bool isLittle);
6869 };
6970
7071 /// ARM little endian target machine.
7475 public:
7576 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
7677 StringRef FS, const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
78 Optional RM, CodeModel::Model CM,
7879 CodeGenOpt::Level OL);
7980 };
8081
8586 public:
8687 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
8788 StringRef FS, const TargetOptions &Options,
88 Reloc::Model RM, CodeModel::Model CM,
89 Optional RM, CodeModel::Model CM,
8990 CodeGenOpt::Level OL);
9091 };
9192
9899 public:
99100 ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
100101 StringRef FS, const TargetOptions &Options,
101 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
102 bool isLittle);
102 Optional RM, CodeModel::Model CM,
103 CodeGenOpt::Level OL, bool isLittle);
103104 };
104105
105106 /// Thumb little endian target machine.
109110 public:
110111 ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
111112 StringRef FS, const TargetOptions &Options,
112 Reloc::Model RM, CodeModel::Model CM,
113 Optional RM, CodeModel::Model CM,
113114 CodeGenOpt::Level OL);
114115 };
115116
120121 public:
121122 ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
122123 StringRef FS, const TargetOptions &Options,
123 Reloc::Model RM, CodeModel::Model CM,
124 Optional RM, CodeModel::Model CM,
124125 CodeGenOpt::Level OL);
125126 };
126127
204204 CodeModel::Model CM,
205205 CodeGenOpt::Level OL) {
206206 MCCodeGenInfo *X = new MCCodeGenInfo();
207 if (RM == Reloc::Default) {
208 // Default relocation model on Darwin is PIC, not DynamicNoPIC.
209 RM = TT.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
210 }
211207 X->initMCCodeGenInfo(RM, CM, OL);
212208 return X;
213209 }
3636 return "e-m:e-p:64:64-i64:64-n32:64-S128";
3737 }
3838
39 static Reloc::Model getEffectiveRelocModel(Optional RM) {
40 if (!RM.hasValue())
41 return Reloc::PIC_;
42 return *RM;
43 }
44
3945 BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
4046 StringRef CPU, StringRef FS,
4147 const TargetOptions &Options,
42 Reloc::Model RM, CodeModel::Model CM,
43 CodeGenOpt::Level OL)
44 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
45 OL),
48 Optional RM,
49 CodeModel::Model CM, CodeGenOpt::Level OL)
50 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
51 getEffectiveRelocModel(RM), CM, OL),
4652 TLOF(make_unique()),
4753 Subtarget(TT, CPU, FS, *this) {
4854 initAsmInfo();
2323
2424 public:
2525 BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
26 StringRef FS, const TargetOptions &Options, Reloc::Model RM,
27 CodeModel::Model CM, CodeGenOpt::Level OL);
26 StringRef FS, const TargetOptions &Options,
27 Optional RM, CodeModel::Model CM,
28 CodeGenOpt::Level OL);
2829
2930 const BPFSubtarget *getSubtargetImpl() const { return &Subtarget; }
3031 const BPFSubtarget *getSubtargetImpl(const Function &) const override {
129129 FunctionPass *createHexagonStoreWidening();
130130 } // end namespace llvm;
131131
132 static Reloc::Model getEffectiveRelocModel(Optional RM) {
133 if (!RM.hasValue())
134 return Reloc::Static;
135 return *RM;
136 }
132137
133138 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
134139 StringRef CPU, StringRef FS,
135140 const TargetOptions &Options,
136 Reloc::Model RM, CodeModel::Model CM,
141 Optional RM,
142 CodeModel::Model CM,
137143 CodeGenOpt::Level OL)
138144 // Specify the vector alignment explicitly. For v512x1, the calculated
139145 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
140146 // the required minimum of 64 bytes.
141 : LLVMTargetMachine(T, "e-m:e-p:32:32:32-a:0-n16:32-"
142 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
143 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
144 TT, CPU, FS, Options, RM, CM, (HexagonNoOpt ? CodeGenOpt::None : OL)),
147 : LLVMTargetMachine(
148 T, "e-m:e-p:32:32:32-a:0-n16:32-"
149 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
150 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
151 TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
152 (HexagonNoOpt ? CodeGenOpt::None : OL)),
145153 TLOF(make_unique()) {
146154 initAsmInfo();
147155 }
2929 public:
3030 HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
3131 StringRef FS, const TargetOptions &Options,
32 Reloc::Model RM, CodeModel::Model CM,
32 Optional RM, CodeModel::Model CM,
3333 CodeGenOpt::Level OL);
3434 ~HexagonTargetMachine() override;
3535 const HexagonSubtarget *getSubtargetImpl(const Function &F) const override;
203203 CodeModel::Model CM,
204204 CodeGenOpt::Level OL) {
205205 MCCodeGenInfo *X = new MCCodeGenInfo();
206 if (RM == Reloc::Default)
207 RM = Reloc::Static;
208206 X->initMCCodeGenInfo(RM, CM, OL);
209207 return X;
210208 }
2525 RegisterTargetMachine X(TheMSP430Target);
2626 }
2727
28 static Reloc::Model getEffectiveRelocModel(Optional RM) {
29 if (!RM.hasValue())
30 return Reloc::Static;
31 return *RM;
32 }
33
2834 MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT,
2935 StringRef CPU, StringRef FS,
3036 const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM,
37 Optional RM,
38 CodeModel::Model CM,
3239 CodeGenOpt::Level OL)
3340 : LLVMTargetMachine(T, "e-m:e-p:16:16-i32:16:32-a:16-n8:16", TT, CPU, FS,
34 Options, RM, CM, OL),
41 Options, getEffectiveRelocModel(RM), CM, OL),
3542 TLOF(make_unique()),
3643 // FIXME: Check DataLayout string.
3744 Subtarget(TT, CPU, FS, *this) {
2929 public:
3030 MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
3131 StringRef FS, const TargetOptions &Options,
32 Reloc::Model RM, CodeModel::Model CM,
32 Optional RM, CodeModel::Model CM,
3333 CodeGenOpt::Level OL);
3434 ~MSP430TargetMachine() override;
3535
8585 CodeModel::Model CM,
8686 CodeGenOpt::Level OL) {
8787 MCCodeGenInfo *X = new MCCodeGenInfo();
88 if (RM == Reloc::Default || CM == CodeModel::JITDefault)
89 RM = Reloc::Static;
9088 X->initMCCodeGenInfo(RM, CM, OL);
9189 return X;
9290 }
7777 return Ret;
7878 }
7979
80 static Reloc::Model getEffectiveRelocModel(CodeModel::Model CM,
81 Optional RM) {
82 if (!RM.hasValue() || CM == CodeModel::JITDefault)
83 return Reloc::Static;
84 return *RM;
85 }
86
8087 // On function prologue, the stack is created by decrementing
8188 // its pointer. Once decremented, all references are done with positive
8289 // offset from the stack/frame pointer, using StackGrowsUp enables
8592 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
8693 StringRef CPU, StringRef FS,
8794 const TargetOptions &Options,
88 Reloc::Model RM, CodeModel::Model CM,
89 CodeGenOpt::Level OL, bool isLittle)
95 Optional RM,
96 CodeModel::Model CM, CodeGenOpt::Level OL,
97 bool isLittle)
9098 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
91 CPU, FS, Options, RM, CM, OL),
99 CPU, FS, Options, getEffectiveRelocModel(CM, RM), CM,
100 OL),
92101 isLittle(isLittle), TLOF(make_unique()),
93102 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
94103 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
107116 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
108117 StringRef CPU, StringRef FS,
109118 const TargetOptions &Options,
110 Reloc::Model RM, CodeModel::Model CM,
119 Optional RM,
120 CodeModel::Model CM,
111121 CodeGenOpt::Level OL)
112122 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
113123
116126 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
117127 StringRef CPU, StringRef FS,
118128 const TargetOptions &Options,
119 Reloc::Model RM, CodeModel::Model CM,
129 Optional RM,
130 CodeModel::Model CM,
120131 CodeGenOpt::Level OL)
121132 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
122133
3939
4040 public:
4141 MipsTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
42 StringRef FS, const TargetOptions &Options, Reloc::Model RM,
43 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
42 StringRef FS, const TargetOptions &Options,
43 Optional RM, CodeModel::Model CM,
44 CodeGenOpt::Level OL, bool isLittle);
4445 ~MipsTargetMachine() override;
4546
4647 TargetIRAnalysis getTargetIRAnalysis() override;
7475 public:
7576 MipsebTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
7677 StringRef FS, const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
78 Optional RM, CodeModel::Model CM,
7879 CodeGenOpt::Level OL);
7980 };
8081
8586 public:
8687 MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
8788 StringRef FS, const TargetOptions &Options,
88 Reloc::Model RM, CodeModel::Model CM,
89 Optional RM, CodeModel::Model CM,
8990 CodeGenOpt::Level OL);
9091 };
9192
5454 CodeGenOpt::Level OL) {
5555 MCCodeGenInfo *X = new MCCodeGenInfo();
5656
57 // The default relocation model is used regardless of what the client has
58 // specified, as it is the only relocation model currently supported.
59 X->initMCCodeGenInfo(Reloc::Default, CM, OL);
57 X->initMCCodeGenInfo(RM, CM, OL);
6058 return X;
6159 }
6260
9898 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
9999 StringRef CPU, StringRef FS,
100100 const TargetOptions &Options,
101 Reloc::Model RM, CodeModel::Model CM,
101 Optional RM,
102 CodeModel::Model CM,
102103 CodeGenOpt::Level OL, bool is64bit)
103 : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
104 CM, OL),
105 is64bit(is64bit), TLOF(make_unique()),
104 // The pic relocation model is used regardless of what the client has
105 // specified, as it is the only relocation model currently supported.
106 : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options,
107 Reloc::PIC_, CM, OL),
108 is64bit(is64bit),
109 TLOF(make_unique()),
106110 Subtarget(TT, CPU, FS, *this) {
107111 if (TT.getOS() == Triple::NVCL)
108112 drvInterface = NVPTX::NVCL;
118122 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
119123 StringRef CPU, StringRef FS,
120124 const TargetOptions &Options,
121 Reloc::Model RM, CodeModel::Model CM,
125 Optional RM,
126 CodeModel::Model CM,
122127 CodeGenOpt::Level OL)
123128 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
124129
127132 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
128133 StringRef CPU, StringRef FS,
129134 const TargetOptions &Options,
130 Reloc::Model RM, CodeModel::Model CM,
135 Optional RM,
136 CodeModel::Model CM,
131137 CodeGenOpt::Level OL)
132138 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
133139
3535 public:
3636 NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
3737 StringRef FS, const TargetOptions &Options,
38 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OP,
39 bool is64bit);
38 Optional RM, CodeModel::Model CM,
39 CodeGenOpt::Level OP, bool is64bit);
4040
4141 ~NVPTXTargetMachine() override;
4242 const NVPTXSubtarget *getSubtargetImpl(const Function &) const override {
7070 public:
7171 NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
7272 StringRef FS, const TargetOptions &Options,
73 Reloc::Model RM, CodeModel::Model CM,
73 Optional RM, CodeModel::Model CM,
7474 CodeGenOpt::Level OL);
7575 };
7676
7979 public:
8080 NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
8181 StringRef FS, const TargetOptions &Options,
82 Reloc::Model RM, CodeModel::Model CM,
82 Optional RM, CodeModel::Model CM,
8383 CodeGenOpt::Level OL);
8484 };
8585
9191 CodeGenOpt::Level OL) {
9292 MCCodeGenInfo *X = new MCCodeGenInfo();
9393
94 if (RM == Reloc::Default) {
95 if (TT.isOSDarwin())
96 RM = Reloc::DynamicNoPIC;
97 else
98 RM = Reloc::Static;
99 }
10094 if (CM == CodeModel::Default) {
10195 if (!TT.isOSDarwin() &&
10296 (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
177177 return PPCTargetMachine::PPC_ABI_UNKNOWN;
178178 }
179179
180 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
181 Optional RM) {
182 if (!RM.hasValue()) {
183 if (TT.isOSDarwin())
184 return Reloc::DynamicNoPIC;
185 return Reloc::Static;
186 }
187 return *RM;
188 }
189
180190 // The FeatureString here is a little subtle. We are modifying the feature
181191 // string with what are (currently) non-function specific overrides as it goes
182192 // into the LLVMTargetMachine constructor and then using the stored value in the
184194 PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT,
185195 StringRef CPU, StringRef FS,
186196 const TargetOptions &Options,
187 Reloc::Model RM, CodeModel::Model CM,
188 CodeGenOpt::Level OL)
197 Optional RM,
198 CodeModel::Model CM, CodeGenOpt::Level OL)
189199 : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
190 computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
200 computeFSAdditions(FS, OL, TT), Options,
201 getEffectiveRelocModel(TT, RM), CM, OL),
191202 TLOF(createTLOF(getTargetTriple())),
192203 TargetABI(computeTargetABI(TT, Options)),
193204 Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) {
219230 PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Triple &TT,
220231 StringRef CPU, StringRef FS,
221232 const TargetOptions &Options,
222 Reloc::Model RM, CodeModel::Model CM,
233 Optional RM,
234 CodeModel::Model CM,
223235 CodeGenOpt::Level OL)
224236 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
225237
228240 PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Triple &TT,
229241 StringRef CPU, StringRef FS,
230242 const TargetOptions &Options,
231 Reloc::Model RM, CodeModel::Model CM,
243 Optional RM,
244 CodeModel::Model CM,
232245 CodeGenOpt::Level OL)
233246 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
234247
3434
3535 public:
3636 PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
37 StringRef FS, const TargetOptions &Options, Reloc::Model RM,
38 CodeModel::Model CM, CodeGenOpt::Level OL);
37 StringRef FS, const TargetOptions &Options,
38 Optional RM, CodeModel::Model CM,
39 CodeGenOpt::Level OL);
3940
4041 ~PPCTargetMachine() override;
4142
6364 public:
6465 PPC32TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
6566 StringRef FS, const TargetOptions &Options,
66 Reloc::Model RM, CodeModel::Model CM,
67 Optional RM, CodeModel::Model CM,
6768 CodeGenOpt::Level OL);
6869 };
6970
7475 public:
7576 PPC64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
7677 StringRef FS, const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
78 Optional RM, CodeModel::Model CM,
7879 CodeGenOpt::Level OL);
7980 };
8081
5252 return Ret;
5353 }
5454
55 static Reloc::Model getEffectiveRelocModel(Optional RM) {
56 if (!RM.hasValue())
57 return Reloc::Static;
58 return *RM;
59 }
60
5561 /// Create an ILP32 architecture model
5662 ///
5763 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
5864 StringRef CPU, StringRef FS,
5965 const TargetOptions &Options,
60 Reloc::Model RM, CodeModel::Model CM,
66 Optional RM,
67 CodeModel::Model CM,
6168 CodeGenOpt::Level OL, bool is64bit)
6269 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
63 RM, CM, OL),
70 getEffectiveRelocModel(RM), CM, OL),
6471 TLOF(make_unique()) {
6572 initAsmInfo();
6673 this->is64Bit = is64bit;
143150 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
144151 StringRef CPU, StringRef FS,
145152 const TargetOptions &Options,
146 Reloc::Model RM, CodeModel::Model CM,
153 Optional RM,
154 CodeModel::Model CM,
147155 CodeGenOpt::Level OL)
148156 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
149157
152160 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
153161 StringRef CPU, StringRef FS,
154162 const TargetOptions &Options,
155 Reloc::Model RM, CodeModel::Model CM,
163 Optional RM,
164 CodeModel::Model CM,
156165 CodeGenOpt::Level OL)
157166 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
158167
161170 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
162171 StringRef CPU, StringRef FS,
163172 const TargetOptions &Options,
164 Reloc::Model RM, CodeModel::Model CM,
173 Optional RM,
174 CodeModel::Model CM,
165175 CodeGenOpt::Level OL)
166176 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
2626 public:
2727 SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
2828 StringRef FS, const TargetOptions &Options,
29 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
30 bool is64bit);
29 Optional RM, CodeModel::Model CM,
30 CodeGenOpt::Level OL, bool is64bit);
3131 ~SparcTargetMachine() override;
3232
3333 const SparcSubtarget *getSubtargetImpl(const Function &) const override;
4646 public:
4747 SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
4848 StringRef FS, const TargetOptions &Options,
49 Reloc::Model RM, CodeModel::Model CM,
49 Optional RM, CodeModel::Model CM,
5050 CodeGenOpt::Level OL);
5151 };
5252
5757 public:
5858 SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
5959 StringRef FS, const TargetOptions &Options,
60 Reloc::Model RM, CodeModel::Model CM,
60 Optional RM, CodeModel::Model CM,
6161 CodeGenOpt::Level OL);
6262 };
6363
6767 public:
6868 SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
6969 StringRef FS, const TargetOptions &Options,
70 Reloc::Model RM, CodeModel::Model CM,
70 Optional RM, CodeModel::Model CM,
7171 CodeGenOpt::Level OL);
7272 };
7373
163163 CodeModel::Model CM,
164164 CodeGenOpt::Level OL) {
165165 MCCodeGenInfo *X = new MCCodeGenInfo();
166
167 // Static code is suitable for use in a dynamic executable; there is no
168 // separate DynamicNoPIC model.
169 if (RM == Reloc::Default || RM == Reloc::DynamicNoPIC)
170 RM = Reloc::Static;
171
172166 // For SystemZ we define the models as follows:
173167 //
174168 // Small: BRASL can call any function and will use a stub if necessary.
7979 return Ret;
8080 }
8181
82 static Reloc::Model getEffectiveRelocModel(Optional RM) {
83 // Static code is suitable for use in a dynamic executable; there is no
84 // separate DynamicNoPIC model.
85 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
86 return Reloc::Static;
87 return *RM;
88 }
89
8290 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT,
8391 StringRef CPU, StringRef FS,
8492 const TargetOptions &Options,
85 Reloc::Model RM, CodeModel::Model CM,
93 Optional RM,
94 CodeModel::Model CM,
8695 CodeGenOpt::Level OL)
8796 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
88 RM, CM, OL),
97 getEffectiveRelocModel(RM), CM, OL),
8998 TLOF(make_unique()),
9099 Subtarget(TT, CPU, FS, *this) {
91100 initAsmInfo();
2828 public:
2929 SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
3030 StringRef FS, const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM,
31 Optional RM, CodeModel::Model CM,
3232 CodeGenOpt::Level OL);
3333 ~SystemZTargetMachine() override;
3434
7171 }
7272
7373 /// Returns the code generation relocation model. The choices are static, PIC,
74 /// and dynamic-no-pic, and target default.
74 /// and dynamic-no-pic.
7575 Reloc::Model TargetMachine::getRelocationModel() const {
7676 if (!CodeGenInfo)
77 return Reloc::Default;
77 return Reloc::Static; // FIXME
7878 return CodeGenInfo->getRelocationModel();
7979 }
8080
104104 const char* Triple, const char* CPU, const char* Features,
105105 LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc,
106106 LLVMCodeModel CodeModel) {
107 Reloc::Model RM;
107 Optional RM;
108108 switch (Reloc){
109109 case LLVMRelocStatic:
110110 RM = Reloc::Static;
116116 RM = Reloc::DynamicNoPIC;
117117 break;
118118 default:
119 RM = Reloc::Default;
120119 break;
121120 }
122121
202202 MCCodeGenInfo *X = new MCCodeGenInfo();
203203
204204 bool is64Bit = TT.getArch() == Triple::x86_64;
205
206 if (RM == Reloc::Default) {
207 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
208 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
209 // use static relocation model by default.
210 if (TT.isOSDarwin()) {
211 if (is64Bit)
212 RM = Reloc::PIC_;
213 else
214 RM = Reloc::DynamicNoPIC;
215 } else if (TT.isOSWindows() && is64Bit)
216 RM = Reloc::PIC_;
217 else
218 RM = Reloc::Static;
219 }
220
221 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
222 // is defined as a model for code which may be used in static or dynamic
223 // executables but not necessarily a shared library. On X86-32 we just
224 // compile in -static mode, in x86-64 we use PIC.
225 if (RM == Reloc::DynamicNoPIC) {
226 if (is64Bit)
227 RM = Reloc::PIC_;
228 else if (!TT.isOSDarwin())
229 RM = Reloc::Static;
230 }
231
232 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
233 // the Mach-O file format doesn't support it.
234 if (RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
235 RM = Reloc::PIC_;
236205
237206 // For static codegen, if we're not already set, use Small codegen.
238207 if (CM == CodeModel::Default)
105105 return Ret;
106106 }
107107
108 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
109 Optional RM) {
110 bool is64Bit = TT.getArch() == Triple::x86_64;
111 if (!RM.hasValue()) {
112 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
113 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
114 // use static relocation model by default.
115 if (TT.isOSDarwin()) {
116 if (is64Bit)
117 return Reloc::PIC_;
118 return Reloc::DynamicNoPIC;
119 }
120 if (TT.isOSWindows() && is64Bit)
121 return Reloc::PIC_;
122 return Reloc::Static;
123 }
124
125 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
126 // is defined as a model for code which may be used in static or dynamic
127 // executables but not necessarily a shared library. On X86-32 we just
128 // compile in -static mode, in x86-64 we use PIC.
129 if (*RM == Reloc::DynamicNoPIC) {
130 if (is64Bit)
131 return Reloc::PIC_;
132 if (!TT.isOSDarwin())
133 return Reloc::Static;
134 }
135
136 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
137 // the Mach-O file format doesn't support it.
138 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
139 return Reloc::PIC_;
140
141 return *RM;
142 }
143
108144 /// Create an X86 target.
109145 ///
110146 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
111147 StringRef CPU, StringRef FS,
112148 const TargetOptions &Options,
113 Reloc::Model RM, CodeModel::Model CM,
114 CodeGenOpt::Level OL)
115 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
116 OL),
149 Optional RM,
150 CodeModel::Model CM, CodeGenOpt::Level OL)
151 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
152 getEffectiveRelocModel(TT, RM), CM, OL),
117153 TLOF(createTLOF(getTargetTriple())),
118154 Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) {
119155 // Windows stack unwinder gets confused when execution flow "falls through"
2929
3030 public:
3131 X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
32 StringRef FS, const TargetOptions &Options, Reloc::Model RM,
33 CodeModel::Model CM, CodeGenOpt::Level OL);
32 StringRef FS, const TargetOptions &Options,
33 Optional RM, CodeModel::Model CM,
34 CodeGenOpt::Level OL);
3435 ~X86TargetMachine() override;
3536 const X86Subtarget *getSubtargetImpl(const Function &F) const override;
3637
6666 CodeModel::Model CM,
6767 CodeGenOpt::Level OL) {
6868 MCCodeGenInfo *X = new MCCodeGenInfo();
69 if (RM == Reloc::Default) {
70 RM = Reloc::Static;
71 }
7269 if (CM == CodeModel::Default) {
7370 CM = CodeModel::Small;
7471 }
2020 #include "llvm/Support/TargetRegistry.h"
2121 using namespace llvm;
2222
23 static Reloc::Model getEffectiveRelocModel(Optional RM) {
24 if (!RM.hasValue())
25 return Reloc::Static;
26 return *RM;
27 }
28
2329 /// Create an ILP32 architecture model
2430 ///
2531 XCoreTargetMachine::XCoreTargetMachine(const Target &T, const Triple &TT,
2632 StringRef CPU, StringRef FS,
2733 const TargetOptions &Options,
28 Reloc::Model RM, CodeModel::Model CM,
34 Optional RM,
35 CodeModel::Model CM,
2936 CodeGenOpt::Level OL)
3037 : LLVMTargetMachine(
3138 T, "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32-f64:32-a:0:32-n32",
32 TT, CPU, FS, Options, RM, CM, OL),
39 TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL),
3340 TLOF(make_unique()),
3441 Subtarget(TT, CPU, FS, *this) {
3542 initAsmInfo();
2424 public:
2525 XCoreTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
2626 StringRef FS, const TargetOptions &Options,
27 Reloc::Model RM, CodeModel::Model CM,
27 Optional RM, CodeModel::Model CM,
2828 CodeGenOpt::Level OL);
2929 ~XCoreTargetMachine() override;
3030
138138 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,,+d16,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4
139139 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=pic | FileCheck %s --check-prefix=RELOC-PIC
140140 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=static | FileCheck %s --check-prefix=RELOC-OTHER
141 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=default | FileCheck %s --check-prefix=RELOC-OTHER
142141 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER
143142 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=RELOC-OTHER
144143 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=PCS-R9-USE
None ; RUN: llc -O3 -code-model=default -relocation-model=default -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s
0 ; RUN: llc -O3 -code-model=default -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s
11 ; Check that we respect the existing chain between loads and stores when we
22 ; legalize unaligned loads.
33 ; Test case from PR24669.
628628 return error("no object streamer for target " + TripleName, Context);
629629
630630 // Finally create the AsmPrinter we'll use to emit the DIEs.
631 TM.reset(TheTarget->createTargetMachine(TripleName, "", "", TargetOptions()));
631 TM.reset(TheTarget->createTargetMachine(TripleName, "", "", TargetOptions(),
632 None));
632633 if (!TM)
633634 return error("no target machine for target " + TripleName, Context);
634635
142142 static ld_plugin_add_input_file add_input_file = nullptr;
143143 static ld_plugin_set_extra_library_path set_extra_library_path = nullptr;
144144 static ld_plugin_get_view get_view = nullptr;
145 static Reloc::Model RelocationModel = Reloc::Default;
145 static Optional RelocationModel;
146146 static std::string output_name = "";
147147 static std::list Modules;
148148 static StringMap ResInfo;
320320
321321 std::unique_ptr Target(
322322 TheTarget->createTargetMachine(TheTriple.getTriple(), CPUStr, FeaturesStr,
323 Options, RelocModel, CMModel, OLvl));
323 Options, getRelocModel(), CMModel, OLvl));
324324
325325 assert(Target && "Could not allocate target machine!");
326326
186186 cl::desc("Disable JIT lazy compilation"),
187187 cl::init(false));
188188
189 cl::opt
190 RelocModel("relocation-model",
191 cl::desc("Choose relocation model"),
192 cl::init(Reloc::Default),
193 cl::values(
194 clEnumValN(Reloc::Default, "default",
195 "Target default relocation model"),
196 clEnumValN(Reloc::Static, "static",
197 "Non-relocatable code"),
198 clEnumValN(Reloc::PIC_, "pic",
199 "Fully relocatable, position independent code"),
200 clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
201 "Relocatable external references, non-relocatable code"),
202 clEnumValEnd));
189 cl::opt RelocModel(
190 "relocation-model", cl::desc("Choose relocation model"),
191 cl::values(
192 clEnumValN(Reloc::Static, "static", "Non-relocatable code"),
193 clEnumValN(Reloc::PIC_, "pic",
194 "Fully relocatable, position independent code"),
195 clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
196 "Relocatable external references, non-relocatable code"),
197 clEnumValEnd));
203198
204199 cl::opt
205200 CMModel("code-model",
424419 builder.setMArch(MArch);
425420 builder.setMCPU(MCPU);
426421 builder.setMAttrs(MAttrs);
427 builder.setRelocationModel(RelocModel);
422 if (RelocModel.getNumOccurrences())
423 builder.setRelocationModel(RelocModel);
428424 builder.setCodeModel(CMModel);
429425 builder.setErrorStr(&ErrorMsg);
430426 builder.setEngineKind(ForceInterpreter
389389 ThinLTOCodeGenerator ThinGenerator;
390390
391391 ThinLTOProcessing(const TargetOptions &Options) {
392 ThinGenerator.setCodePICModel(RelocModel);
392 ThinGenerator.setCodePICModel(getRelocModel());
393393 ThinGenerator.setTargetOptions(Options);
394394 ThinGenerator.setCacheDir(ThinLTOCacheDir);
395395
736736 if (UseDiagnosticHandler)
737737 CodeGen.setDiagnosticHandler(handleDiagnostics, nullptr);
738738
739 CodeGen.setCodePICModel(RelocModel);
739 CodeGen.setCodePICModel(getRelocModel());
740740
741741 CodeGen.setDebugInfo(LTO_DEBUG_MODEL_DWARF);
742742 CodeGen.setTargetOptions(Options);
356356 unwrap(cg)->setCodePICModel(Reloc::DynamicNoPIC);
357357 return false;
358358 case LTO_CODEGEN_PIC_MODEL_DEFAULT:
359 unwrap(cg)->setCodePICModel(Reloc::Default);
359 unwrap(cg)->setCodePICModel(None);
360360 return false;
361361 }
362362 sLastErrorString = "Unknown PIC model";
551551 unwrap(cg)->setCodePICModel(Reloc::DynamicNoPIC);
552552 return false;
553553 case LTO_CODEGEN_PIC_MODEL_DEFAULT:
554 unwrap(cg)->setCodePICModel(Reloc::Default);
554 unwrap(cg)->setCodePICModel(None);
555555 return false;
556556 }
557557 sLastErrorString = "Unknown PIC model";
311311 return nullptr;
312312 }
313313
314 return TheTarget->createTargetMachine(TheTriple.getTriple(),
315 CPUStr, FeaturesStr, Options,
316 RelocModel, CMModel,
317 GetCodeGenOptLevel());
314 return TheTarget->createTargetMachine(TheTriple.getTriple(), CPUStr,
315 FeaturesStr, Options, getRelocModel(),
316 CMModel, GetCodeGenOptLevel());
318317 }
319318
320319 #ifdef LINK_POLLY_INTO_TOOLS
4444
4545 TargetOptions Options;
4646 return std::unique_ptr(
47 T->createTargetMachine("x86_64", "", "", Options, Reloc::Default,
47 T->createTargetMachine("x86_64", "", "", Options, None,
4848 CodeModel::Default, CodeGenOpt::Aggressive));
4949 }
5050