llvm.org GIT mirror llvm / ac27366
Replace copyRegToReg with copyPhysReg for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
6 changed file(s) with 87 addition(s) and 149 deletion(s). Raw diff Collapse all Expand all
692692 return 0;
693693 }
694694
695 bool
696 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
697 MachineBasicBlock::iterator I,
698 unsigned DestReg, unsigned SrcReg,
699 const TargetRegisterClass *DestRC,
700 const TargetRegisterClass *SrcRC,
701 DebugLoc DL) const {
702 // tGPR or tcGPR is used sometimes in ARM instructions that need to avoid
703 // using certain registers. Just treat them as GPR here.
704 if (DestRC == ARM::tGPRRegisterClass || DestRC == ARM::tcGPRRegisterClass)
705 DestRC = ARM::GPRRegisterClass;
706 if (SrcRC == ARM::tGPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass)
707 SrcRC = ARM::GPRRegisterClass;
708
709 if (DestRC == ARM::SPR_8RegisterClass)
710 DestRC = ARM::SPRRegisterClass;
711 if (SrcRC == ARM::SPR_8RegisterClass)
712 SrcRC = ARM::SPRRegisterClass;
713
714 // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
715 if (DestRC == ARM::DPR_8RegisterClass)
716 DestRC = ARM::DPR_VFP2RegisterClass;
717 if (SrcRC == ARM::DPR_8RegisterClass)
718 SrcRC = ARM::DPR_VFP2RegisterClass;
719
720 // NEONMoveFixPass will convert VFP moves to NEON moves when profitable.
721 if (DestRC == ARM::DPR_VFP2RegisterClass)
722 DestRC = ARM::DPRRegisterClass;
723 if (SrcRC == ARM::DPR_VFP2RegisterClass)
724 SrcRC = ARM::DPRRegisterClass;
725
726 // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
727 if (DestRC == ARM::QPR_VFP2RegisterClass ||
728 DestRC == ARM::QPR_8RegisterClass)
729 DestRC = ARM::QPRRegisterClass;
730 if (SrcRC == ARM::QPR_VFP2RegisterClass ||
731 SrcRC == ARM::QPR_8RegisterClass)
732 SrcRC = ARM::QPRRegisterClass;
733
734 // Allow QQPR / QQPR_VFP2 cross-class copies.
735 if (DestRC == ARM::QQPR_VFP2RegisterClass)
736 DestRC = ARM::QQPRRegisterClass;
737 if (SrcRC == ARM::QQPR_VFP2RegisterClass)
738 SrcRC = ARM::QQPRRegisterClass;
739
740 // Disallow copies of unequal sizes.
741 if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
742 return false;
743
744 if (DestRC == ARM::GPRRegisterClass) {
745 if (SrcRC == ARM::SPRRegisterClass)
746 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
747 .addReg(SrcReg));
748 else
749 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
750 DestReg).addReg(SrcReg)));
751 } else {
752 unsigned Opc;
753
754 if (DestRC == ARM::SPRRegisterClass)
755 Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
756 else if (DestRC == ARM::DPRRegisterClass)
757 Opc = ARM::VMOVD;
758 else if (DestRC == ARM::QPRRegisterClass)
759 Opc = ARM::VMOVQ;
760 else if (DestRC == ARM::QQPRRegisterClass)
761 Opc = ARM::VMOVQQ;
762 else if (DestRC == ARM::QQQQPRRegisterClass)
763 Opc = ARM::VMOVQQQQ;
764 else
765 return false;
766
767 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
768 MIB.addReg(SrcReg);
769 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
770 AddDefaultPred(MIB);
771 }
772
773 return true;
695 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
696 MachineBasicBlock::iterator I, DebugLoc DL,
697 unsigned DestReg, unsigned SrcReg,
698 bool KillSrc) const {
699 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
700 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
701
702 if (GPRDest && GPRSrc) {
703 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
704 .addReg(SrcReg, getKillRegState(KillSrc))));
705 return;
706 }
707
708 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
709 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
710
711 unsigned Opc;
712 if (SPRDest && SPRSrc)
713 Opc = ARM::VMOVS;
714 else if (GPRDest && SPRSrc)
715 Opc = ARM::VMOVRS;
716 else if (SPRDest && GPRSrc)
717 Opc = ARM::VMOVSR;
718 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
719 Opc = ARM::VMOVD;
720 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
721 Opc = ARM::VMOVQ;
722 else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
723 Opc = ARM::VMOVQQ;
724 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
725 Opc = ARM::VMOVQQQQ;
726 else
727 llvm_unreachable("Impossible reg-to-reg copy");
728
729 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
730 MIB.addReg(SrcReg, getKillRegState(KillSrc));
731 if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
732 AddDefaultPred(MIB);
774733 }
775734
776735 static const
272272 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
273273 int &FrameIndex) const;
274274
275 virtual bool copyRegToReg(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator I,
277 unsigned DestReg, unsigned SrcReg,
278 const TargetRegisterClass *DestRC,
279 const TargetRegisterClass *SrcRC,
280 DebugLoc DL) const;
275 virtual void copyPhysReg(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator I, DebugLoc DL,
277 unsigned DestReg, unsigned SrcReg,
278 bool KillSrc) const;
281279
282280 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
283281 MachineBasicBlock::iterator MBBI,
3232 return 0;
3333 }
3434
35 bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I,
37 unsigned DestReg, unsigned SrcReg,
38 const TargetRegisterClass *DestRC,
39 const TargetRegisterClass *SrcRC,
40 DebugLoc DL) const {
41 if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
42 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
43 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
44 return true;
45 } else if (SrcRC == ARM::tGPRRegisterClass) {
46 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
47 return true;
48 }
49 } else if (DestRC == ARM::tGPRRegisterClass) {
50 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
51 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
52 return true;
53 } else if (SrcRC == ARM::tGPRRegisterClass) {
54 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
55 return true;
56 }
57 }
58
59 return false;
35 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator I, DebugLoc DL,
37 unsigned DestReg, unsigned SrcReg,
38 bool KillSrc) const {
39 bool tDest = ARM::tGPRRegClass.contains(DestReg);
40 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
41 unsigned Opc = ARM::tMOVgpr2gpr;
42 if (tDest && tSrc)
43 Opc = ARM::tMOVr;
44 else if (tSrc)
45 Opc = ARM::tMOVtgpr2gpr;
46 else if (tDest)
47 Opc = ARM::tMOVgpr2tgpr;
48
49 BuildMI(MBB, I, DL, get(Opc), DestReg)
50 .addReg(SrcReg, getKillRegState(KillSrc));
51 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
52 "Thumb1 can only copy GPR registers");
6053 }
6154
6255 bool Thumb1InstrInfo::
4545 const std::vector &CSI,
4646 const TargetRegisterInfo *TRI) const;
4747
48 bool copyRegToReg(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator I,
50 unsigned DestReg, unsigned SrcReg,
51 const TargetRegisterClass *DestRC,
52 const TargetRegisterClass *SrcRC,
53 DebugLoc DL) const;
48 void copyPhysReg(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator I, DebugLoc DL,
50 unsigned DestReg, unsigned SrcReg,
51 bool KillSrc) const;
5452 void storeRegToStackSlot(MachineBasicBlock &MBB,
5553 MachineBasicBlock::iterator MBBI,
5654 unsigned SrcReg, bool isKill, int FrameIndex,
119119 NumT <= (IfCvtDiamondLimit) && NumF <= (IfCvtDiamondLimit);
120120 }
121121
122 bool
123 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
124 MachineBasicBlock::iterator I,
125 unsigned DestReg, unsigned SrcReg,
126 const TargetRegisterClass *DestRC,
127 const TargetRegisterClass *SrcRC,
128 DebugLoc DL) const {
129 if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
130 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
131 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
132 return true;
133 } else if (SrcRC == ARM::tGPRRegisterClass) {
134 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
135 return true;
136 }
137 } else if (DestRC == ARM::tGPRRegisterClass) {
138 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
139 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
140 return true;
141 } else if (SrcRC == ARM::tGPRRegisterClass) {
142 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
143 return true;
144 }
145 }
146
122 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I, DebugLoc DL,
124 unsigned DestReg, unsigned SrcReg,
125 bool KillSrc) const {
147126 // Handle SPR, DPR, and QPR copies.
148 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC,
149 SrcRC, DL);
127 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
128 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
129
130 bool tDest = ARM::tGPRRegClass.contains(DestReg);
131 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
132 unsigned Opc = ARM::tMOVgpr2gpr;
133 if (tDest && tSrc)
134 Opc = ARM::tMOVr;
135 else if (tSrc)
136 Opc = ARM::tMOVtgpr2gpr;
137 else if (tDest)
138 Opc = ARM::tMOVgpr2tgpr;
139
140 BuildMI(MBB, I, DL, get(Opc), DestReg)
141 .addReg(SrcReg, getKillRegState(KillSrc));
150142 }
151143
152144 void Thumb2InstrInfo::
4242 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs,
4343 MachineBasicBlock &FMBB, unsigned NumFInstrs) const;
4444
45 bool copyRegToReg(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator I,
47 unsigned DestReg, unsigned SrcReg,
48 const TargetRegisterClass *DestRC,
49 const TargetRegisterClass *SrcRC,
50 DebugLoc DL) const;
45 void copyPhysReg(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator I, DebugLoc DL,
47 unsigned DestReg, unsigned SrcReg,
48 bool KillSrc) const;
5149
5250 void storeRegToStackSlot(MachineBasicBlock &MBB,
5351 MachineBasicBlock::iterator MBBI,