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Revert r355224 "[TableGen][SelectionDAG][X86] Add specific isel matchers for immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary." This caused the first matcher in the isel table for many targets to Opc_Scope instead of Opc_SwitchOpcode. This leads to a significant increase in isel match failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355433 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 7 months ago
12 changed file(s) with 68 addition(s) and 137 deletion(s). Raw diff Collapse all Expand all
146146 OPC_CheckValueType,
147147 OPC_CheckComplexPat,
148148 OPC_CheckAndImm, OPC_CheckOrImm,
149 OPC_CheckImmAllOnesV,
150 OPC_CheckImmAllZerosV,
151149 OPC_CheckFoldableChainNode,
152150
153151 OPC_EmitInteger,
781781 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
782782 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
783783
784 def immAllOnesV; // ISD::isBuildVectorAllOnes
785 def immAllZerosV; // ISD::isBuildVectorAllZeros
784 def immAllOnesV: PatLeaf<(build_vector), [{
785 return ISD::isBuildVectorAllOnes(N);
786 }]>;
787 def immAllZerosV: PatLeaf<(build_vector), [{
788 return ISD::isBuildVectorAllZeros(N);
789 }]>;
790
791
786792
787793 // Other helper fragments.
788794 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
33923392 case OPC_CheckOrImm:
33933393 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
33943394 continue;
3395 case OPC_CheckImmAllOnesV:
3396 if (!ISD::isBuildVectorAllOnes(N.getNode())) break;
3397 continue;
3398 case OPC_CheckImmAllZerosV:
3399 if (!ISD::isBuildVectorAllZeros(N.getNode())) break;
3400 continue;
34013395
34023396 case OPC_CheckFoldableChainNode: {
34033397 assert(NodeStack.size() != 1 && "No parent node");
734734 // zeroed vector.
735735 class z_vllez
736736 : PatFrag<(ops node:$addr),
737 (z_vector_insert immAllZerosV,
737 (z_vector_insert (immAllZerosV),
738738 (scalartype (load node:$addr)), (i32 index))>;
739739 def z_vllezi8 : z_vllez;
740740 def z_vllezi16 : z_vllez;
741741 def z_vllezi32 : z_vllez;
742742 def z_vllezi64 : PatFrags<(ops node:$addr),
743 [(z_vector_insert immAllZerosV,
743 [(z_vector_insert (immAllZerosV),
744744 (i64 (load node:$addr)), (i32 0)),
745745 (z_join_dwords (i64 (load node:$addr)), (i64 0))]>;
746746 // We use high merges to form a v4f32 from four f32s. Propagating zero
754754 (v4f32 (scalar_to_vector
755755 (f32 (load node:$addr)))))))),
756756 (v2i64
757 (bitconvert (v4f32 immAllZerosV))))>;
757 (bitconvert (v4f32 (immAllZerosV)))))>;
758758 def z_vllezf64 : PatFrag<(ops node:$addr),
759759 (z_merge_high
760760 (v2f64 (scalar_to_vector (f64 (load node:$addr)))),
761 immAllZerosV)>;
761 (immAllZerosV))>;
762762
763763 // Similarly for the high element of a zeroed vector.
764764 def z_vllezli32 : z_vllez;
769769 (z_merge_high
770770 (v4f32 (scalar_to_vector
771771 (f32 (load node:$addr)))),
772 (v4f32 immAllZerosV)))),
772 (v4f32 (immAllZerosV))))),
773773 (v2i64
774 (bitconvert (v4f32 immAllZerosV))))>;
774 (bitconvert (v4f32 (immAllZerosV)))))>;
775775
776776 // Store one element of a vector.
777777 class z_vste
786786 def z_vstef64 : z_vste;
787787
788788 // Arithmetic negation on vectors.
789 def z_vneg : PatFrag<(ops node:$x), (sub immAllZerosV, node:$x)>;
789 def z_vneg : PatFrag<(ops node:$x), (sub (immAllZerosV), node:$x)>;
790790
791791 // Bitwise negation on vectors.
792 def z_vnot : PatFrag<(ops node:$x), (xor node:$x, immAllOnesV)>;
792 def z_vnot : PatFrag<(ops node:$x), (xor node:$x, (immAllOnesV))>;
793793
794794 // Signed "integer greater than zero" on vectors.
795 def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, immAllZerosV)>;
795 def z_vicmph_zero : PatFrag<(ops node:$x), (z_vicmph node:$x, (immAllZerosV))>;
796796
797797 // Signed "integer less than zero" on vectors.
798 def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph immAllZerosV, node:$x)>;
798 def z_vicmpl_zero : PatFrag<(ops node:$x), (z_vicmph (immAllZerosV), node:$x)>;
799799
800800 // Integer absolute on vectors.
801801 class z_viabs
9393
9494 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
9595
96 dag ImmAllZerosV = (VT immAllZerosV);
96 // A vector type of the same width with element type i32. This is used to
97 // create the canonical constant zero node ImmAllZerosV.
98 ValueType i32VT = !cast("v" # !srl(Size, 5) # "i32");
99 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
97100
98101 string ZSuffix = !if (!eq (Size, 128), "Z128",
99102 !if (!eq (Size, 256), "Z256", "Z"));
446449 def AVX512_512_SEXT_MASK_64 : I<0, Pseudo, (outs VR512:$dst),
447450 (ins VK8WM:$mask), "",
448451 [(set VR512:$dst, (vselect (v8i1 VK8WM:$mask),
449 (v8i64 immAllOnesV),
450 (v8i64 immAllZerosV)))]>;
452 (bc_v8i64 (v16i32 immAllOnesV)),
453 (bc_v8i64 (v16i32 immAllZerosV))))]>;
451454 }
452455
453456 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
14601463 // Patterns for selects of bitcasted operations.
14611464 def : Pat<(vselect VK16WM:$mask,
14621465 (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv2f64 addr:$src)))),
1463 (v16f32 immAllZerosV)),
1466 (bc_v16f32 (v16i32 immAllZerosV))),
14641467 (VBROADCASTF32X4rmkz VK16WM:$mask, addr:$src)>;
14651468 def : Pat<(vselect VK16WM:$mask,
14661469 (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv2f64 addr:$src)))),
14771480
14781481 def : Pat<(vselect VK8WM:$mask,
14791482 (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv8f32 addr:$src)))),
1480 (v8f64 immAllZerosV)),
1483 (bc_v8f64 (v16i32 immAllZerosV))),
14811484 (VBROADCASTF64X4rmkz VK8WM:$mask, addr:$src)>;
14821485 def : Pat<(vselect VK8WM:$mask,
14831486 (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv8f32 addr:$src)))),
14851488 (VBROADCASTF64X4rmk VR512:$src0, VK8WM:$mask, addr:$src)>;
14861489 def : Pat<(vselect VK8WM:$mask,
14871490 (bc_v8i64 (v16i32 (X86SubVBroadcast (loadv8i32 addr:$src)))),
1488 (v8i64 immAllZerosV)),
1491 (bc_v8i64 (v16i32 immAllZerosV))),
14891492 (VBROADCASTI64X4rmkz VK8WM:$mask, addr:$src)>;
14901493 def : Pat<(vselect VK8WM:$mask,
14911494 (bc_v8i64 (v16i32 (X86SubVBroadcast (loadv8i32 addr:$src)))),
15131516 // Patterns for selects of bitcasted operations.
15141517 def : Pat<(vselect VK8WM:$mask,
15151518 (bc_v8f32 (v4f64 (X86SubVBroadcast (loadv2f64 addr:$src)))),
1516 (v8f32 immAllZerosV)),
1519 (bc_v8f32 (v8i32 immAllZerosV))),
15171520 (VBROADCASTF32X4Z256rmkz VK8WM:$mask, addr:$src)>;
15181521 def : Pat<(vselect VK8WM:$mask,
15191522 (bc_v8f32 (v4f64 (X86SubVBroadcast (loadv2f64 addr:$src)))),
15621565 // Patterns for selects of bitcasted operations.
15631566 def : Pat<(vselect VK4WM:$mask,
15641567 (bc_v4f64 (v8f32 (X86SubVBroadcast (loadv4f32 addr:$src)))),
1565 (v4f64 immAllZerosV)),
1568 (bc_v4f64 (v8i32 immAllZerosV))),
15661569 (VBROADCASTF64X2Z128rmkz VK4WM:$mask, addr:$src)>;
15671570 def : Pat<(vselect VK4WM:$mask,
15681571 (bc_v4f64 (v8f32 (X86SubVBroadcast (loadv4f32 addr:$src)))),
15701573 (VBROADCASTF64X2Z128rmk VR256X:$src0, VK4WM:$mask, addr:$src)>;
15711574 def : Pat<(vselect VK4WM:$mask,
15721575 (bc_v4i64 (v8i32 (X86SubVBroadcast (loadv4i32 addr:$src)))),
1573 (v4i64 immAllZerosV)),
1576 (bc_v4i64 (v8i32 immAllZerosV))),
15741577 (VBROADCASTI64X2Z128rmkz VK4WM:$mask, addr:$src)>;
15751578 def : Pat<(vselect VK4WM:$mask,
15761579 (bc_v4i64 (v8i32 (X86SubVBroadcast (loadv4i32 addr:$src)))),
15951598 // Patterns for selects of bitcasted operations.
15961599 def : Pat<(vselect VK16WM:$mask,
15971600 (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv4f64 addr:$src)))),
1598 (v16f32 immAllZerosV)),
1601 (bc_v16f32 (v16i32 immAllZerosV))),
15991602 (VBROADCASTF32X8rmkz VK16WM:$mask, addr:$src)>;
16001603 def : Pat<(vselect VK16WM:$mask,
16011604 (bc_v16f32 (v8f64 (X86SubVBroadcast (loadv4f64 addr:$src)))),
16121615
16131616 def : Pat<(vselect VK8WM:$mask,
16141617 (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv4f32 addr:$src)))),
1615 (v8f64 immAllZerosV)),
1618 (bc_v8f64 (v16i32 immAllZerosV))),
16161619 (VBROADCASTF64X2rmkz VK8WM:$mask, addr:$src)>;
16171620 def : Pat<(vselect VK8WM:$mask,
16181621 (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv4f32 addr:$src)))),
16201623 (VBROADCASTF64X2rmk VR512:$src0, VK8WM:$mask, addr:$src)>;
16211624 def : Pat<(vselect VK8WM:$mask,
16221625 (bc_v8i64 (v16i32 (X86SubVBroadcast (loadv4i32 addr:$src)))),
1623 (v8i64 immAllZerosV)),
1626 (bc_v8i64 (v16i32 immAllZerosV))),
16241627 (VBROADCASTI64X2rmkz VK8WM:$mask, addr:$src)>;
16251628 def : Pat<(vselect VK8WM:$mask,
16261629 (bc_v8i64 (v16i32 (X86SubVBroadcast (loadv4i32 addr:$src)))),
36053608 "", []>, Sched<[WriteFStoreY]>;
36063609 }
36073610
3608 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 immAllZerosV),
3611 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
36093612 (v8i64 VR512:$src))),
36103613 (VMOVDQA64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
36113614 VK8), VR512:$src)>;
36173620 // These patterns exist to prevent the above patterns from introducing a second
36183621 // mask inversion when one already exists.
36193622 def : Pat<(v8i64 (vselect (xor VK8:$mask, (v8i1 immAllOnesV)),
3620 (v8i64 immAllZerosV),
3623 (bc_v8i64 (v16i32 immAllZerosV)),
36213624 (v8i64 VR512:$src))),
36223625 (VMOVDQA64Zrrkz VK8:$mask, VR512:$src)>;
36233626 def : Pat<(v16i32 (vselect (xor VK16:$mask, (v16i1 immAllOnesV)),
41154118
41164119 def : Pat<(_.info128.VT (extract_subvector
41174120 (_.info512.VT (masked_load addr:$srcAddr, Mask,
4118 _.info512.ImmAllZerosV)),
4121 (_.info512.VT (bitconvert
4122 (v16i32 immAllZerosV))))),
41194123 (iPTR 0))),
41204124 (!cast(InstrStr#rmkz)
41214125 (COPY_TO_REGCLASS MaskRC:$mask, VK1WM),
41404144
41414145 def : Pat<(_.info128.VT (extract_subvector
41424146 (_.info512.VT (masked_load addr:$srcAddr, Mask,
4143 _.info512.ImmAllZerosV)),
4147 (_.info512.VT (bitconvert
4148 (v16i32 immAllZerosV))))),
41444149 (iPTR 0))),
41454150 (!cast(InstrStr#rmkz)
41464151 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
41694174 // AVX512F patterns.
41704175 def : Pat<(_.info128.VT (extract_subvector
41714176 (_.info512.VT (masked_load addr:$srcAddr, Mask512,
4172 _.info512.ImmAllZerosV)),
4177 (_.info512.VT (bitconvert
4178 (v16i32 immAllZerosV))))),
41734179 (iPTR 0))),
41744180 (!cast(InstrStr#rmkz)
41754181 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
41874193
41884194 // AVX512Vl patterns.
41894195 def : Pat<(_.info128.VT (masked_load addr:$srcAddr, Mask128,
4190 _.info128.ImmAllZerosV)),
4196 (_.info128.VT (bitconvert (v4i32 immAllZerosV))))),
41914197 (!cast(InstrStr#rmkz)
41924198 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
41934199 addr:$srcAddr)>;
1157111577 (VMOVDDUPZ128rrk VR128X:$src0, VK2WM:$mask,
1157211578 (v2f64 (COPY_TO_REGCLASS FR64X:$src, VR128X)))>;
1157311579 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast f64:$src)),
11574 immAllZerosV),
11580 (bitconvert (v4i32 immAllZerosV))),
1157511581 (VMOVDDUPZ128rrkz VK2WM:$mask, (v2f64 (COPY_TO_REGCLASS FR64X:$src, VR128X)))>;
1157611582
1157711583 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadf64 addr:$src))),
1157811584 (v2f64 VR128X:$src0)),
1157911585 (VMOVDDUPZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
1158011586 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadf64 addr:$src))),
11581 immAllZerosV),
11587 (bitconvert (v4i32 immAllZerosV))),
1158211588 (VMOVDDUPZ128rmkz VK2WM:$mask, addr:$src)>;
1158311589
1158411590 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadv2f64 addr:$src))),
1158511591 (v2f64 VR128X:$src0)),
1158611592 (VMOVDDUPZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
1158711593 def : Pat<(vselect (v2i1 VK2WM:$mask), (v2f64 (X86VBroadcast (loadv2f64 addr:$src))),
11588 immAllZerosV),
11594 (bitconvert (v4i32 immAllZerosV))),
1158911595 (VMOVDDUPZ128rmkz VK2WM:$mask, addr:$src)>;
1159011596 }
1159111597
1208412090 // TODO: We should maybe have a more generalized algorithm for folding to
1208512091 // vpternlog.
1208612092 let Predicates = [HasAVX512] in {
12087 def : Pat<(xor VR512:$src, (v64i8 immAllOnesV)),
12093 def : Pat<(xor VR512:$src, (bc_v64i8 (v16i32 immAllOnesV))),
1208812094 (VPTERNLOGQZrri VR512:$src, VR512:$src, VR512:$src, (i8 15))>;
12089 def : Pat<(xor VR512:$src, (v32i16 immAllOnesV)),
12095 def : Pat<(xor VR512:$src, (bc_v32i16 (v16i32 immAllOnesV))),
1209012096 (VPTERNLOGQZrri VR512:$src, VR512:$src, VR512:$src, (i8 15))>;
12091 def : Pat<(xor VR512:$src, (v16i32 immAllOnesV)),
12097 def : Pat<(xor VR512:$src, (bc_v16i32 (v16i32 immAllOnesV))),
1209212098 (VPTERNLOGQZrri VR512:$src, VR512:$src, VR512:$src, (i8 15))>;
12093 def : Pat<(xor VR512:$src, (v8i64 immAllOnesV)),
12099 def : Pat<(xor VR512:$src, (bc_v8i64 (v16i32 immAllOnesV))),
1209412100 (VPTERNLOGQZrri VR512:$src, VR512:$src, VR512:$src, (i8 15))>;
1209512101 }
1209612102
1209712103 let Predicates = [HasAVX512, NoVLX] in {
12098 def : Pat<(xor VR128X:$src, (v16i8 immAllOnesV)),
12104 def : Pat<(xor VR128X:$src, (bc_v16i8 (v4i32 immAllOnesV))),
1209912105 (EXTRACT_SUBREG
1210012106 (VPTERNLOGQZrri
1210112107 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1210212108 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1210312109 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1210412110 (i8 15)), sub_xmm)>;
12105 def : Pat<(xor VR128X:$src, (v8i16 immAllOnesV)),
12111 def : Pat<(xor VR128X:$src, (bc_v8i16 (v4i32 immAllOnesV))),
1210612112 (EXTRACT_SUBREG
1210712113 (VPTERNLOGQZrri
1210812114 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1210912115 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1211012116 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1211112117 (i8 15)), sub_xmm)>;
12112 def : Pat<(xor VR128X:$src, (v4i32 immAllOnesV)),
12118 def : Pat<(xor VR128X:$src, (bc_v4i32 (v4i32 immAllOnesV))),
1211312119 (EXTRACT_SUBREG
1211412120 (VPTERNLOGQZrri
1211512121 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1211612122 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1211712123 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1211812124 (i8 15)), sub_xmm)>;
12119 def : Pat<(xor VR128X:$src, (v2i64 immAllOnesV)),
12125 def : Pat<(xor VR128X:$src, (bc_v2i64 (v4i32 immAllOnesV))),
1212012126 (EXTRACT_SUBREG
1212112127 (VPTERNLOGQZrri
1212212128 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1212412130 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1212512131 (i8 15)), sub_xmm)>;
1212612132
12127 def : Pat<(xor VR256X:$src, (v32i8 immAllOnesV)),
12133 def : Pat<(xor VR256X:$src, (bc_v32i8 (v8i32 immAllOnesV))),
1212812134 (EXTRACT_SUBREG
1212912135 (VPTERNLOGQZrri
1213012136 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1213112137 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1213212138 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1213312139 (i8 15)), sub_ymm)>;
12134 def : Pat<(xor VR256X:$src, (v16i16 immAllOnesV)),
12140 def : Pat<(xor VR256X:$src, (bc_v16i16 (v8i32 immAllOnesV))),
1213512141 (EXTRACT_SUBREG
1213612142 (VPTERNLOGQZrri
1213712143 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1213812144 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1213912145 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1214012146 (i8 15)), sub_ymm)>;
12141 def : Pat<(xor VR256X:$src, (v8i32 immAllOnesV)),
12147 def : Pat<(xor VR256X:$src, (bc_v8i32 (v8i32 immAllOnesV))),
1214212148 (EXTRACT_SUBREG
1214312149 (VPTERNLOGQZrri
1214412150 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1214512151 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1214612152 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1214712153 (i8 15)), sub_ymm)>;
12148 def : Pat<(xor VR256X:$src, (v4i64 immAllOnesV)),
12154 def : Pat<(xor VR256X:$src, (bc_v4i64 (v8i32 immAllOnesV))),
1214912155 (EXTRACT_SUBREG
1215012156 (VPTERNLOGQZrri
1215112157 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1215512161 }
1215612162
1215712163 let Predicates = [HasVLX] in {
12158 def : Pat<(xor VR128X:$src, (v16i8 immAllOnesV)),
12164 def : Pat<(xor VR128X:$src, (bc_v16i8 (v4i32 immAllOnesV))),
1215912165 (VPTERNLOGQZ128rri VR128X:$src, VR128X:$src, VR128X:$src, (i8 15))>;
12160 def : Pat<(xor VR128X:$src, (v8i16 immAllOnesV)),
12166 def : Pat<(xor VR128X:$src, (bc_v8i16 (v4i32 immAllOnesV))),
1216112167 (VPTERNLOGQZ128rri VR128X:$src, VR128X:$src, VR128X:$src, (i8 15))>;
12162 def : Pat<(xor VR128X:$src, (v4i32 immAllOnesV)),
12168 def : Pat<(xor VR128X:$src, (bc_v4i32 (v4i32 immAllOnesV))),
1216312169 (VPTERNLOGQZ128rri VR128X:$src, VR128X:$src, VR128X:$src, (i8 15))>;
12164 def : Pat<(xor VR128X:$src, (v2i64 immAllOnesV)),
12170 def : Pat<(xor VR128X:$src, (bc_v2i64 (v4i32 immAllOnesV))),
1216512171 (VPTERNLOGQZ128rri VR128X:$src, VR128X:$src, VR128X:$src, (i8 15))>;
1216612172
12167 def : Pat<(xor VR256X:$src, (v32i8 immAllOnesV)),
12173 def : Pat<(xor VR256X:$src, (bc_v32i8 (v8i32 immAllOnesV))),
1216812174 (VPTERNLOGQZ256rri VR256X:$src, VR256X:$src, VR256X:$src, (i8 15))>;
12169 def : Pat<(xor VR256X:$src, (v16i16 immAllOnesV)),
12175 def : Pat<(xor VR256X:$src, (bc_v16i16 (v8i32 immAllOnesV))),
1217012176 (VPTERNLOGQZ256rri VR256X:$src, VR256X:$src, VR256X:$src, (i8 15))>;
12171 def : Pat<(xor VR256X:$src, (v8i32 immAllOnesV)),
12177 def : Pat<(xor VR256X:$src, (bc_v8i32 (v8i32 immAllOnesV))),
1217212178 (VPTERNLOGQZ256rri VR256X:$src, VR256X:$src, VR256X:$src, (i8 15))>;
12173 def : Pat<(xor VR256X:$src, (v4i64 immAllOnesV)),
12179 def : Pat<(xor VR256X:$src, (bc_v4i64 (v8i32 immAllOnesV))),
1217412180 (VPTERNLOGQZ256rri VR256X:$src, VR256X:$src, VR256X:$src, (i8 15))>;
1217512181 }
1217612182
82898289 def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask), undef)),
82908290 (!cast(InstrStr#"rm") RC:$mask, addr:$ptr)>;
82918291 def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask),
8292 (VT immAllZerosV))),
8292 (VT (bitconvert (ZeroVT immAllZerosV))))),
82938293 (!cast(InstrStr#"rm") RC:$mask, addr:$ptr)>;
82948294 def: Pat<(VT (X86mload addr:$ptr, (MaskVT RC:$mask), (VT RC:$src0))),
82958295 (!cast(BlendStr#"rr")
174174 RegisterClass RC, ValueType DstTy,
175175 ValueType SrcTy, ValueType ZeroTy,
176176 SubRegIndex SubIdx> {
177 def : Pat<(DstTy (insert_subvector immAllZerosV,
177 def : Pat<(DstTy (insert_subvector (bitconvert (ZeroTy immAllZerosV)),
178178 (SrcTy RC:$src), (iPTR 0))),
179179 (SUBREG_TO_REG (i64 0),
180180 (SrcTy (!cast("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>;
12801280 // PatternToMatch implementation
12811281 //
12821282
1283 static bool isImmAllOnesAllZerosMatch(const TreePatternNode *P) {
1284 if (!P->isLeaf())
1285 return false;
1286 DefInit *DI = dyn_cast(P->getLeafValue());
1287 if (!DI)
1288 return false;
1289
1290 Record *R = DI->getDef();
1291 return R->getName() == "immAllOnesV" || R->getName() == "immAllZerosV";
1292 }
1293
12941283 /// getPatternSize - Return the 'size' of this pattern. We want to match large
12951284 /// patterns before small ones. This is used to determine the size of a
12961285 /// pattern.
13301319 Size += 5; // Matches a ConstantSDNode (+3) and a specific value (+2).
13311320 else if (Child->getComplexPatternInfo(CGP))
13321321 Size += getPatternSize(Child, CGP);
1333 else if (isImmAllOnesAllZerosMatch(Child))
1334 Size += 4; // Matches a build_vector(+3) and a predicate (+1).
13351322 else if (!Child->getPredicateCalls().empty())
13361323 ++Size;
13371324 }
21382125 }
21392126
21402127 if (R->getName() == "node" || R->getName() == "srcvalue" ||
2141 R->getName() == "zero_reg" || R->getName() == "immAllOnesV" ||
2142 R->getName() == "immAllZerosV") {
2128 R->getName() == "zero_reg") {
21432129 // Placeholder.
21442130 return TypeSetByHwMode(); // Unknown.
21452131 }
236236 OS.indent(indent) << "CheckFoldableChainNode\n";
237237 }
238238
239 void CheckImmAllOnesVMatcher::printImpl(raw_ostream &OS,
240 unsigned indent) const {
241 OS.indent(indent) << "CheckAllOnesV\n";
242 }
243
244 void CheckImmAllZerosVMatcher::printImpl(raw_ostream &OS,
245 unsigned indent) const {
246 OS.indent(indent) << "CheckAllZerosV\n";
247 }
248
249239 void EmitIntegerMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
250240 OS.indent(indent) << "EmitInteger " << Val << " VT=" << getEnumName(VT)
251241 << '\n';
7070 CheckComplexPat,
7171 CheckAndImm,
7272 CheckOrImm,
73 CheckImmAllOnesV,
74 CheckImmAllZerosV,
7573 CheckFoldableChainNode,
7674
7775 // Node creation/emisssion.
127125 case CheckValueType:
128126 case CheckAndImm:
129127 case CheckOrImm:
130 case CheckImmAllOnesV:
131 case CheckImmAllZerosV:
132128 case CheckFoldableChainNode:
133129 return true;
134130 }
756752 }
757753 };
758754
759 /// CheckImmAllOnesVMatcher - This check if the current node is an build vector
760 /// of all ones.
761 class CheckImmAllOnesVMatcher : public Matcher {
762 public:
763 CheckImmAllOnesVMatcher() : Matcher(CheckImmAllOnesV) {}
764
765 static bool classof(const Matcher *N) {
766 return N->getKind() == CheckImmAllOnesV;
767 }
768
769 private:
770 void printImpl(raw_ostream &OS, unsigned indent) const override;
771 bool isEqualImpl(const Matcher *M) const override { return true; }
772 };
773
774 /// CheckImmAllZerosVMatcher - This check if the current node is an build vector
775 /// of all zeros.
776 class CheckImmAllZerosVMatcher : public Matcher {
777 public:
778 CheckImmAllZerosVMatcher() : Matcher(CheckImmAllZerosV) {}
779
780 static bool classof(const Matcher *N) {
781 return N->getKind() == CheckImmAllZerosV;
782 }
783
784 private:
785 void printImpl(raw_ostream &OS, unsigned indent) const override;
786 bool isEqualImpl(const Matcher *M) const override { return true; }
787 };
788
789755 /// CheckFoldableChainNodeMatcher - This checks to see if the current node
790756 /// (which defines a chain operand) is safe to fold into a larger pattern.
791757 class CheckFoldableChainNodeMatcher : public Matcher {
598598
599599 case Matcher::CheckFoldableChainNode:
600600 OS << "OPC_CheckFoldableChainNode,\n";
601 return 1;
602
603 case Matcher::CheckImmAllOnesV:
604 OS << "OPC_CheckImmAllOnesV,\n";
605 return 1;
606
607 case Matcher::CheckImmAllZerosV:
608 OS << "OPC_CheckImmAllZerosV,\n";
609601 return 1;
610602
611603 case Matcher::EmitInteger: {
10141006 case Matcher::CheckOrImm: return "OPC_CheckOrImm"; break;
10151007 case Matcher::CheckFoldableChainNode:
10161008 return "OPC_CheckFoldableChainNode"; break;
1017 case Matcher::CheckImmAllOnesV: return "OPC_CheckImmAllOnesV"; break;
1018 case Matcher::CheckImmAllZerosV: return "OPC_CheckImmAllZerosV"; break;
10191009 case Matcher::EmitInteger: return "OPC_EmitInteger"; break;
10201010 case Matcher::EmitStringInteger: return "OPC_EmitStringInteger"; break;
10211011 case Matcher::EmitRegister: return "OPC_EmitRegister"; break;
275275 MatchedComplexPatterns.push_back(std::make_pair(N, InputOperand));
276276 return;
277277 }
278
279 if (LeafRec->getName() == "immAllOnesV")
280 return AddMatcher(new CheckImmAllOnesVMatcher());
281 if (LeafRec->getName() == "immAllZerosV")
282 return AddMatcher(new CheckImmAllZerosVMatcher());
283278
284279 errs() << "Unknown leaf kind: " << *N << "\n";
285280 abort();