llvm.org GIT mirror llvm / abd02b3
ScheduleDAG: Match enum names when printing sdep kinds It is less confusing to have the same names in the debug print as the enum members. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282273 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 3 years ago
6 changed file(s) with 30 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
336336 I != E; ++I) {
337337 dbgs() << " ";
338338 switch (I->getKind()) {
339 case SDep::Data: dbgs() << "val "; break;
340 case SDep::Anti: dbgs() << "anti"; break;
341 case SDep::Output: dbgs() << "out "; break;
342 case SDep::Order: dbgs() << "ch "; break;
339 case SDep::Data: dbgs() << "data "; break;
340 case SDep::Anti: dbgs() << "anti "; break;
341 case SDep::Output: dbgs() << "out "; break;
342 case SDep::Order: dbgs() << "ord "; break;
343343 }
344344 dbgs() << "SU(" << I->getSUnit()->NodeNum << ")";
345345 if (I->isArtificial())
356356 I != E; ++I) {
357357 dbgs() << " ";
358358 switch (I->getKind()) {
359 case SDep::Data: dbgs() << "val "; break;
360 case SDep::Anti: dbgs() << "anti"; break;
361 case SDep::Output: dbgs() << "out "; break;
362 case SDep::Order: dbgs() << "ch "; break;
359 case SDep::Data: dbgs() << "data "; break;
360 case SDep::Anti: dbgs() << "anti "; break;
361 case SDep::Output: dbgs() << "out "; break;
362 case SDep::Order: dbgs() << "ord "; break;
363363 }
364364 dbgs() << "SU(" << I->getSUnit()->NodeNum << ")";
365365 if (I->isArtificial())
1212 ; CHECK: SU(2): STRWui %WZR
1313 ; CHECK: SU(3): %X21, %X20 = LDPXi %SP
1414 ; CHECK: Predecessors:
15 ; CHECK-NEXT: out SU(0)
16 ; CHECK-NEXT: out SU(0)
17 ; CHECK-NEXT: ch SU(0)
15 ; CHECK-NEXT: out SU(0)
16 ; CHECK-NEXT: out SU(0)
17 ; CHECK-NEXT: ord SU(0)
1818 ; CHECK-NEXT: Successors:
1919 define void @test1() {
2020 entry:
77 ; CHECK: shiftable
88 ; CHECK: SU(2): %vreg2 = SUBXri %vreg1, 20, 0
99 ; CHECK: Successors:
10 ; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2
11 ; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2
10 ; CHECK-NEXT: data SU(4): Latency=1 Reg=%vreg2
11 ; CHECK-NEXT: data SU(3): Latency=2 Reg=%vreg2
1212 ; CHECK: ********** INTERVALS **********
1313 define i64 @shiftable(i64 %A, i64 %B) {
1414 %tmp0 = sub i64 %B, 20
66 ; CHECK: misched_bug:BB#0 entry
77 ; CHECK: SU(2): %vreg2 = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0
88 ; CHECK: Successors:
9 ; CHECK-NEXT: val SU(5): Latency=4 Reg=%vreg2
10 ; CHECK-NEXT: ch SU(4): Latency=0
9 ; CHECK-NEXT: data SU(5): Latency=4 Reg=%vreg2
10 ; CHECK-NEXT: ord SU(4): Latency=0
1111 ; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0
1212 ; CHECK: Successors:
13 ; CHECK: ch SU(4): Latency=0
13 ; CHECK: ord SU(4): Latency=0
1414 ; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1
1515 ; CHECK: SU(5): %W0 = COPY %vreg2; GPR32:%vreg2
1616 ; CHECK: ** ScheduleDAGMI::schedule picking next node
3636 ; CHECK: SU({{.*}}): [[VRB]] = LDRXui
3737 ; CHECK-NOT: SU
3838 ; CHECK: Successors:
39 ; CHECK: ch SU([[DEPSTOREB:.*]]): Latency=0
40 ; CHECK: ch SU([[DEPSTOREA:.*]]): Latency=0
39 ; CHECK: ord SU([[DEPSTOREB:.*]]): Latency=0
40 ; CHECK: ord SU([[DEPSTOREA:.*]]): Latency=0
4141
4242 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}},
4343 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}},
55
66 ; CHECK: ** List Scheduling
77 ; CHECK: SU(2){{.*}}STR{{.*}}Volatile
8 ; CHECK-NOT: ch SU
9 ; CHECK: ch SU(3): Latency=1
10 ; CHECK-NOT: ch SU
8 ; CHECK-NOT: ord SU
9 ; CHECK: ord SU(3): Latency=1
10 ; CHECK-NOT: ord SU
1111 ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile
12 ; CHECK-NOT: ch SU
13 ; CHECK: ch SU(2): Latency=1
14 ; CHECK-NOT: ch SU
12 ; CHECK-NOT: ord SU
13 ; CHECK: ord SU(2): Latency=1
14 ; CHECK-NOT: ord SU
1515 ; CHECK: Successors:
1616 ; CHECK: ** List Scheduling
1717 ; CHECK: SU(2){{.*}}STR{{.*}}
18 ; CHECK-NOT: ch SU
19 ; CHECK: ch SU(3): Latency=1
20 ; CHECK-NOT: ch SU
18 ; CHECK-NOT: ord SU
19 ; CHECK: ord SU(3): Latency=1
20 ; CHECK-NOT: ord SU
2121 ; CHECK: SU(3){{.*}}LDR{{.*}}
22 ; CHECK-NOT: ch SU
23 ; CHECK: ch SU(2): Latency=1
24 ; CHECK-NOT: ch SU
22 ; CHECK-NOT: ord SU
23 ; CHECK: ord SU(2): Latency=1
24 ; CHECK-NOT: ord SU
2525 ; CHECK: Successors:
2626 define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
2727 entry: