llvm.org GIT mirror llvm / ab7c09b
Start converting to new error handling API. cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8 Torok Edwin 11 years ago
21 changed file(s) with 93 addition(s) and 95 deletion(s). Raw diff Collapse all Expand all
4848 void llvm_unreachable(void) NORETURN;
4949 }
5050
51 #define LLVM_UNREACHABLE(msg) do { assert(0 && msg); llvm_unreachable(); } while(0);
52
5153 #endif
5254
2525 #include "llvm/CodeGen/MachineLocation.h"
2626 #include "llvm/CodeGen/MachineRegisterInfo.h"
2727 #include "llvm/CodeGen/RegisterScavenging.h"
28 #include "llvm/Support/ErrorHandling.h"
2829 #include "llvm/Target/TargetFrameInfo.h"
2930 #include "llvm/Target/TargetMachine.h"
3031 #include "llvm/Target/TargetOptions.h"
6869 case S30: return 30;
6970 case S31: return 31;
7071 default:
71 assert(0 && "Unknown ARM register!");
72 abort();
72 LLVM_UNREACHABLE("Unknown ARM register!");
7373 }
7474 }
7575
8080 using namespace ARM;
8181 switch (RegEnum) {
8282 default:
83 assert(0 && "Unknown ARM register!");
84 abort();
83 LLVM_UNREACHABLE("Unknown ARM register!");
8584 case R0: case D0: return 0;
8685 case R1: case D1: return 1;
8786 case R2: case D2: return 2;
3434 #include "llvm/ADT/Statistic.h"
3535 #include "llvm/Support/Compiler.h"
3636 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
3739 #ifndef NDEBUG
3840 #include
3941 #endif
220222 template
221223 unsigned Emitter::getShiftOp(unsigned Imm) const {
222224 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
223 default: assert(0 && "Unknown shift opc!");
225 default: LLVM_UNREACHABLE("Unknown shift opc!");
224226 case ARM_AM::asr: return 2;
225227 case ARM_AM::lsl: return 0;
226228 case ARM_AM::lsr: return 1;
254256 else if (MO.isMBB())
255257 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
256258 else {
257 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
258 abort();
259 std::string msg;
260 raw_string_ostream Msg(msg);
261 Msg << "ERROR: Unknown type of MachineOperand: " << MO;
262 llvm_report_error(Msg.str());
259263 }
260264 return 0;
261265 }
335339 NumEmitted++; // Keep track of the # of mi's emitted
336340 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
337341 default: {
338 assert(0 && "Unhandled instruction encoding format!");
342 LLVM_UNREACHABLE("Unhandled instruction encoding format!");
339343 break;
340344 }
341345 case ARMII::Pseudo:
453457 else if (CFP->getType() == Type::DoubleTy)
454458 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
455459 else {
456 assert(0 && "Unable to handle this constantpool entry!");
457 abort();
460 LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
458461 }
459462 } else {
460 assert(0 && "Unable to handle this constantpool entry!");
461 abort();
463 LLVM_UNREACHABLE("Unable to handle this constantpool entry!");
462464 }
463465 }
464466 }
585587 unsigned Opcode = MI.getDesc().Opcode;
586588 switch (Opcode) {
587589 default:
588 abort(); // FIXME:
590 llvm_report_error("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
589591 case TargetInstrInfo::INLINEASM: {
590592 // We allow inline assembler nodes with empty bodies - they can
591593 // implicitly define registers, which is ok for JIT.
592594 if (MI.getOperand(0).getSymbolName()[0]) {
593 assert(0 && "JIT does not support inline asm!\n");
594 abort();
595 llvm_report_error("JIT does not support inline asm!\n");
595596 }
596597 break;
597598 }
673674 // ROR - 0111
674675 // RRX - 0110 and bit[11:8] clear.
675676 switch (SOpc) {
676 default: assert(0 && "Unknown shift opc!");
677 default: LLVM_UNREACHABLE("Unknown shift opc!");
677678 case ARM_AM::lsl: SBits = 0x1; break;
678679 case ARM_AM::lsr: SBits = 0x3; break;
679680 case ARM_AM::asr: SBits = 0x5; break;
687688 // ASR - 100
688689 // ROR - 110
689690 switch (SOpc) {
690 default: assert(0 && "Unknown shift opc!");
691 default: LLVM_UNREACHABLE("Unknown shift opc!");
691692 case ARM_AM::lsl: SBits = 0x0; break;
692693 case ARM_AM::lsr: SBits = 0x2; break;
693694 case ARM_AM::asr: SBits = 0x4; break;
740741 const TargetInstrDesc &TID = MI.getDesc();
741742
742743 if (TID.Opcode == ARM::BFC) {
743 cerr << "ERROR: ARMv6t2 JIT is not yet supported.\n";
744 abort();
744 llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported.");
745745 }
746746
747747 // Part of binary is determined by TableGn.
955955 // DA - Decrement after - bit U = 0 and bit P = 0
956956 // DB - Decrement before - bit U = 0 and bit P = 1
957957 switch (Mode) {
958 default: assert(0 && "Unknown addressing sub-mode!");
958 default: LLVM_UNREACHABLE("Unknown addressing sub-mode!");
959959 case ARM_AM::da: break;
960960 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
961961 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
11191119 const TargetInstrDesc &TID = MI.getDesc();
11201120
11211121 if (TID.Opcode == ARM::TPsoft)
1122 abort(); // FIXME
1122 llvm_report_error("ARM::TPsoft FIXME"); // FIXME
11231123
11241124 // Part of binary is determined by TableGn.
11251125 unsigned Binary = getBinaryCodeForInstr(MI);
3535 #include "llvm/CodeGen/SelectionDAG.h"
3636 #include "llvm/Target/TargetOptions.h"
3737 #include "llvm/ADT/VectorExtras.h"
38 #include "llvm/Support/ErrorHandling.h"
3839 #include "llvm/Support/MathExtras.h"
3940 using namespace llvm;
4041
22572258
22582259 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
22592260 switch (Op.getOpcode()) {
2260 default: assert(0 && "Don't know how to custom lower this!"); abort();
2261 default: LLVM_UNREACHABLE("Don't know how to custom lower this!");
22612262 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
22622263 case ISD::GlobalAddress:
22632264 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
25922593 case Intrinsic::arm_neon_vshiftlu:
25932594 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
25942595 break;
2595 assert(0 && "invalid shift count for vshll intrinsic");
2596 abort();
2596 LLVM_UNREACHABLE("invalid shift count for vshll intrinsic");
25972597
25982598 case Intrinsic::arm_neon_vrshifts:
25992599 case Intrinsic::arm_neon_vrshiftu:
26102610 case Intrinsic::arm_neon_vqshiftsu:
26112611 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
26122612 break;
2613 assert(0 && "invalid shift count for vqshlu intrinsic");
2614 abort();
2613 LLVM_UNREACHABLE("invalid shift count for vqshlu intrinsic");
26152614
26162615 case Intrinsic::arm_neon_vshiftn:
26172616 case Intrinsic::arm_neon_vrshiftn:
26242623 // Narrowing shifts require an immediate right shift.
26252624 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
26262625 break;
2627 assert(0 && "invalid shift count for narrowing vector shift intrinsic");
2628 abort();
2626 LLVM_UNREACHABLE("invalid shift count for narrowing vector shift intrinsic");
26292627
26302628 default:
26312629 assert(0 && "unhandled vector shift");
26862684 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
26872685 VShiftOpc = ARMISD::VSRI;
26882686 else {
2689 assert(0 && "invalid shift count for vsli/vsri intrinsic");
2690 abort();
2687 LLVM_UNREACHABLE("invalid shift count for vsli/vsri intrinsic");
26912688 }
26922689
26932690 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2020 #include "llvm/CodeGen/JITCodeEmitter.h"
2121 #include "llvm/Config/alloca.h"
2222 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
2324 #include "llvm/Support/Streams.h"
2425 #include "llvm/System/Memory.h"
2526 #include
2627 using namespace llvm;
2728
2829 void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
29 abort();
30 llvm_report_error("ARMJITInfo::replaceMachineCodeForFunction");
3031 }
3132
3233 /// JITCompilerFunction - This contains the address of the JIT function used to
102103 );
103104 #else // Not an ARM host
104105 void ARMCompilationCallback() {
105 assert(0 && "Cannot call ARMCompilationCallback() on a non-ARM arch!\n");
106 abort();
106 LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!\n");
107107 }
108108 #endif
109109 }
122122 // ldr pc, [pc,#-4]
123123 //
124124 if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
125 cerr << "ERROR: Unable to mark stub writable\n";
126 abort();
125 llvm_report_error("ERROR: Unable to mark stub writable");
127126 }
128127 *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4]
129128 *(intptr_t *)(StubAddr+4) = NewVal;
130129 if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
131 cerr << "ERROR: Unable to mark stub executable\n";
132 abort();
130 llvm_report_error("ERROR: Unable to mark stub executable");
133131 }
134132 }
135133
2828 #include "llvm/Target/TargetMachine.h"
2929 #include "llvm/Target/TargetRegisterInfo.h"
3030 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/ErrorHandling.h"
3132 #include "llvm/ADT/DenseMap.h"
3233 #include "llvm/ADT/STLExtras.h"
3334 #include "llvm/ADT/SmallPtrSet.h"
118119 case ARM::FSTD:
119120 NumFSTMGened++;
120121 return ARM::FSTMD;
121 default: abort();
122 default: llvm_report_error("Unhandled opcode!");
122123 }
123124 return 0;
124125 }
440441 case ARM::FLDD: return ARM::FLDMD;
441442 case ARM::FSTS: return ARM::FSTMS;
442443 case ARM::FSTD: return ARM::FSTMD;
443 default: abort();
444 default: llvm_report_error("Unhandled opcode!");
444445 }
445446 return 0;
446447 }
453454 case ARM::FLDD: return ARM::FLDMD;
454455 case ARM::FSTS: return ARM::FSTMS;
455456 case ARM::FSTD: return ARM::FSTMD;
456 default: abort();
457 default: llvm_report_error("Unhandled opcode!");
457458 }
458459 return 0;
459460 }
2525 #include "llvm/CodeGen/MachineLocation.h"
2626 #include "llvm/CodeGen/MachineRegisterInfo.h"
2727 #include "llvm/CodeGen/RegisterScavenging.h"
28 #include "llvm/Support/ErrorHandling.h"
2829 #include "llvm/Target/TargetFrameInfo.h"
2930 #include "llvm/Target/TargetMachine.h"
3031 #include "llvm/Target/TargetOptions.h"
289290 break;
290291 }
291292 default:
292 assert(0 && "Unsupported addressing mode!");
293 abort();
293 LLVM_UNREACHABLE("Unsupported addressing mode!");
294294 break;
295295 }
296296
2929 #include "llvm/ADT/BitVector.h"
3030 #include "llvm/ADT/SmallVector.h"
3131 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/ErrorHandling.h"
3233 using namespace llvm;
3334
3435 static cl::opt
451452 break;
452453 }
453454 default:
454 assert(0 && "Unsupported addressing mode!");
455 abort();
455 LLVM_UNREACHABLE("Unsupported addressing mode!");
456456 break;
457457 }
458458
2929 #include "llvm/ADT/BitVector.h"
3030 #include "llvm/ADT/SmallVector.h"
3131 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/ErrorHandling.h"
3233 using namespace llvm;
3334
3435 static cl::opt
451452 break;
452453 }
453454 default:
454 assert(0 && "Unsupported addressing mode!");
455 abort();
455 llvm_report_error("Unsupported addressing mode!");
456456 break;
457457 }
458458
1515 #include "llvm/MC/MCInst.h"
1616 #include "X86ATTAsmPrinter.h"
1717 #include "llvm/Target/TargetAsmInfo.h"
18 #include "llvm/Support/ErrorHandling.h"
1819 #include "llvm/Support/raw_ostream.h"
1920 using namespace llvm;
2021
102103 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
103104 O << DispVal;
104105 } else {
105 abort();
106 llvm_report_error("non-immediate displacement for LEA?");
106107 //assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
107108 // DispSpec.isJTI() || DispSpec.isSymbol());
108109 //printOperand(MI, Op+3, "mem");
3030 #include "llvm/ADT/Statistic.h"
3131 #include "llvm/Support/Compiler.h"
3232 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
3335 #include "llvm/Target/TargetOptions.h"
3436 using namespace llvm;
3537
555557 // We allow inline assembler nodes with empty bodies - they can
556558 // implicitly define registers, which is ok for JIT.
557559 if (MI.getOperand(0).getSymbolName()[0]) {
558 assert(0 && "JIT does not support inline asm!\n");
559 abort();
560 llvm_report_error("JIT does not support inline asm!");
560561 }
561562 break;
562563 }
804805 }
805806
806807 if (!Desc->isVariadic() && CurOp != NumOps) {
807 cerr << "Cannot encode: ";
808 MI.dump();
809 cerr << '\n';
810 abort();
811 }
812 }
813
808 std::string msg;
809 raw_string_ostream Msg(msg);
810 Msg << "Cannot encode: " << MI;
811 llvm_report_error(Msg.str());
812 }
813 }
814
3232 #include "llvm/CodeGen/PseudoSourceValue.h"
3333 #include "llvm/Support/MathExtras.h"
3434 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
3536 #include "llvm/Target/TargetOptions.h"
3637 #include "llvm/ADT/SmallSet.h"
3738 #include "llvm/ADT/StringExtras.h"
60536054 SDValue SrcPtr = Op.getOperand(1);
60546055 SDValue SrcSV = Op.getOperand(2);
60556056
6056 assert(0 && "VAArgInst is not yet implemented for x86-64!");
6057 abort();
6057 LLVM_UNREACHABLE("VAArgInst is not yet implemented for x86-64!");
60586058 return SDValue();
60596059 }
60606060
62556255 case Intrinsic::x86_mmx_psrai_d:
62566256 NewIntNo = Intrinsic::x86_mmx_psra_d;
62576257 break;
6258 default: abort(); // Can't reach here.
6258 default: LLVM_UNREACHABLE("Impossible intrinsic"); // Can't reach here.
62596259 }
62606260 break;
62616261 }
64276427 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
64286428
64296429 if (InRegCount > 2) {
6430 cerr << "Nest register in use - reduce number of inreg parameters!\n";
6431 abort();
6430 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
64326431 }
64336432 }
64346433 break;
2626 #include "llvm/CodeGen/MachineRegisterInfo.h"
2727 #include "llvm/CodeGen/LiveVariables.h"
2828 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
2931 #include "llvm/Target/TargetOptions.h"
3032 #include "llvm/Target/TargetAsmInfo.h"
3133 using namespace llvm;
18881890 } else if (RC == &X86::VR64RegClass) {
18891891 Opc = X86::MMX_MOVQ64mr;
18901892 } else {
1891 assert(0 && "Unknown regclass");
1892 abort();
1893 LLVM_UNREACHABLE("Unknown regclass");
18931894 }
18941895
18951896 return Opc;
19811982 } else if (RC == &X86::VR64RegClass) {
19821983 Opc = X86::MMX_MOVQ64rm;
19831984 } else {
1984 assert(0 && "Unknown regclass");
1985 abort();
1985 LLVM_UNREACHABLE("Unknown regclass");
19861986 }
19871987
19881988 return Opc;
31953195 }
31963196
31973197 if (!Desc->isVariadic() && CurOp != NumOps) {
3198 cerr << "Cannot determine size: ";
3199 MI.dump();
3200 cerr << '\n';
3201 abort();
3198 std::string msg;
3199 raw_string_ostream Msg(msg);
3200 Msg << "Cannot determine size: " << MI;
3201 llvm_report_error(Msg.str());
32023202 }
32033203
32043204
1717 #include "llvm/Function.h"
1818 #include "llvm/Config/alloca.h"
1919 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/ErrorHandling.h"
2021 #include
2122 #include
2223 using namespace llvm;
320321
321322 #else // Not an i386 host
322323 void X86CompilationCallback() {
323 assert(0 && "Cannot call X86CompilationCallback() on a non-x86 arch!\n");
324 abort();
324 LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!\n");
325325 }
326326 #endif
327327 }
3030 #include "llvm/ADT/StringExtras.h"
3131 #include "llvm/ADT/STLExtras.h"
3232 #include "llvm/Support/CFG.h"
33 #include "llvm/Support/ErrorHandling.h"
3334 #include "llvm/Support/MathExtras.h"
3435 #include "llvm/Support/raw_ostream.h"
3536 #include
12331234 case GlobalValue::ExternalWeakLinkage: Out << "extern_weak "; break;
12341235 case GlobalValue::ExternalLinkage: break;
12351236 case GlobalValue::GhostLinkage:
1236 Out << "GhostLinkage not allowed in AsmWriter!\n";
1237 abort();
1237 llvm_report_error("GhostLinkage not allowed in AsmWriter!");
12381238 }
12391239 }
12401240
1818 #include "llvm/LLVMContext.h"
1919 #include "llvm/Module.h"
2020 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/Support/ErrorHandling.h"
2122 #include "llvm/Support/LeakDetector.h"
2223 using namespace llvm;
2324
7677 /// Override destroyConstant to make sure it doesn't get called on
7778 /// GlobalValue's because they shouldn't be treated like other constants.
7879 void GlobalValue::destroyConstant() {
79 assert(0 && "You can't GV->destroyConstant()!");
80 abort();
80 LLVM_UNREACHABLE("You can't GV->destroyConstant()!");
8181 }
8282
8383 /// copyAttributesFrom - copy all additional attributes (those not needed to
246246 CE->getOpcode() == Instruction::GetElementPtr))
247247 return dyn_cast(CE->getOperand(0));
248248 else
249 assert(0 && "Unsupported aliasee");
249 LLVM_UNREACHABLE("Unsupported aliasee");
250250 }
251251 }
252252 return 0;
1515 #include "llvm/DerivedTypes.h"
1616 #include "llvm/Function.h"
1717 #include "llvm/Instructions.h"
18 #include "llvm/Support/ErrorHandling.h"
1819 #include "llvm/Support/CallSite.h"
1920 #include "llvm/Support/ConstantRange.h"
2021 #include "llvm/Support/MathExtras.h"
533534 /// Out-of-line ReturnInst method, put here so the C++ compiler can choose to
534535 /// emit the vtable for the class in this translation unit.
535536 void ReturnInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) {
536 assert(0 && "ReturnInst has no successors!");
537 LLVM_UNREACHABLE("ReturnInst has no successors!");
537538 }
538539
539540 BasicBlock *ReturnInst::getSuccessorV(unsigned idx) const {
540 assert(0 && "ReturnInst has no successors!");
541 abort();
541 LLVM_UNREACHABLE("ReturnInst has no successors!");
542542 return 0;
543543 }
544544
562562 }
563563
564564 void UnwindInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) {
565 assert(0 && "UnwindInst has no successors!");
565 LLVM_UNREACHABLE("UnwindInst has no successors!");
566566 }
567567
568568 BasicBlock *UnwindInst::getSuccessorV(unsigned idx) const {
569 assert(0 && "UnwindInst has no successors!");
570 abort();
569 LLVM_UNREACHABLE("UnwindInst has no successors!");
571570 return 0;
572571 }
573572
587586 }
588587
589588 void UnreachableInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) {
590 assert(0 && "UnwindInst has no successors!");
589 LLVM_UNREACHABLE("UnwindInst has no successors!");
591590 }
592591
593592 BasicBlock *UnreachableInst::getSuccessorV(unsigned idx) const {
594 assert(0 && "UnwindInst has no successors!");
595 abort();
593 LLVM_UNREACHABLE("UnwindInst has no successors!");
596594 return 0;
597595 }
598596
22942292 PTy = NULL;
22952293 return BitCast; // same size, no-op cast
22962294 } else {
2297 assert(0 && "Casting pointer or non-first class to float");
2295 LLVM_UNREACHABLE("Casting pointer or non-first class to float");
22982296 }
22992297 } else if (const VectorType *DestPTy = dyn_cast(DestTy)) {
23002298 if (const VectorType *SrcPTy = dyn_cast(SrcTy)) {
1616 #include "llvm/Support/Timer.h"
1717 #include "llvm/Module.h"
1818 #include "llvm/ModuleProvider.h"
19 #include "llvm/Support/ErrorHandling.h"
1920 #include "llvm/Support/Streams.h"
2021 #include "llvm/Support/ManagedStatic.h"
2122 #include "llvm/Support/raw_ostream.h"
12471248 bool FunctionPassManager::run(Function &F) {
12481249 std::string errstr;
12491250 if (MP->materializeFunction(&F, &errstr)) {
1250 cerr << "Error reading bitcode file: " << errstr << "\n";
1251 abort();
1251 llvm_report_error("Error reading bitcode file: " + errstr);
12521252 }
12531253 return FPM->run(F);
12541254 }
1919 #include "llvm/ADT/STLExtras.h"
2020 #include "llvm/Support/Compiler.h"
2121 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
2223 #include "llvm/Support/ManagedStatic.h"
2324 #include "llvm/Support/MathExtras.h"
2425 #include "llvm/Support/raw_ostream.h"
263264 }
264265
265266 void Type::refineAbstractType(const DerivedType *OldTy, const Type *NewTy) {
266 abort();
267 llvm_report_error("Attempting to refine a derived type!");
267268 }
268269 void Type::typeBecameConcrete(const DerivedType *AbsTy) {
269 abort();
270 llvm_report_error("DerivedType is already a concrete type!");
270271 }
271272
272273
1818 #include "llvm/Module.h"
1919 #include "llvm/ValueSymbolTable.h"
2020 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
2122 #include "llvm/Support/LeakDetector.h"
2223 #include "llvm/Support/ManagedStatic.h"
2324 #include "llvm/Support/ValueHandle.h"
513514 cerr << "While deleting: " << *V->getType() << " %" << V->getNameStr()
514515 << "\n";
515516 #endif
516 cerr << "An asserting value handle still pointed to this value!\n";
517 abort();
517 llvm_report_error("An asserting value handle still pointed to this"
518 "value!");
518519 case Weak:
519520 // Weak just goes to null, which will unlink it from the list.
520521 ThisNode->operator=(0);
6161 #include "llvm/ADT/StringExtras.h"
6262 #include "llvm/ADT/STLExtras.h"
6363 #include "llvm/Support/Compiler.h"
64 #include "llvm/Support/ErrorHandling.h"
6465 #include "llvm/Support/raw_ostream.h"
6566 #include
6667 #include
9293 }
9394
9495 if (Broken)
95 abort();
96 llvm_report_error("Broken module, no Basic Block terminator!");
9697
9798 return false;
9899 }
209210 default: assert(0 && "Unknown action");
210211 case AbortProcessAction:
211212 msgs << "compilation aborted!\n";
212 cerr << msgs.str();
213 abort();
213 llvm_report_error(msgs.str());
214214 case PrintMessageAction:
215215 msgs << "verification continues.\n";
216216 cerr << msgs.str();