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Baby steps towards ARM fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 10 years ago
6 changed file(s) with 104 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
0 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the ARM-specific support for the FastISel class. Some
10 // of the target-specific code is generated by tablegen in the file
11 // ARMGenFastISel.inc, which is #included here.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "ARM.h"
16 #include "ARMRegisterInfo.h"
17 #include "ARMTargetMachine.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/IntrinsicInst.h"
24 #include "llvm/CodeGen/Analysis.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/Support/CallSite.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/GetElementPtrTypeIterator.h"
33 #include "llvm/Target/TargetOptions.h"
34 using namespace llvm;
35
36 namespace {
37
38 class ARMFastISel : public FastISel {
39
40 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
41 /// make the right decision when generating code for different targets.
42 const ARMSubtarget *Subtarget;
43
44 public:
45 explicit ARMFastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
46 Subtarget = &TM.getSubtarget();
47 }
48
49 virtual bool TargetSelectInstruction(const Instruction *I);
50
51 #include "ARMGenFastISel.inc"
52
53 };
54
55 } // end anonymous namespace
56
57 // #include "ARMGenCallingConv.inc"
58
59 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
60 switch (I->getOpcode()) {
61 default: break;
62 }
63 return false;
64 }
65
66 namespace llvm {
67 llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
68 return new ARMFastISel(funcInfo);
69 }
70 }
693693 return TargetLowering::getRegClassFor(VT);
694694 }
695695
696 // Create a fast isel object.
697 FastISel *
698 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
699 return ARM::createFastISel(funcInfo);
700 }
701
696702 /// getFunctionAlignment - Return the Log2 alignment of this function.
697703 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
698704 return getTargetMachine().getSubtarget().isThumb() ? 1 : 2;
1616
1717 #include "ARMSubtarget.h"
1818 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/FastISel.h"
1920 #include "llvm/CodeGen/SelectionDAG.h"
2021 #include "llvm/CodeGen/CallingConvLower.h"
2122 #include
259260
260261 /// getFunctionAlignment - Return the Log2 alignment of this function.
261262 virtual unsigned getFunctionAlignment(const Function *F) const;
263
264 /// createFastISel - This method returns a target specific FastISel object,
265 /// or null if the target does not support "fast" ISel.
266 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
262267
263268 Sched::Preference getSchedulingPreference(SDNode *N) const;
264269
386391 unsigned BinOpcode) const;
387392
388393 };
394
395 namespace ARM {
396 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
397 }
389398 }
390399
391400 #endif // ARMISELLOWERING_H
1010 tablegen(ARMGenCallingConv.inc -gen-callingconv)
1111 tablegen(ARMGenSubtarget.inc -gen-subtarget)
1212 tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
13 tablegen(ARMFastISel.inc -gen-fast-isel)
1314
1415 add_llvm_target(ARMCodeGen
1516 ARMAsmPrinter.cpp
1616 ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
1717 ARMGenDAGISel.inc ARMGenSubtarget.inc \
1818 ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
19 ARMGenDecoderTables.inc ARMGenEDInfo.inc
19 ARMGenDecoderTables.inc ARMGenEDInfo.inc \
20 ARMGenFastISel.inc
2021
2122 DIRS = AsmPrinter AsmParser Disassembler TargetInfo
2223
0 ; RUN: llc < %s -fast-isel -fast-isel-abort -march=arm
1
2 ; Very basic fast-isel functionality.
3
4 define i32 @add(i32 %a, i32 %b) nounwind ssp {
5 entry:
6 %a.addr = alloca i32, align 4
7 %b.addr = alloca i32, align 4
8 store i32 %a, i32* %a.addr
9 store i32 %b, i32* %b.addr
10 %tmp = load i32* %a.addr
11 %tmp1 = load i32* %b.addr
12 %add = add nsw i32 %tmp, %tmp1
13 ret i32 %add
14 }