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Improved generated code for atomic operators git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50677 91177308-0d34-0410-b5e6-96231b3b80d8 Mon P Wang 12 years ago
1 changed file(s) with 16 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
57525752 // For the atomic bitwise operator, we generate
57535753 // thisMBB:
57545754 // newMBB:
5755 // ld EAX = [bitinstr.addr]
5756 // mov t1 = EAX
5757 // op t2 = t1, [bitinstr.val]
5755 // ld t1 = [bitinstr.addr]
5756 // op t2 = t1, [bitinstr.val]
5757 // mov EAX = t1
57585758 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
57595759 // bz newMBB
57605760 // fallthrough -->nextMBB
57935793 int lastAddrIndx = 3; // [0,3]
57945794 int valArgIndx = 4;
57955795
5796 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), X86::EAX);
5796 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5797 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
57975798 for (int i=0; i <= lastAddrIndx; ++i)
57985799 (*MIB).addOperand(*argOpers[i]);
5799
5800 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5801 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t1);
5802 MIB.addReg(X86::EAX);
58035800
58045801 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
58055802 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
58115808 MIB.addReg(t1);
58125809 (*MIB).addOperand(*argOpers[valArgIndx]);
58135810
5811 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
5812 MIB.addReg(t1);
5813
58145814 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
58155815 for (int i=0; i <= lastAddrIndx; ++i)
58165816 (*MIB).addOperand(*argOpers[i]);
58345834 // For the atomic min/max operator, we generate
58355835 // thisMBB:
58365836 // newMBB:
5837 // ld EAX = [min/max.addr]
5838 // mov t1 = EAX
5837 // ld t1 = [min/max.addr]
58395838 // mov t2 = [min/max.val]
58405839 // cmp t1, t2
58415840 // cmov[cond] t2 = t1
5841 // mov EAX = t1
58425842 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
58435843 // bz newMBB
58445844 // fallthrough -->nextMBB
58785878 int lastAddrIndx = 3; // [0,3]
58795879 int valArgIndx = 4;
58805880
5881 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), X86::EAX);
5881 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5882 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
58825883 for (int i=0; i <= lastAddrIndx; ++i)
58835884 (*MIB).addOperand(*argOpers[i]);
5884
5885 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
5886 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t1);
5887 MIB.addReg(X86::EAX);
5888
5885
58895886 // We only support register and immediate values
58905887 assert( (argOpers[valArgIndx]->isReg() || argOpers[valArgIndx]->isImm())
58915888 && "invalid operand");
58965893 else
58975894 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
58985895 (*MIB).addOperand(*argOpers[valArgIndx]);
5896
5897 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
5898 MIB.addReg(t1);
58995899
59005900 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
59015901 MIB.addReg(t1);