llvm.org GIT mirror llvm / ab0b15d
[X86] Refactor the prologue emission to prepare for shrink-wrapping. - Add a late pass to expand pseudo instructions (tail call and EH returns). Instead of doing it in the prologue emission. - Factor some static methods in X86FrameLowering to ease code sharing. NFC. Related to <rdar://problem/20821487> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237977 91177308-0d34-0410-b5e6-96231b3b80d8 Quentin Colombet 5 years ago
7 changed file(s) with 251 addition(s) and 112 deletion(s). Raw diff Collapse all Expand all
1414 set(sources
1515 X86AsmPrinter.cpp
1616 X86CallFrameOptimization.cpp
17 X86ExpandPseudo.cpp
1718 X86FastISel.cpp
1819 X86FloatingPoint.cpp
1920 X86FrameLowering.cpp
7474 /// preparation.
7575 FunctionPass *createX86WinEHStatePass();
7676
77 /// Return a Machine IR pass that expands X86-specific pseudo
78 /// instructions into a sequence of actual instructions. This pass
79 /// must run after prologue/epilogue insertion and before lowering
80 /// the MachineInstr to MC.
81 FunctionPass *createX86ExpandPseudoPass();
7782 } // End llvm namespace
7883
7984 #endif
0 //===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions to allow proper scheduling, if-conversion, other late
11 // optimizations, or simply the encoding of the instructions.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "X86.h"
16 #include "X86FrameLowering.h"
17 #include "X86InstrBuilder.h"
18 #include "X86InstrInfo.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/IR/GlobalValue.h"
25 using namespace llvm;
26
27 #define DEBUG_TYPE "x86-pseudo"
28
29 namespace {
30 class X86ExpandPseudo : public MachineFunctionPass {
31 public:
32 static char ID;
33 X86ExpandPseudo() : MachineFunctionPass(ID) {}
34
35 void getAnalysisUsage(AnalysisUsage &AU) const override {
36 AU.setPreservesCFG();
37 AU.addPreservedID(MachineLoopInfoID);
38 AU.addPreservedID(MachineDominatorsID);
39 MachineFunctionPass::getAnalysisUsage(AU);
40 }
41
42 const X86Subtarget *STI;
43 const X86InstrInfo *TII;
44 const X86RegisterInfo *TRI;
45 const X86FrameLowering *X86FrameLowering;
46
47 bool runOnMachineFunction(MachineFunction &Fn) override;
48
49 const char *getPassName() const override {
50 return "X86 pseudo instruction expansion pass";
51 }
52
53 private:
54 bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
55 bool ExpandMBB(MachineBasicBlock &MBB);
56 };
57 char X86ExpandPseudo::ID = 0;
58 } // End anonymous namespace.
59
60 /// If \p MBBI is a pseudo instruction, this method expands
61 /// it to the corresponding (sequence of) actual instruction(s).
62 /// \returns true if \p MBBI has been expanded.
63 bool X86ExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator MBBI) {
65 MachineInstr &MI = *MBBI;
66 unsigned Opcode = MI.getOpcode();
67 DebugLoc DL = MBBI->getDebugLoc();
68 switch (Opcode) {
69 default:
70 return false;
71 case X86::TCRETURNdi:
72 case X86::TCRETURNri:
73 case X86::TCRETURNmi:
74 case X86::TCRETURNdi64:
75 case X86::TCRETURNri64:
76 case X86::TCRETURNmi64: {
77 bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64;
78 MachineOperand &JumpTarget = MBBI->getOperand(0);
79 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
80 assert(StackAdjust.isImm() && "Expecting immediate value.");
81
82 // Adjust stack pointer.
83 int StackAdj = StackAdjust.getImm();
84
85 if (StackAdj) {
86 bool Is64Bit = STI->is64Bit();
87 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
88 const bool Uses64BitFramePtr =
89 STI->isTarget64BitLP64() || STI->isTargetNaCl64();
90 bool UseLEAForSP =
91 X86FrameLowering->useLEAForSPInProlog(*MBB.getParent());
92 unsigned StackPtr = TRI->getStackRegister();
93 // Check for possible merge with preceding ADD instruction.
94 StackAdj += X86FrameLowering::mergeSPUpdates(MBB, MBBI, StackPtr, true);
95 X86FrameLowering::emitSPUpdate(MBB, MBBI, StackPtr, StackAdj, Is64Bit,
96 Uses64BitFramePtr, UseLEAForSP, *TII,
97 *TRI);
98 }
99
100 // Jump to label or value in register.
101 bool IsWin64 = STI->isTargetWin64();
102 if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdi64) {
103 unsigned Op = (Opcode == X86::TCRETURNdi)
104 ? X86::TAILJMPd
105 : (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);
106 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
107 if (JumpTarget.isGlobal())
108 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
109 JumpTarget.getTargetFlags());
110 else {
111 assert(JumpTarget.isSymbol());
112 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
113 JumpTarget.getTargetFlags());
114 }
115 } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64) {
116 unsigned Op = (Opcode == X86::TCRETURNmi)
117 ? X86::TAILJMPm
118 : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
119 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
120 for (unsigned i = 0; i != 5; ++i)
121 MIB.addOperand(MBBI->getOperand(i));
122 } else if (Opcode == X86::TCRETURNri64) {
123 BuildMI(MBB, MBBI, DL,
124 TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
125 .addReg(JumpTarget.getReg(), RegState::Kill);
126 } else {
127 BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
128 .addReg(JumpTarget.getReg(), RegState::Kill);
129 }
130
131 MachineInstr *NewMI = std::prev(MBBI);
132 NewMI->copyImplicitOps(*MBBI->getParent()->getParent(), MBBI);
133
134 // Delete the pseudo instruction TCRETURN.
135 MBB.erase(MBBI);
136
137 return true;
138 }
139 case X86::EH_RETURN:
140 case X86::EH_RETURN64: {
141 MachineOperand &DestAddr = MBBI->getOperand(0);
142 assert(DestAddr.isReg() && "Offset should be in register!");
143 const bool Uses64BitFramePtr =
144 STI->isTarget64BitLP64() || STI->isTargetNaCl64();
145 unsigned StackPtr = TRI->getStackRegister();
146 BuildMI(MBB, MBBI, DL,
147 TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
148 .addReg(DestAddr.getReg());
149 // The EH_RETURN pseudo is really removed during the MC Lowering.
150 return true;
151 }
152 }
153 llvm_unreachable("Previous switch has a fallthrough?");
154 }
155
156 /// Expand all pseudo instructions contained in \p MBB.
157 /// \returns true if any expansion occurred for \p MBB.
158 bool X86ExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
159 bool Modified = false;
160
161 // MBBI may be invalidated by the expansion.
162 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
163 while (MBBI != E) {
164 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
165 Modified |= ExpandMI(MBB, MBBI);
166 MBBI = NMBBI;
167 }
168
169 return Modified;
170 }
171
172 bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
173 STI = &static_cast(MF.getSubtarget());
174 TII = STI->getInstrInfo();
175 TRI = STI->getRegisterInfo();
176 X86FrameLowering = STI->getFrameLowering();
177
178 bool Modified = false;
179 for (MachineBasicBlock &MBB : MF)
180 Modified |= ExpandMBB(MBB);
181 return Modified;
182 }
183
184 /// Returns an instance of the pseudo instruction expansion pass.
185 FunctionPass *llvm::createX86ExpandPseudoPass() {
186 return new X86ExpandPseudo();
187 }
204204
205205 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
206206 /// stack pointer by a constant value.
207 static
208 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
209 unsigned StackPtr, int64_t NumBytes,
210 bool Is64BitTarget, bool Is64BitStackPtr, bool UseLEA,
211 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
207 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
208 MachineBasicBlock::iterator &MBBI,
209 unsigned StackPtr, int64_t NumBytes,
210 bool Is64BitTarget, bool Is64BitStackPtr,
211 bool UseLEA, const TargetInstrInfo &TII,
212 const TargetRegisterInfo &TRI) {
212213 bool isSub = NumBytes < 0;
213214 uint64_t Offset = isSub ? -NumBytes : NumBytes;
214215 unsigned Opc;
311312 }
312313 }
313314
314 /// mergeSPUpdates - Checks the instruction before/after the passed
315 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
316 /// the stack adjustment is returned as a positive value for ADD/LEA and a
317 /// negative for SUB.
318 static int mergeSPUpdates(MachineBasicBlock &MBB,
319 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
320 bool doMergeWithPrevious) {
315 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
316 MachineBasicBlock::iterator &MBBI,
317 unsigned StackPtr,
318 bool doMergeWithPrevious) {
321319 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
322320 (!doMergeWithPrevious && MBBI == MBB.end()))
323321 return 0;
966964 }
967965 }
968966
967 bool X86FrameLowering::useLEAForSPInProlog(const MachineFunction &MF) const {
968 // We can't use LEA instructions for adjusting the stack pointer if this is a
969 // leaf function in the Win64 ABI. Only ADD instructions may be used to
970 // deallocate the stack.
971 // This means that we can use LEA for SP in two situations:
972 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
973 // 2. We *have* a frame pointer which means we are permitted to use LEA.
974 return MF.getSubtarget().useLeaForSP() &&
975 (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF));
976 }
977
969978 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
970979 MachineBasicBlock &MBB) const {
971980 const MachineFrameInfo *MFI = MF.getFrameInfo();
973982 const X86Subtarget &STI = MF.getSubtarget();
974983 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
975984 const TargetInstrInfo &TII = *STI.getInstrInfo();
976 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
985 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
977986 assert(MBBI != MBB.end() && "Returning block has no instructions");
978 unsigned RetOpcode = MBBI->getOpcode();
979987 DebugLoc DL = MBBI->getDebugLoc();
980988 bool Is64Bit = STI.is64Bit();
981989 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
982990 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
983 bool HasFP = hasFP(MF);
984991 const bool Is64BitILP32 = STI.isTarget64BitILP32();
985992 unsigned SlotSize = RegInfo->getSlotSize();
986993 unsigned FramePtr = RegInfo->getFrameRegister(MF);
991998
992999 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
9931000 bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
994 bool UseLEAForSP = false;
995
996 // We can't use LEA instructions for adjusting the stack pointer if this is a
997 // leaf function in the Win64 ABI. Only ADD instructions may be used to
998 // deallocate the stack.
999 if (STI.useLeaForSP()) {
1000 if (!IsWinEH) {
1001 // We *aren't* using the Win64 ABI which means we are free to use LEA.
1002 UseLEAForSP = true;
1003 } else if (HasFP) {
1004 // We *have* a frame pointer which means we are permitted to use LEA.
1005 UseLEAForSP = true;
1006 }
1007 }
1008
1009 switch (RetOpcode) {
1001 bool UseLEAForSP = useLEAForSPInProlog(MF);
1002
1003 switch (MBBI->getOpcode()) {
10101004 default:
10111005 llvm_unreachable("Can only insert epilogue into returning blocks");
10121006 case X86::RETQ:
11111105 if (NeedsWinEH)
11121106 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
11131107
1114 // We're returning from function via eh_return.
1115 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1116 MBBI = MBB.getLastNonDebugInstr();
1117 MachineOperand &DestAddr = MBBI->getOperand(0);
1118 assert(DestAddr.isReg() && "Offset should be in register!");
1119 BuildMI(MBB, MBBI, DL,
1120 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1121 StackPtr).addReg(DestAddr.getReg());
1122 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1123 RetOpcode == X86::TCRETURNmi ||
1124 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1125 RetOpcode == X86::TCRETURNmi64) {
1126 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1127 // Tail call return: adjust the stack pointer and jump to callee.
1128 MBBI = MBB.getLastNonDebugInstr();
1129 MachineOperand &JumpTarget = MBBI->getOperand(0);
1130 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1131 assert(StackAdjust.isImm() && "Expecting immediate value.");
1132
1133 // Adjust stack pointer.
1134 int StackAdj = StackAdjust.getImm();
1135 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1136 int Offset = 0;
1137 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1138
1139 // Incoporate the retaddr area.
1140 Offset = StackAdj-MaxTCDelta;
1141 assert(Offset >= 0 && "Offset should never be negative");
1142
1143 if (Offset) {
1144 // Check for possible merge with preceding ADD instruction.
1145 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1146 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, Uses64BitFramePtr,
1147 UseLEAForSP, TII, *RegInfo);
1148 }
1149
1150 // Jump to label or value in register.
1151 bool IsWin64 = STI.isTargetWin64();
1152 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1153 unsigned Op = (RetOpcode == X86::TCRETURNdi)
1154 ? X86::TAILJMPd
1155 : (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);
1156 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(Op));
1157 if (JumpTarget.isGlobal())
1158 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1159 JumpTarget.getTargetFlags());
1160 else {
1161 assert(JumpTarget.isSymbol());
1162 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1163 JumpTarget.getTargetFlags());
1164 }
1165 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1166 unsigned Op = (RetOpcode == X86::TCRETURNmi)
1167 ? X86::TAILJMPm
1168 : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
1169 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(Op));
1170 for (unsigned i = 0; i != 5; ++i)
1171 MIB.addOperand(MBBI->getOperand(i));
1172 } else if (RetOpcode == X86::TCRETURNri64) {
1173 BuildMI(MBB, MBBI, DL,
1174 TII.get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
1175 .addReg(JumpTarget.getReg(), RegState::Kill);
1176 } else {
1177 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1178 addReg(JumpTarget.getReg(), RegState::Kill);
1179 }
1180
1181 MachineInstr *NewMI = std::prev(MBBI);
1182 NewMI->copyImplicitOps(MF, MBBI);
1183
1184 // Delete the pseudo instruction TCRETURN.
1185 MBB.erase(MBBI);
1186 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1187 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1188 (X86FI->getTCReturnAddrDelta() < 0)) {
1189 // Add the return addr area delta back since we are not tail calling.
1190 int delta = -1*X86FI->getTCReturnAddrDelta();
1191 MBBI = MBB.getLastNonDebugInstr();
1108 // Add the return addr area delta back since we are not tail calling.
1109 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1110 assert(Offset >= 0 && "TCDelta should never be positive");
1111 if (Offset) {
1112 MBBI = MBB.getFirstTerminator();
11921113
11931114 // Check for possible merge with preceding ADD instruction.
1194 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1195 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, Uses64BitFramePtr,
1115 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1116 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, Uses64BitFramePtr,
11961117 UseLEAForSP, TII, *RegInfo);
11971118 }
11981119 }
7878 MachineBasicBlock &MBB,
7979 MachineBasicBlock::iterator MI) const override;
8080
81 /// Check the instruction before/after the passed instruction. If
82 /// it is an ADD/SUB/LEA instruction it is deleted argument and the
83 /// stack adjustment is returned as a positive value for ADD/LEA and
84 /// a negative for SUB.
85 static int mergeSPUpdates(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator &MBBI,
87 unsigned StackPtr, bool doMergeWithPrevious);
88
89 /// Emit a series of instructions to increment / decrement the stack
90 /// pointer by a constant value.
91 static void emitSPUpdate(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
93 int64_t NumBytes, bool Is64BitTarget,
94 bool Is64BitStackPtr, bool UseLEA,
95 const TargetInstrInfo &TII,
96 const TargetRegisterInfo &TRI);
97
98 /// Check that LEA can be use on SP in a prologue sequence for \p MF.
99 bool useLEAForSPInProlog(const MachineFunction &MF) const;
100
81101 private:
82102 /// convertArgMovsToPushes - This method tries to convert a call sequence
83103 /// that uses sub and mov instructions to put the argument onto the stack
491491 unsigned BasePtr;
492492
493493 unsigned Opc = MI.getOpcode();
494 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
494 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
495 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
495496 if (hasBasePointer(MF))
496497 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
497498 else if (needsStackRealignment(MF))
186186 void addPreRegAlloc() override;
187187 void addPostRegAlloc() override;
188188 void addPreEmitPass() override;
189 void addPreSched2() override;
189190 };
190191 } // namespace
191192
234235 addPass(createX86FloatingPointStackifierPass());
235236 }
236237
238 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
239
237240 void X86PassConfig::addPreEmitPass() {
238241 if (getOptLevel() != CodeGenOpt::None)
239242 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));