llvm.org GIT mirror llvm / aafca11
R600/SI: Define a schedule model The machine scheduler is still disabled by default. The schedule model is not complete yet, and could be improved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225913 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
4 changed file(s) with 155 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
8282 // Southern Islands
8383 //===----------------------------------------------------------------------===//
8484
85 def : Proc<"SI", SI_Itin, [FeatureSouthernIslands]>;
85 def : ProcessorModel<"SI", SIFullSpeedModel, [FeatureSouthernIslands]>;
8686
87 def : Proc<"tahiti", SI_Itin, [FeatureSouthernIslands]>;
87 def : ProcessorModel<"tahiti", SIFullSpeedModel, [FeatureSouthernIslands]>;
8888
89 def : Proc<"pitcairn", SI_Itin, [FeatureSouthernIslands]>;
89 def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
9090
91 def : Proc<"verde", SI_Itin, [FeatureSouthernIslands]>;
91 def : ProcessorModel<"verde", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
9292
93 def : Proc<"oland", SI_Itin, [FeatureSouthernIslands]>;
93 def : ProcessorModel<"oland", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
9494
95 def : Proc<"hainan", SI_Itin, [FeatureSouthernIslands]>;
95 def : ProcessorModel<"hainan", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
9696
9797 //===----------------------------------------------------------------------===//
9898 // Sea Islands
9999 //===----------------------------------------------------------------------===//
100100
101 def : Proc<"bonaire", SI_Itin, [FeatureSeaIslands]>;
101 def : ProcessorModel<"bonaire", SIQuarterSpeedModel, [FeatureSeaIslands]>;
102102
103 def : Proc<"kabini", SI_Itin, [FeatureSeaIslands]>;
103 def : ProcessorModel<"kabini", SIQuarterSpeedModel, [FeatureSeaIslands]>;
104104
105 def : Proc<"kaveri", SI_Itin, [FeatureSeaIslands]>;
105 def : ProcessorModel<"kaveri", SIQuarterSpeedModel, [FeatureSeaIslands]>;
106106
107 def : Proc<"hawaii", SI_Itin, [FeatureSeaIslands]>;
107 def : ProcessorModel<"hawaii", SIFullSpeedModel, [FeatureSeaIslands]>;
108108
109 def : Proc<"mullins", SI_Itin, [FeatureSeaIslands]>;
109 def : ProcessorModel<"mullins", SIQuarterSpeedModel, [FeatureSeaIslands]>;
110110
111 def : Proc<"tonga", SI_Itin, [FeatureVolcanicIslands]>;
111 //===----------------------------------------------------------------------===//
112 // Volcanic Islands
113 //===----------------------------------------------------------------------===//
112114
113 def : Proc<"iceland", SI_Itin, [FeatureVolcanicIslands]>;
115 def : ProcessorModel<"tonga", SIFullSpeedModel, [FeatureVolcanicIslands]>;
114116
115 def : Proc<"carrizo", SI_Itin, [FeatureVolcanicIslands]>;
117 def : ProcessorModel<"iceland", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
118
119 def : ProcessorModel<"carrizo", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
6767 // Most instructions require adjustments after selection to satisfy
6868 // operand requirements.
6969 let hasPostISelHook = 1;
70 let SchedRW = [Write32Bit];
7071 }
7172
7273 class Enc32 {
213214 let Inst{31-27} = 0x18; //encoding
214215 }
215216
217 let SchedRW = [WriteSALU] in {
216218 class SOP1 pattern> :
217219 InstSI {
218
219220 let mayLoad = 0;
220221 let mayStore = 0;
221222 let hasSideEffects = 0;
273274 let UseNamedOperandTable = 1;
274275 }
275276
277 } // let SchedRW = [WriteSALU]
278
276279 class SMRD pattern> :
277280 InstSI {
278281
282285 let mayLoad = 1;
283286 let hasSideEffects = 0;
284287 let UseNamedOperandTable = 1;
288 let SchedRW = [WriteSMEM];
285289 }
286290
287291 //===----------------------------------------------------------------------===//
587591 let DS = 1;
588592 let UseNamedOperandTable = 1;
589593 let DisableEncoding = "$m0";
594 let SchedRW = [WriteLDS];
590595 }
591596
592597 class DS_si op, dag outs, dag ins, string asm, list pattern> :
601606
602607 let hasSideEffects = 0;
603608 let UseNamedOperandTable = 1;
609 let SchedRW = [WriteVMEM];
604610 }
605611
606612 class MTBUF pattern> :
612618
613619 let hasSideEffects = 0;
614620 let UseNamedOperandTable = 1;
621 let SchedRW = [WriteVMEM];
615622 }
616623
617624 class FLAT op, dag outs, dag ins, string asm, list pattern> :
640647 }
641648
642649
643
644650 } // End Uses = [EXEC]
11901190
11911191 let Uses = [EXEC] in {
11921192
1193 // FIXME: Specify SchedRW for READFIRSTLANE_B32
1194
11931195 def V_READFIRSTLANE_B32 : VOP1 <
11941196 0x00000002,
11951197 (outs SReg_32:$vdst),
12001202
12011203 }
12021204
1205 let SchedRW = [WriteQuarterRate32] in {
1206
12031207 defm V_CVT_I32_F64 : VOP1Inst , "v_cvt_i32_f64",
12041208 VOP_I32_F64, fp_to_sint
12051209 >;
12521256 defm V_CVT_F64_U32 : VOP1Inst , "v_cvt_f64_u32",
12531257 VOP_F64_I32, uint_to_fp
12541258 >;
1259
1260 } // let SchedRW = [WriteQuarterRate32]
1261
12551262 defm V_FRACT_F32 : VOP1Inst , "v_fract_f32",
12561263 VOP_F32_F32, AMDGPUfract
12571264 >;
12701277 defm V_EXP_F32 : VOP1Inst , "v_exp_f32",
12711278 VOP_F32_F32, fexp2
12721279 >;
1280
1281 let SchedRW = [WriteQuarterRate32] in {
1282
12731283 defm V_LOG_F32 : VOP1Inst , "v_log_f32",
12741284 VOP_F32_F32, flog2
12751285 >;
12821292 defm V_RSQ_F32 : VOP1Inst , "v_rsq_f32",
12831293 VOP_F32_F32, AMDGPUrsq
12841294 >;
1295
1296 } //let SchedRW = [WriteQuarterRate32]
1297
1298 let SchedRW = [WriteDouble] in {
1299
12851300 defm V_RCP_F64 : VOP1Inst , "v_rcp_f64",
12861301 VOP_F64_F64, AMDGPUrcp
12871302 >;
12881303 defm V_RSQ_F64 : VOP1Inst , "v_rsq_f64",
12891304 VOP_F64_F64, AMDGPUrsq
12901305 >;
1306
1307 } // let SchedRW = [WriteDouble];
1308
12911309 defm V_SQRT_F32 : VOP1Inst , "v_sqrt_f32",
12921310 VOP_F32_F32, fsqrt
12931311 >;
1312
1313 let SchedRW = [WriteDouble] in {
1314
12941315 defm V_SQRT_F64 : VOP1Inst , "v_sqrt_f64",
12951316 VOP_F64_F64, fsqrt
12961317 >;
1318
1319 } // let SchedRW = [WriteDouble]
1320
12971321 defm V_SIN_F32 : VOP1Inst , "v_sin_f32",
12981322 VOP_F32_F32, AMDGPUsin
12991323 >;
13221346 // These instruction only exist on SI and CI
13231347 let SubtargetPredicate = isSICI in {
13241348
1349 let SchedRW = [WriteQuarterRate32] in {
1350
13251351 defm V_LOG_CLAMP_F32 : VOP1InstSI , "v_log_clamp_f32", VOP_F32_F32>;
13261352 defm V_RCP_CLAMP_F32 : VOP1InstSI , "v_rcp_clamp_f32", VOP_F32_F32>;
13271353 defm V_RCP_LEGACY_F32 : VOP1InstSI , "v_rcp_legacy_f32", VOP_F32_F32>;
13311357 defm V_RSQ_LEGACY_F32 : VOP1InstSI , "v_rsq_legacy_f32",
13321358 VOP_F32_F32, AMDGPUrsq_legacy
13331359 >;
1360
1361 } // End let SchedRW = [WriteQuarterRate32]
1362
1363 let SchedRW = [WriteDouble] in {
1364
13341365 defm V_RCP_CLAMP_F64 : VOP1InstSI , "v_rcp_clamp_f64", VOP_F64_F64>;
13351366 defm V_RSQ_CLAMP_F64 : VOP1InstSI , "v_rsq_clamp_f64",
13361367 VOP_F64_F64, AMDGPUrsq_clamped
13371368 >;
13381369
1370 } // End SchedRW = [WriteDouble]
1371
13391372 } // End SubtargetPredicate = isSICI
13401373
13411374 //===----------------------------------------------------------------------===//
13421375 // VINTRP Instructions
13431376 //===----------------------------------------------------------------------===//
13441377
1378 // FIXME: Specify SchedRW for VINTRP insturctions.
13451379 defm V_INTERP_P1_F32 : VINTRP_m <
13461380 0x00000000, "v_interp_p1_f32",
13471381 (outs VGPR_32:$dst),
16551689 defm V_DIV_FIXUP_F32 : VOP3Inst <
16561690 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
16571691 >;
1692
1693 let SchedRW = [WriteDouble] in {
1694
16581695 defm V_DIV_FIXUP_F64 : VOP3Inst <
16591696 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
16601697 >;
16611698
1662 // Only on SI
1699 } // let SchedRW = [WriteDouble]
1700
16631701 defm V_LSHL_B64 : VOP3Inst , "v_lshl_b64",
16641702 VOP_I64_I64_I32, shl
16651703 >;
16741712 VOP_I64_I64_I32, sra
16751713 >;
16761714
1715 let SchedRW = [WriteDouble] in {
16771716 let isCommutable = 1 in {
16781717
16791718 defm V_ADD_F64 : VOP3Inst , "v_add_f64",
16961735 VOP_F64_F64_I32, AMDGPUldexp
16971736 >;
16981737
1699 let isCommutable = 1 in {
1738 } // let SchedRW = [WriteDouble]
1739
1740 let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
17001741
17011742 defm V_MUL_LO_U32 : VOP3Inst , "v_mul_lo_u32",
17021743 VOP_I32_I32_I32
17121753 VOP_I32_I32_I32
17131754 >;
17141755
1715 } // isCommutable = 1
1756 } // isCommutable = 1, SchedRW = [WriteQuarterRate32]
17161757
17171758 defm V_DIV_SCALE_F32 : VOP3b_32 , "v_div_scale_f32", []>;
17181759
1760 let SchedRW = [WriteDouble] in {
17191761 // Double precision division pre-scale.
17201762 defm V_DIV_SCALE_F64 : VOP3b_64 , "v_div_scale_f64", []>;
1763 } // let SchedRW = [WriteDouble]
17211764
17221765 let isCommutable = 1 in {
17231766 defm V_DIV_FMAS_F32 : VOP3Inst , "v_div_fmas_f32",
17241767 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
17251768 >;
1769 let SchedRW = [WriteDouble] in {
17261770 defm V_DIV_FMAS_F64 : VOP3Inst , "v_div_fmas_f64",
17271771 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
17281772 >;
1773 } // End SchedRW = [WriteDouble]
17291774 } // End isCommutable = 1
17301775
17311776 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>;
17321777 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>;
17331778 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
17341779
1780 let SchedRW = [WriteDouble] in {
17351781 defm V_TRIG_PREOP_F64 : VOP3Inst <
17361782 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
17371783 >;
1784
1785 } // let SchedRW = [WriteDouble]
17381786
17391787 //===----------------------------------------------------------------------===//
17401788 // Pseudo Instructions
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // TODO: This is just a place holder for now.
9 // MachineModel definitions for Southern Islands (SI)
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 def WriteBranch : SchedWrite;
14 def WriteExport : SchedWrite;
15 def WriteLDS : SchedWrite;
16 def WriteSALU : SchedWrite;
17 def WriteSMEM : SchedWrite;
18 def WriteVMEM : SchedWrite;
1319
14 def SI_Itin : ProcessorItineraries <[], [], []>;
20 // Vector ALU instructions
21 def Write32Bit : SchedWrite;
22 def WriteQuarterRate32 : SchedWrite;
23
24 def WriteFloatFMA : SchedWrite;
25
26 def WriteDouble : SchedWrite;
27 def WriteDoubleAdd : SchedWrite;
28
29 def SIFullSpeedModel : SchedMachineModel;
30 def SIQuarterSpeedModel : SchedMachineModel;
31
32 // BufferSize = 0 means the processors are in-order.
33 let BufferSize = 0 in {
34
35 // XXX: Are the resource counts correct?
36 def HWBranch : ProcResource<1>;
37 def HWExport : ProcResource<7>; // Taken from S_WAITCNT
38 def HWLGKM : ProcResource<31>; // Taken from S_WAITCNT
39 def HWSALU : ProcResource<1>;
40 def HWVMEM : ProcResource<15>; // Taken from S_WAITCNT
41 def HWVALU : ProcResource<1>;
42
43 }
44
45 class HWWriteRes resources,
46 int latency> : WriteRes {
47 let Latency = latency;
48 }
49
50 class HWVALUWriteRes :
51 HWWriteRes;
52
53
54 // The latency numbers are taken from AMD Accelerated Parallel Processing
55 // guide. They may not be acurate.
56
57 // The latency values are 1 / (operations / cycle) / 4.
58 multiclass SICommonWriteRes {
59
60 def : HWWriteRes; // XXX: Guessed ???
61 def : HWWriteRes; // XXX: Guessed ???
62 def : HWWriteRes; // 2 - 64
63 def : HWWriteRes;
64 def : HWWriteRes; // XXX: Guessed ???
65 def : HWWriteRes; // 300 - 600
66
67 def : HWVALUWriteRes;
68 def : HWVALUWriteRes;
69 }
70
71
72 let SchedModel = SIFullSpeedModel in {
73
74 defm : SICommonWriteRes;
75
76 def : HWVALUWriteRes;
77 def : HWVALUWriteRes;
78 def : HWVALUWriteRes;
79
80 } // End SchedModel = SIFullSpeedModel
81
82 let SchedModel = SIQuarterSpeedModel in {
83
84 defm : SICommonWriteRes;
85
86 def : HWVALUWriteRes;
87 def : HWVALUWriteRes;
88 def : HWVALUWriteRes;
89
90 } // End SchedModel = SIQuarterSpeedModel