llvm.org GIT mirror llvm / aaf6ddf
Merging r340932: ------------------------------------------------------------------------ r340932 | atanasyan | 2018-08-29 07:54:01 -0700 (Wed, 29 Aug 2018) | 11 lines [mips] Fix microMIPS unconditional branch offset handling MipsSEInstrInfo class defines for internal purpose unconditional branches as Mips::B nad Mips:J even in case of microMIPS code generation. Under some conditions that leads to the bug - for rather long branch which fits to Mips jump instruction offset size, but does not fit to microMIPS jump offset size, we generate 'short' branch and later show an error 'out of range PC16 fixup' after check in the isBranchOffsetInRange routine. Differential revision: https://reviews.llvm.org/D50615 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@346736 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 11 months ago
2 changed file(s) with 105 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
2424
2525 using namespace llvm;
2626
27 static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
28 if (STI.inMicroMipsMode())
29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
30 return STI.isPositionIndependent() ? Mips::B : Mips::J;
31 }
32
2733 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
28 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J),
29 RI() {}
34 : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
3035
3136 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
3237 return RI;
0 ; RUN: llc -march=mips -relocation-model=pic -mattr=+micromips \
1 ; RUN: -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
2
3 ; CHECK-LABEL: foo:
4 ; CHECK-NEXT: 0: 41 a2 00 00 lui $2, 0
5 ; CHECK-NEXT: 4: 30 42 00 00 addiu $2, $2, 0
6 ; CHECK-NEXT: 8: 03 22 11 50 addu $2, $2, $25
7 ; CHECK-NEXT: c: fc 42 00 00 lw $2, 0($2)
8 ; CHECK-NEXT: 10: 69 20 lw16 $2, 0($2)
9 ; CHECK-NEXT: 12: 40 c2 00 14 bgtz $2, 44
10 ; CHECK-NEXT: 16: 00 00 00 00 nop
11 ; CHECK-NEXT: 1a: 33 bd ff f8 addiu $sp, $sp, -8
12 ; CHECK-NEXT: 1e: fb fd 00 00 sw $ra, 0($sp)
13 ; CHECK-NEXT: 22: 41 a1 00 01 lui $1, 1
14 ; CHECK-NEXT: 26: 40 60 00 02 bal 8
15 ; CHECK-NEXT: 2a: 30 21 04 68 addiu $1, $1, 1128
16 ; CHECK-NEXT: 2e: 00 3f 09 50 addu $1, $ra, $1
17 ; CHECK-NEXT: 32: ff fd 00 00 lw $ra, 0($sp)
18 ; CHECK-NEXT: 36: 00 01 0f 3c jr $1
19 ; CHECK-NEXT: 3a: 33 bd 00 08 addiu $sp, $sp, 8
20 ; CHECK-NEXT: 3e: 94 00 00 02 b 8
21 ; CHECK-NEXT: 42: 00 00 00 00 nop
22 ; CHECK-NEXT: 46: 30 20 4e 1f addiu $1, $zero, 19999
23 ; CHECK-NEXT: 4a: b4 22 00 14 bne $2, $1, 44
24 ; CHECK-NEXT: 4e: 00 00 00 00 nop
25 ; CHECK-NEXT: 52: 33 bd ff f8 addiu $sp, $sp, -8
26 ; CHECK-NEXT: 56: fb fd 00 00 sw $ra, 0($sp)
27 ; CHECK-NEXT: 5a: 41 a1 00 01 lui $1, 1
28 ; CHECK-NEXT: 5e: 40 60 00 02 bal 8
29 ; CHECK-NEXT: 62: 30 21 04 5c addiu $1, $1, 1116
30 ; CHECK-NEXT: 66: 00 3f 09 50 addu $1, $ra, $1
31 ; CHECK-NEXT: 6a: ff fd 00 00 lw $ra, 0($sp)
32 ; CHECK-NEXT: 6e: 00 01 0f 3c jr $1
33 ; CHECK-NEXT: 72: 33 bd 00 08 addiu $sp, $sp, 8
34 ; CHECK-NEXT: 76: 30 20 27 0f addiu $1, $zero, 9999
35 ; CHECK-NEXT: 7a: 94 22 00 14 beq $2, $1, 44
36 ; CHECK-NEXT: 7e: 00 00 00 00 nop
37 ; CHECK-NEXT: 82: 33 bd ff f8 addiu $sp, $sp, -8
38 ; CHECK-NEXT: 86: fb fd 00 00 sw $ra, 0($sp)
39 ; CHECK-NEXT: 8a: 41 a1 00 01 lui $1, 1
40 ; CHECK-NEXT: 8e: 40 60 00 02 bal 8
41 ; CHECK-NEXT: 92: 30 21 04 2c addiu $1, $1, 1068
42 ; CHECK-NEXT: 96: 00 3f 09 50 addu $1, $ra, $1
43 ; CHECK-NEXT: 9a: ff fd 00 00 lw $ra, 0($sp)
44 ; CHECK-NEXT: 9e: 00 01 0f 3c jr $1
45 ; CHECK-NEXT: a2: 33 bd 00 08 addiu $sp, $sp, 8
46
47 ; CHECK: 10466: 00 00 00 00 nop
48 ; CHECK-NEXT: 1046a: 94 00 00 02 b 8
49 ; CHECK-NEXT: 1046e: 00 00 00 00 nop
50 ; CHECK-NEXT: 10472: 33 bd ff f8 addiu $sp, $sp, -8
51 ; CHECK-NEXT: 10476: fb fd 00 00 sw $ra, 0($sp)
52 ; CHECK-NEXT: 1047a: 41 a1 00 01 lui $1, 1
53 ; CHECK-NEXT: 1047e: 40 60 00 02 bal 8
54 ; CHECK-NEXT: 10482: 30 21 04 00 addiu $1, $1, 1024
55 ; CHECK-NEXT: 10486: 00 3f 09 50 addu $1, $ra, $1
56 ; CHECK-NEXT: 1048a: ff fd 00 00 lw $ra, 0($sp)
57 ; CHECK-NEXT: 1048e: 00 01 0f 3c jr $1
58 ; CHECK-NEXT: 10492: 33 bd 00 08 addiu $sp, $sp, 8
59 ; CHECK-NEXT: 10496: 94 00 00 02 b 8
60
61 @x = external global i32, align 4
62
63 define void @foo() {
64 %1 = load i32, i32* @x, align 4
65 %2 = icmp sgt i32 %1, 0
66 br i1 %2, label %la, label %lf
67
68 la:
69 switch i32 %1, label %le [
70 i32 9999, label %lb
71 i32 19999, label %lc
72 ]
73
74 lb:
75 tail call void asm sideeffect ".space 0", ""()
76 br label %le
77
78 lc:
79 tail call void asm sideeffect ".space 0", ""()
80 br label %le
81
82 le:
83 tail call void asm sideeffect ".space 66500", ""()
84 br label %lg
85
86 lf:
87 tail call void asm sideeffect ".space 0", ""()
88 br label %lg
89
90 lg:
91 tail call void asm sideeffect ".space 0", ""()
92 br label %li
93
94 li:
95 tail call void asm sideeffect ".space 0", ""()
96 ret void
97 }