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[Stackmap] Liveness Analysis Pass This optional register liveness analysis pass can be enabled with either -enable-stackmap-liveness, -enable-patchpoint-liveness, or both. The pass traverses each basic block in a machine function. For each basic block the instructions are processed in reversed order and if a patchpoint or stackmap instruction is encountered the current live-out register set is encoded as a register mask and attached to the instruction. Later on during stackmap generation the live-out register mask is processed and also emitted as part of the stackmap. This information is optional and intended for optimization purposes only. This will enable a client of the stackmap to reason about the registers it can use and which registers need to be preserved. Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197317 91177308-0d34-0410-b5e6-96231b3b80d8 Juergen Ributzka 6 years ago
16 changed file(s) with 614 addition(s) and 52 deletion(s). Raw diff Collapse all Expand all
144144 /// to builtin \@llvm.returnaddress.
145145 bool ReturnAddressTaken;
146146
147 /// HasStackMap - This boolean keeps track of whether there is a call
148 /// to builtin \@llvm.experimental.stackmap.
149 bool HasStackMap;
150
151 /// HasPatchPoint - This boolean keeps track of whether there is a call
152 /// to builtin \@llvm.experimental.patchpoint.
153 bool HasPatchPoint;
154
147155 /// StackSize - The prolog/epilog code inserter calculates the final stack
148156 /// offsets for all of the fixed size objects, updating the Objects list
149157 /// above. It then updates StackSize to contain the number of bytes that need
234242 HasVarSizedObjects = false;
235243 FrameAddressTaken = false;
236244 ReturnAddressTaken = false;
245 HasStackMap = false;
246 HasPatchPoint = false;
237247 AdjustsStack = false;
238248 HasCalls = false;
239249 StackProtectorIdx = -1;
279289 bool isReturnAddressTaken() const { return ReturnAddressTaken; }
280290 void setReturnAddressIsTaken(bool s) { ReturnAddressTaken = s; }
281291
292 /// hasStackMap - This method may be called any time after instruction
293 /// selection is complete to determine if there is a call to builtin
294 /// \@llvm.experimental.stackmap.
295 bool hasStackMap() const { return HasStackMap; }
296 void setHasStackMap(bool s = true) { HasStackMap = s; }
297
298 /// hasPatchPoint - This method may be called any time after instruction
299 /// selection is complete to determine if there is a call to builtin
300 /// \@llvm.experimental.patchpoint.
301 bool hasPatchPoint() const { return HasPatchPoint; }
302 void setHasPatchPoint(bool s = true) { HasPatchPoint = s; }
303
282304 /// getObjectIndexBegin - Return the minimum frame object index.
283305 ///
284306 int getObjectIndexBegin() const { return -NumFixedObjects; }
425425 OperandRecycler.deallocate(Cap, Array);
426426 }
427427
428 /// \brief Allocate and initialize a register mask with @p NumRegister bits.
429 uint32_t *allocateRegisterMask(unsigned NumRegister) {
430 unsigned Size = (NumRegister + 31) / 32;
431 uint32_t *Mask = Allocator.Allocate(Size);
432 for (unsigned i = 0; i != Size; ++i)
433 Mask[i] = 0;
434 return Mask;
435 }
436
428437 /// allocateMemRefsArray - Allocate an array to hold MachineMemOperand
429438 /// pointers. This array is owned by the MachineFunction.
430439 MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num);
5555 MO_GlobalAddress, ///< Address of a global value
5656 MO_BlockAddress, ///< Address of a basic block
5757 MO_RegisterMask, ///< Mask of preserved registers.
58 MO_RegisterLiveOut, ///< Mask of live-out registers.
5859 MO_Metadata, ///< Metadata reference (for debug info)
5960 MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
6061 };
152153 const ConstantFP *CFP; // For MO_FPImmediate.
153154 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
154155 int64_t ImmVal; // For MO_Immediate.
155 const uint32_t *RegMask; // For MO_RegisterMask.
156 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
156157 const MDNode *MD; // For MO_Metadata.
157158 MCSymbol *Sym; // For MO_MCSymbol
158159
245246 bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
246247 /// isRegMask - Tests if this is a MO_RegisterMask operand.
247248 bool isRegMask() const { return OpKind == MO_RegisterMask; }
249 /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
250 bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
248251 /// isMetadata - Tests if this is a MO_Metadata operand.
249252 bool isMetadata() const { return OpKind == MO_Metadata; }
250253 bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
472475 /// operand.
473476 const uint32_t *getRegMask() const {
474477 assert(isRegMask() && "Wrong MachineOperand accessor");
478 return Contents.RegMask;
479 }
480
481 /// getRegLiveOut - Returns a bit mask of live-out registers.
482 const uint32_t *getRegLiveOut() const {
483 assert(isRegLiveOut() && "Wrong MachineOperand accessor");
475484 return Contents.RegMask;
476485 }
477486
658667 Op.Contents.RegMask = Mask;
659668 return Op;
660669 }
670 static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
671 assert(Mask && "Missing live-out register mask");
672 MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
673 Op.Contents.RegMask = Mask;
674 return Op;
675 }
661676 static MachineOperand CreateMetadata(const MDNode *Meta) {
662677 MachineOperand Op(MachineOperand::MO_Metadata);
663678 Op.Contents.MD = Meta;
567567 /// bundles (created earlier, e.g. during pre-RA scheduling).
568568 extern char &FinalizeMachineBundlesID;
569569
570 /// StackMapLiveness - This pass analyses the register live-out set of
571 /// stackmap/patchpoint intrinsics and attaches the calculated information to
572 /// the intrinsic for later emission to the StackMap.
573 extern char &StackMapLivenessID;
574
570575 } // End llvm namespace
571576
572577 #endif
0 //===--- StackMapLivenessAnalysis - StackMap Liveness Analysis --*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass calculates the liveness for each basic block in a function and
10 // attaches the register live-out information to a stackmap or patchpoint
11 // intrinsic if present.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef LLVM_CODEGEN_STACKMAP_LIVENESS_ANALYSIS_H
16 #define LLVM_CODEGEN_STACKMAP_LIVENESS_ANALYSIS_H
17
18 #include "llvm/CodeGen/LivePhysRegs.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20
21
22 namespace llvm {
23
24 /// \brief This pass calculates the liveness information for each basic block in
25 /// a function and attaches the register live-out information to a stackmap or
26 /// patchpoint intrinsic if present.
27 ///
28 /// This is an optional pass that has to be explicitly enabled via the
29 /// -enable-stackmap-liveness and/or -enable-patchpoint-liveness flag. The pass
30 /// skips functions that don't have any stackmap or patchpoint intrinsics. The
31 /// information provided by this pass is optional and not required by the
32 /// aformentioned intrinsics to function.
33 class StackMapLiveness : public MachineFunctionPass {
34 MachineFunction *MF;
35 const TargetRegisterInfo *TRI;
36 LivePhysRegs LiveRegs;
37 public:
38 static char ID;
39
40 /// \brief Default construct and initialize the pass.
41 StackMapLiveness();
42
43 /// \brief Tell the pass manager which passes we depend on and what
44 /// information we preserve.
45 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
46
47 /// \brief Calculate the liveness information for the given machine function.
48 virtual bool runOnMachineFunction(MachineFunction &MF);
49
50 private:
51 /// \brief Performs the actual liveness calculation for the function.
52 bool calculateLiveness();
53
54 /// \brief Add the current register live set to the instruction.
55 void addLiveOutSetToMI(MachineInstr &MI);
56
57 /// \brief Create a register mask and initialize it with the registers from
58 /// the register live set.
59 uint32_t *createRegisterMask() const;
60 };
61
62 } // llvm namespace
63
64 #endif // LLVM_CODEGEN_STACKMAP_LIVENESS_ANALYSIS_H
9292 : LocType(LocType), Size(Size), Reg(Reg), Offset(Offset) {}
9393 };
9494
95 struct LiveOutReg {
96 unsigned short Reg;
97 unsigned short RegNo;
98 unsigned short Size;
99
100 LiveOutReg() : Reg(0), RegNo(0), Size(0) {}
101 LiveOutReg(unsigned short Reg, unsigned short RegNo, unsigned short Size)
102 : Reg(Reg), RegNo(RegNo), Size(Size) {}
103
104 void MarkInvalid() { Reg = 0; }
105
106 // Only sort by the dwarf register number.
107 bool operator< (const LiveOutReg &LO) const { return RegNo < LO.RegNo; }
108 static bool IsInvalid(const LiveOutReg &LO) { return LO.Reg == 0; }
109 };
110
95111 // OpTypes are used to encode information about the following logical
96112 // operand (which may consist of several MachineOperands) for the
97113 // OpParser.
114130
115131 private:
116132 typedef SmallVector LocationVec;
133 typedef SmallVector LiveOutVec;
117134
118135 struct CallsiteInfo {
119136 const MCExpr *CSOffsetExpr;
120137 uint64_t ID;
121138 LocationVec Locations;
139 LiveOutVec LiveOuts;
122140 CallsiteInfo() : CSOffsetExpr(0), ID(0) {}
123141 CallsiteInfo(const MCExpr *CSOffsetExpr, uint64_t ID,
124 LocationVec Locations)
125 : CSOffsetExpr(CSOffsetExpr), ID(ID), Locations(Locations) {}
142 LocationVec &Locations, LiveOutVec &LiveOuts)
143 : CSOffsetExpr(CSOffsetExpr), ID(ID), Locations(Locations),
144 LiveOuts(LiveOuts) {}
126145 };
127146
128147 typedef std::vector CallsiteInfoList;
153172
154173 std::pair
155174 parseOperand(MachineInstr::const_mop_iterator MOI,
156 MachineInstr::const_mop_iterator MOE);
175 MachineInstr::const_mop_iterator MOE) const;
157176
177 /// \brief Create a live-out register record for the given register @p Reg.
178 LiveOutReg createLiveOutReg(unsigned Reg, const MCRegisterInfo &MCRI,
179 const TargetRegisterInfo *TRI) const;
180
181 /// \brief Parse the register live-out mask and return a vector of live-out
182 /// registers that need to be recorded in the stackmap.
183 LiveOutVec parseRegisterLiveOutMask(const uint32_t *Mask) const;
158184
159185 /// This should be called by the MC lowering code _immediately_ before
160186 /// lowering the MI to an MCInst. It records where the operands for the
265265 void initializeSLPVectorizerPass(PassRegistry&);
266266 void initializeBBVectorizePass(PassRegistry&);
267267 void initializeMachineFunctionPrinterPassPass(PassRegistry&);
268 void initializeStackMapLivenessPass(PassRegistry&);
268269 }
269270
270271 #endif
9696 StackColoring.cpp
9797 StackProtector.cpp
9898 StackSlotColoring.cpp
99 StackMapLivenessAnalysis.cpp
99100 StackMaps.cpp
100101 TailDuplication.cpp
101102 TargetFrameLoweringImpl.cpp
6868 initializeVirtRegRewriterPass(Registry);
6969 initializeLowerIntrinsicsPass(Registry);
7070 initializeMachineFunctionPrinterPassPass(Registry);
71 initializeStackMapLivenessPass(Registry);
7172 }
7273
7374 void LLVMInitializeCodeGen(LLVMPassRegistryRef R) {
198198 case MachineOperand::MO_BlockAddress:
199199 return getBlockAddress() == Other.getBlockAddress() &&
200200 getOffset() == Other.getOffset();
201 case MO_RegisterMask:
201 case MachineOperand::MO_RegisterMask:
202 case MachineOperand::MO_RegisterLiveOut:
202203 return getRegMask() == Other.getRegMask();
203204 case MachineOperand::MO_MCSymbol:
204205 return getMCSymbol() == Other.getMCSymbol();
240241 return hash_combine(MO.getType(), MO.getTargetFlags(),
241242 MO.getBlockAddress(), MO.getOffset());
242243 case MachineOperand::MO_RegisterMask:
244 case MachineOperand::MO_RegisterLiveOut:
243245 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
244246 case MachineOperand::MO_Metadata:
245247 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
367369 case MachineOperand::MO_RegisterMask:
368370 OS << "";
369371 break;
372 case MachineOperand::MO_RegisterLiveOut:
373 OS << "";
374 break;
370375 case MachineOperand::MO_Metadata:
371376 OS << '<';
372377 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
2828 #include "llvm/Transforms/Scalar.h"
2929
3030 using namespace llvm;
31
32 namespace llvm {
33 extern cl::opt EnableStackMapLiveness;
34 extern cl::opt EnablePatchPointLiveness;
35 }
3136
3237 static cl::opt DisablePostRA("disable-post-ra", cl::Hidden,
3338 cl::desc("Disable Post Regalloc"));
535540
536541 if (addPreEmitPass())
537542 printAndVerify("After PreEmit passes");
543
544 if (EnableStackMapLiveness || EnablePatchPointLiveness)
545 addPass(&StackMapLivenessID);
538546 }
539547
540548 /// Add passes that optimize machine instructions in SSA form.
68856885 DAG.ReplaceAllUsesWith(Call, MN);
68866886
68876887 DAG.DeleteNode(Call);
6888
6889 // Inform the Frame Information that we have a stackmap in this function.
6890 FuncInfo.MF->getFrameInfo()->setHasStackMap();
68886891 }
68896892
68906893 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
70247027 } else
70257028 DAG.ReplaceAllUsesWith(Call, MN);
70267029 DAG.DeleteNode(Call);
7030
7031 // Inform the Frame Information that we have a patchpoint in this function.
7032 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
70277033 }
70287034
70297035 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
0 //===-- StackMapLivenessAnalysis.cpp - StackMap live Out Analysis ----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the StackMap Liveness analysis pass. The pass calculates
10 // the liveness for each basic block in a function and attaches the register
11 // live-out information to a stackmap or patchpoint intrinsic if present.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "stackmaps"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/CodeGen/StackMapLivenessAnalysis.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Debug.h"
24
25
26 using namespace llvm;
27
28 namespace llvm {
29 cl::opt EnableStackMapLiveness("enable-stackmap-liveness",
30 cl::Hidden, cl::desc("Enable StackMap Liveness Analysis Pass"));
31 cl::opt EnablePatchPointLiveness("enable-patchpoint-liveness",
32 cl::Hidden, cl::desc("Enable PatchPoint Liveness Analysis Pass"));
33 }
34
35 STATISTIC(NumStackMapFuncVisited, "Number of functions visited");
36 STATISTIC(NumStackMapFuncSkipped, "Number of functions skipped");
37 STATISTIC(NumBBsVisited, "Number of basic blocks visited");
38 STATISTIC(NumBBsHaveNoStackmap, "Number of basic blocks with no stackmap");
39 STATISTIC(NumStackMaps, "Number of StackMaps visited");
40
41 char StackMapLiveness::ID = 0;
42 char &llvm::StackMapLivenessID = StackMapLiveness::ID;
43 INITIALIZE_PASS(StackMapLiveness, "stackmap-liveness",
44 "StackMap Liveness Analysis", false, false)
45
46 /// Default construct and initialize the pass.
47 StackMapLiveness::StackMapLiveness() : MachineFunctionPass(ID) {
48 initializeStackMapLivenessPass(*PassRegistry::getPassRegistry());
49 }
50
51 /// Tell the pass manager which passes we depend on and what information we
52 /// preserve.
53 void StackMapLiveness::getAnalysisUsage(AnalysisUsage &AU) const {
54 // We preserve all information.
55 AU.setPreservesAll();
56 AU.setPreservesCFG();
57 // Default dependencie for all MachineFunction passes.
58 AU.addRequired();
59 }
60
61 /// Calculate the liveness information for the given machine function.
62 bool StackMapLiveness::runOnMachineFunction(MachineFunction &_MF) {
63 DEBUG(dbgs() << "********** COMPUTING STACKMAP LIVENESS: "
64 << _MF.getName() << " **********\n");
65 MF = &_MF;
66 TRI = MF->getTarget().getRegisterInfo();
67 ++NumStackMapFuncVisited;
68
69 // Skip this function if there are no stackmaps or patchpoints to process.
70 if (!((MF->getFrameInfo()->hasStackMap() && EnableStackMapLiveness) ||
71 (MF->getFrameInfo()->hasPatchPoint() && EnablePatchPointLiveness))) {
72 ++NumStackMapFuncSkipped;
73 return false;
74 }
75 return calculateLiveness();
76 }
77
78 /// Performs the actual liveness calculation for the function.
79 bool StackMapLiveness::calculateLiveness() {
80 bool HasChanged = false;
81 // For all basic blocks in the function.
82 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
83 MBBI != MBBE; ++MBBI) {
84 DEBUG(dbgs() << "****** BB " << MBBI->getName() << " ******\n");
85 LiveRegs.init(TRI);
86 LiveRegs.addLiveOuts(MBBI);
87 bool HasStackMap = false;
88 // Reverse iterate over all instructions and add the current live register
89 // set to an instruction if we encounter a stackmap or patchpoint
90 // instruction.
91 for (MachineBasicBlock::reverse_iterator I = MBBI->rbegin(),
92 E = MBBI->rend(); I != E; ++I) {
93 int Opc = I->getOpcode();
94 if ((EnableStackMapLiveness && (Opc == TargetOpcode::STACKMAP)) ||
95 (EnablePatchPointLiveness && (Opc == TargetOpcode::PATCHPOINT))) {
96 addLiveOutSetToMI(*I);
97 HasChanged = true;
98 HasStackMap = true;
99 ++NumStackMaps;
100 }
101 DEBUG(dbgs() << " " << *I << " " << LiveRegs);
102 LiveRegs.stepBackward(*I);
103 }
104 ++NumBBsVisited;
105 if (!HasStackMap)
106 ++NumBBsHaveNoStackmap;
107 }
108 return HasChanged;
109 }
110
111 /// Add the current register live set to the instruction.
112 void StackMapLiveness::addLiveOutSetToMI(MachineInstr &MI) {
113 uint32_t *Mask = createRegisterMask();
114 MachineOperand MO = MachineOperand::CreateRegLiveOut(Mask);
115 MI.addOperand(*MF, MO);
116 }
117
118 /// Create a register mask and initialize it with the registers from the
119 /// register live set.
120 uint32_t *StackMapLiveness::createRegisterMask() const {
121 // The mask is owned and cleaned up by the Machine Function.
122 uint32_t *Mask = MF->allocateRegisterMask(TRI->getNumRegs());
123 for (LivePhysRegs::const_iterator RI = LiveRegs.begin(), RE = LiveRegs.end();
124 RI != RE; ++RI)
125 Mask[*RI / 32] |= 1U << (*RI % 32);
126 return Mask;
127 }
6767
6868 std::pair
6969 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
70 MachineInstr::const_mop_iterator MOE) {
70 MachineInstr::const_mop_iterator MOE) const {
7171 const MachineOperand &MOP = *MOI;
72 assert(!MOP.isRegMask() && (!MOP.isReg() || !MOP.isImplicit()) &&
73 "Register mask and implicit operands should not be processed.");
72 assert((!MOP.isReg() || !MOP.isImplicit()) &&
73 "Implicit operands should not be processed.");
7474
7575 if (MOP.isImm()) {
7676 // Verify anyregcc
104104 }
105105 }
106106 }
107
108 if (MOP.isRegMask() || MOP.isRegLiveOut())
109 return std::make_pair(Location(), ++MOI);
107110
108111 // Otherwise this is a reg operand. The physical register number will
109112 // ultimately be encoded as a DWARF regno. The stack map also records the size
119122 Location(Location::Register, RC->getSize(), MOP.getReg(), 0), ++MOI);
120123 }
121124
125 /// Go up the super-register chain until we hit a valid dwarf register number.
126 static unsigned short getDwarfRegNum(unsigned Reg, const MCRegisterInfo &MCRI,
127 const TargetRegisterInfo *TRI) {
128 int RegNo = MCRI.getDwarfRegNum(Reg, false);
129 for (MCSuperRegIterator SR(Reg, TRI);
130 SR.isValid() && RegNo < 0; ++SR)
131 RegNo = TRI->getDwarfRegNum(*SR, false);
132
133 assert(RegNo >= 0 && "Invalid Dwarf register number.");
134 return (unsigned short) RegNo;
135 }
136
137 /// Create a live-out register record for the given register Reg.
138 StackMaps::LiveOutReg
139 StackMaps::createLiveOutReg(unsigned Reg, const MCRegisterInfo &MCRI,
140 const TargetRegisterInfo *TRI) const {
141 unsigned RegNo = getDwarfRegNum(Reg, MCRI, TRI);
142 unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
143 return LiveOutReg(Reg, RegNo, Size);
144 }
145
146 /// Parse the register live-out mask and return a vector of live-out registers
147 /// that need to be recorded in the stackmap.
148 StackMaps::LiveOutVec
149 StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
150 assert(Mask && "No register mask specified");
151 const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
152 MCContext &OutContext = AP.OutStreamer.getContext();
153 const MCRegisterInfo &MCRI = *OutContext.getRegisterInfo();
154 LiveOutVec LiveOuts;
155
156 // Create a LiveOutReg for each bit that is set in the register mask.
157 for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
158 if ((Mask[Reg / 32] >> Reg % 32) & 1)
159 LiveOuts.push_back(createLiveOutReg(Reg, MCRI, TRI));
160
161 // We don't need to keep track of a register if its super-register is already
162 // in the list. Merge entries that refer to the same dwarf register and use
163 // the maximum size that needs to be spilled.
164 std::sort(LiveOuts.begin(), LiveOuts.end());
165 for (LiveOutVec::iterator I = LiveOuts.begin(), E = LiveOuts.end();
166 I != E; ++I) {
167 for (LiveOutVec::iterator II = next(I); II != E; ++II) {
168 if (I->RegNo != II->RegNo) {
169 // Skip all the now invalid entries.
170 I = --II;
171 break;
172 }
173 I->Size = std::max(I->Size, II->Size);
174 if (TRI->isSuperRegister(I->Reg, II->Reg))
175 I->Reg = II->Reg;
176 II->MarkInvalid();
177 }
178 }
179 LiveOuts.erase(std::remove_if(LiveOuts.begin(), LiveOuts.end(),
180 LiveOutReg::IsInvalid), LiveOuts.end());
181 return LiveOuts;
182 }
183
122184 void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
123185 MachineInstr::const_mop_iterator MOI,
124186 MachineInstr::const_mop_iterator MOE,
128190 MCSymbol *MILabel = OutContext.CreateTempSymbol();
129191 AP.OutStreamer.EmitLabel(MILabel);
130192
131 LocationVec CallsiteLocs;
193 LocationVec Locations;
194 LiveOutVec LiveOuts;
132195
133196 if (recordResult) {
134197 std::pair ParseResult =
137200 Location &Loc = ParseResult.first;
138201 assert(Loc.LocType == Location::Register &&
139202 "Stackmap return location must be a register.");
140 CallsiteLocs.push_back(Loc);
203 Locations.push_back(Loc);
141204 }
142205
143206 while (MOI != MOE) {
150213 Loc.Offset = ConstPool.getConstantIndex(Loc.Offset);
151214 }
152215
153 CallsiteLocs.push_back(Loc);
216 // Skip the register mask and register live-out mask
217 if (Loc.LocType != Location::Unprocessed)
218 Locations.push_back(Loc);
154219 }
155220
156221 const MCExpr *CSOffsetExpr = MCBinaryExpr::CreateSub(
158223 MCSymbolRefExpr::Create(AP.CurrentFnSym, OutContext),
159224 OutContext);
160225
161 CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, CallsiteLocs));
226 if (MOI->isRegLiveOut())
227 LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());
228
229 CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, Locations, LiveOuts));
162230 }
163231
164232 static MachineInstr::const_mop_iterator
165233 getStackMapEndMOP(MachineInstr::const_mop_iterator MOI,
166234 MachineInstr::const_mop_iterator MOE) {
167235 for (; MOI != MOE; ++MOI)
168 if (MOI->isRegMask() || (MOI->isReg() && MOI->isImplicit()))
236 if (MOI->isRegLiveOut() || (MOI->isReg() && MOI->isImplicit()))
169237 break;
170
171238 return MOI;
172239 }
173240
174241 void StackMaps::recordStackMap(const MachineInstr &MI) {
175 assert(MI.getOpcode() == TargetOpcode::STACKMAP && "exected stackmap");
242 assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");
176243
177244 int64_t ID = MI.getOperand(0).getImm();
178245 recordStackMapOpers(MI, ID, llvm::next(MI.operands_begin(), 2),
181248 }
182249
183250 void StackMaps::recordPatchPoint(const MachineInstr &MI) {
184 assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "exected stackmap");
251 assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "expected patchpoint");
185252
186253 PatchPointOpers opers(&MI);
187254 int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
220287 /// uint16 : Dwarf RegNum
221288 /// int32 : Offset
222289 /// }
290 /// uint16 : NumLiveOuts
291 /// LiveOuts[NumLiveOuts]
292 /// uint16 : Dwarf RegNum
293 /// uint8 : Reserved
294 /// uint8 : Size in Bytes
223295 /// }
224296 ///
225297 /// Location Encoding, Type, Value:
272344
273345 uint64_t CallsiteID = CSII->ID;
274346 const LocationVec &CSLocs = CSII->Locations;
347 const LiveOutVec &LiveOuts = CSII->LiveOuts;
275348
276349 DEBUG(dbgs() << WSMP << "callsite " << CallsiteID << "\n");
277350
279352 // runtime than crash in case of in-process compilation. Currently, we do
280353 // simple overflow checks, but we may eventually communicate other
281354 // compilation errors this way.
282 if (CSLocs.size() > UINT16_MAX) {
283 AP.OutStreamer.EmitIntValue(UINT32_MAX, 8); // Invalid ID.
355 if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) {
356 AP.OutStreamer.EmitIntValue(UINT64_MAX, 8); // Invalid ID.
284357 AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
285358 AP.OutStreamer.EmitIntValue(0, 2); // Reserved.
286359 AP.OutStreamer.EmitIntValue(0, 2); // 0 locations.
360 AP.OutStreamer.EmitIntValue(0, 2); // 0 live-out registers.
287361 continue;
288362 }
289363
360434 AP.OutStreamer.EmitIntValue(RegNo, 2);
361435 AP.OutStreamer.EmitIntValue(Offset, 4);
362436 }
437
438 DEBUG(dbgs() << WSMP << " has " << LiveOuts.size()
439 << " live-out registers\n");
440
441 AP.OutStreamer.EmitIntValue(LiveOuts.size(), 2);
442
443 operIdx = 0;
444 for (LiveOutVec::const_iterator LI = LiveOuts.begin(), LE = LiveOuts.end();
445 LI != LE; ++LI, ++operIdx) {
446 DEBUG(dbgs() << WSMP << " LO " << operIdx << ": "
447 << MCRI.getName(LI->Reg)
448 << " [encoding: .short " << LI->RegNo
449 << ", .byte 0, .byte " << LI->Size << "]\n");
450
451 AP.OutStreamer.EmitIntValue(LI->RegNo, 2);
452 AP.OutStreamer.EmitIntValue(0, 1);
453 AP.OutStreamer.EmitIntValue(LI->Size, 1);
454 }
363455 }
364456
365457 AP.OutStreamer.AddBlankLine();
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim | FileCheck %s
1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim -enable-stackmap-liveness| FileCheck -check-prefix=STACK %s
2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim -enable-patchpoint-liveness| FileCheck -check-prefix=PATCH %s
3 ;
4 ; Note: Print verbose stackmaps using -debug-only=stackmaps.
5
6 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
7 ; CHECK-NEXT: __LLVM_StackMaps:
8 ; CHECK-NEXT: .long 0
9 ; Num LargeConstants
10 ; CHECK-NEXT: .long 0
11 ; Num Callsites
12 ; CHECK-NEXT: .long 5
13 define void @stackmap_liveness() {
14 entry:
15 %a1 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
16 ; StackMap 1 (no liveness information available)
17 ; CHECK-LABEL: .long L{{.*}}-_stackmap_liveness
18 ; CHECK-NEXT: .short 0
19 ; CHECK-NEXT: .short 0
20 ; Num LiveOut Entries: 0
21 ; CHECK-NEXT: .short 0
22
23 ; StackMap 1 (stackmap liveness information enabled)
24 ; STACK-LABEL: .long L{{.*}}-_stackmap_liveness
25 ; STACK-NEXT: .short 0
26 ; STACK-NEXT: .short 0
27 ; Num LiveOut Entries: 2
28 ; STACK-NEXT: .short 2
29 ; LiveOut Entry 1: %RSP (8 bytes)
30 ; STACK-NEXT: .short 7
31 ; STACK-NEXT: .byte 0
32 ; STACK-NEXT: .byte 8
33 ; LiveOut Entry 2: %YMM2 (16 bytes) --> %XMM2
34 ; STACK-NEXT: .short 19
35 ; STACK-NEXT: .byte 0
36 ; STACK-NEXT: .byte 16
37
38 ; StackMap 1 (patchpoint liveness information enabled)
39 ; PATCH-LABEL: .long L{{.*}}-_stackmap_liveness
40 ; PATCH-NEXT: .short 0
41 ; PATCH-NEXT: .short 0
42 ; Num LiveOut Entries: 0
43 ; PATCH-NEXT: .short 0
44 call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 1, i32 5)
45 %a2 = call i64 asm sideeffect "", "={r8}"() nounwind
46 %a3 = call i8 asm sideeffect "", "={ah}"() nounwind
47 %a4 = call <4 x double> asm sideeffect "", "={ymm0}"() nounwind
48 %a5 = call <4 x double> asm sideeffect "", "={ymm1}"() nounwind
49
50 ; StackMap 2 (no liveness information available)
51 ; CHECK-LABEL: .long L{{.*}}-_stackmap_liveness
52 ; CHECK-NEXT: .short 0
53 ; CHECK-NEXT: .short 0
54 ; Num LiveOut Entries: 0
55 ; CHECK-NEXT: .short 0
56
57 ; StackMap 2 (stackmap liveness information enabled)
58 ; STACK-LABEL: .long L{{.*}}-_stackmap_liveness
59 ; STACK-NEXT: .short 0
60 ; STACK-NEXT: .short 0
61 ; Num LiveOut Entries: 6
62 ; STACK-NEXT: .short 6
63 ; LiveOut Entry 2: %RAX (1 bytes) --> %AL or %AH
64 ; STACK-NEXT: .short 0
65 ; STACK-NEXT: .byte 0
66 ; STACK-NEXT: .byte 1
67 ; LiveOut Entry 2: %RSP (8 bytes)
68 ; STACK-NEXT: .short 7
69 ; STACK-NEXT: .byte 0
70 ; STACK-NEXT: .byte 8
71 ; LiveOut Entry 2: %R8 (8 bytes)
72 ; STACK-NEXT: .short 8
73 ; STACK-NEXT: .byte 0
74 ; STACK-NEXT: .byte 8
75 ; LiveOut Entry 2: %YMM0 (32 bytes)
76 ; STACK-NEXT: .short 17
77 ; STACK-NEXT: .byte 0
78 ; STACK-NEXT: .byte 32
79 ; LiveOut Entry 2: %YMM1 (32 bytes)
80 ; STACK-NEXT: .short 18
81 ; STACK-NEXT: .byte 0
82 ; STACK-NEXT: .byte 32
83 ; LiveOut Entry 2: %YMM2 (16 bytes) --> %XMM2
84 ; STACK-NEXT: .short 19
85 ; STACK-NEXT: .byte 0
86 ; STACK-NEXT: .byte 16
87
88 ; StackMap 2 (patchpoint liveness information enabled)
89 ; PATCH-LABEL: .long L{{.*}}-_stackmap_liveness
90 ; PATCH-NEXT: .short 0
91 ; PATCH-NEXT: .short 0
92 ; Num LiveOut Entries: 0
93 ; PATCH-NEXT: .short 0
94 call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 2, i32 5)
95 call void asm sideeffect "", "{r8},{ah},{ymm0},{ymm1}"(i64 %a2, i8 %a3, <4 x double> %a4, <4 x double> %a5) nounwind
96
97 ; StackMap 3 (no liveness information available)
98 ; CHECK-LABEL: .long L{{.*}}-_stackmap_liveness
99 ; CHECK-NEXT: .short 0
100 ; CHECK-NEXT: .short 0
101 ; Num LiveOut Entries: 0
102 ; CHECK-NEXT: .short 0
103
104 ; StackMap 3 (stackmap liveness information enabled)
105 ; STACK-LABEL: .long L{{.*}}-_stackmap_liveness
106 ; STACK-NEXT: .short 0
107 ; STACK-NEXT: .short 0
108 ; Num LiveOut Entries: 2
109 ; STACK-NEXT: .short 2
110 ; LiveOut Entry 2: %RSP (8 bytes)
111 ; STACK-NEXT: .short 7
112 ; STACK-NEXT: .byte 0
113 ; STACK-NEXT: .byte 8
114 ; LiveOut Entry 2: %YMM2 (16 bytes) --> %XMM2
115 ; STACK-NEXT: .short 19
116 ; STACK-NEXT: .byte 0
117 ; STACK-NEXT: .byte 16
118
119 ; StackMap 3 (patchpoint liveness information enabled)
120 ; PATCH-LABEL: .long L{{.*}}-_stackmap_liveness
121 ; PATCH-NEXT: .short 0
122 ; PATCH-NEXT: .short 0
123 ; Num LiveOut Entries: 0
124 ; PATCH-NEXT: .short 0
125 call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 5)
126 call void asm sideeffect "", "{xmm2}"(<2 x double> %a1) nounwind
127 ret void
128 }
129
130 define void @mixed_liveness() {
131 entry:
132 %a1 = call <2 x double> asm sideeffect "", "={xmm2}"() nounwind
133 ; StackMap 4 (stackmap liveness information enabled)
134 ; STACK-LABEL: .long L{{.*}}-_mixed_liveness
135 ; STACK-NEXT: .short 0
136 ; STACK-NEXT: .short 0
137 ; Num LiveOut Entries: 1
138 ; STACK-NEXT: .short 1
139 ; LiveOut Entry 1: %YMM2 (16 bytes) --> %XMM2
140 ; STACK-NEXT: .short 19
141 ; STACK-NEXT: .byte 0
142 ; STACK-NEXT: .byte 16
143 ; StackMap 5 (stackmap liveness information enabled)
144 ; STACK-LABEL: .long L{{.*}}-_mixed_liveness
145 ; STACK-NEXT: .short 0
146 ; STACK-NEXT: .short 0
147 ; Num LiveOut Entries: 0
148 ; STACK-NEXT: .short 0
149
150 ; StackMap 4 (patchpoint liveness information enabled)
151 ; PATCH-LABEL: .long L{{.*}}-_mixed_liveness
152 ; PATCH-NEXT: .short 0
153 ; PATCH-NEXT: .short 0
154 ; Num LiveOut Entries: 0
155 ; PATCH-NEXT: .short 0
156 ; StackMap 5 (patchpoint liveness information enabled)
157 ; PATCH-LABEL: .long L{{.*}}-_mixed_liveness
158 ; PATCH-NEXT: .short 0
159 ; PATCH-NEXT: .short 0
160 ; Num LiveOut Entries: 2
161 ; PATCH-NEXT: .short 2
162 ; LiveOut Entry 1: %RSP (8 bytes)
163 ; PATCH-NEXT: .short 7
164 ; PATCH-NEXT: .byte 0
165 ; PATCH-NEXT: .byte 8
166 ; LiveOut Entry 1: %YMM2 (16 bytes) --> %XMM2
167 ; PATCH-NEXT: .short 19
168 ; PATCH-NEXT: .byte 0
169 ; PATCH-NEXT: .byte 16
170 call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 5)
171 call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 5, i32 0, i8* null, i32 0)
172 call void asm sideeffect "", "{xmm2}"(<2 x double> %a1) nounwind
173 ret void
174 }
175
176 declare void @llvm.experimental.stackmap(i64, i32, ...)
177 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
182182 ;
183183 ; Verify 17 stack map entries.
184184 ;
185 ; CHECK-LABEL:.long L{{.*}}-_spilledValue
186 ; CHECK-NEXT: .short 0
187 ; CHECK-NEXT: .short 17
185 ; CHECK-LABEL: .long L{{.*}}-_spilledValue
186 ; CHECK-NEXT: .short 0
187 ; CHECK-NEXT: .short 17
188188 ;
189189 ; Check that at least one is a spilled entry from RBP.
190190 ; Location: Indirect RBP + ...
191 ; CHECK: .byte 3
192 ; CHECK-NEXT: .byte 8
193 ; CHECK-NEXT: .short 6
191 ; CHECK: .byte 3
192 ; CHECK-NEXT: .byte 8
193 ; CHECK-NEXT: .short 6
194194 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
195195 entry:
196196 call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 15, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
201201 ;
202202 ; Verify 17 stack map entries.
203203 ;
204 ; CHECK-LABEL: .long L{{.*}}-_spilledStackMapValue
205 ; CHECK-NEXT: .short 0
206 ; CHECK-NEXT: .short 17
204 ; CHECK-LABEL: .long L{{.*}}-_spilledStackMapValue
205 ; CHECK-NEXT: .short 0
206 ; CHECK-NEXT: .short 17
207207 ;
208208 ; Check that at least one is a spilled entry from RBP.
209209 ; Location: Indirect RBP + ...
210 ; CHECK: .byte 3
211 ; CHECK-NEXT: .byte 8
212 ; CHECK-NEXT: .short 6
210 ; CHECK: .byte 3
211 ; CHECK-NEXT: .byte 8
212 ; CHECK-NEXT: .short 6
213213 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16) {
214214 entry:
215215 call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 15, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16)
218218
219219 ; Spill a subregister stackmap operand.
220220 ;
221 ; CHECK-LABEL: .long L{{.*}}-_spillSubReg
222 ; CHECK-NEXT: .short 0
221 ; CHECK-LABEL: .long L{{.*}}-_spillSubReg
222 ; CHECK-NEXT: .short 0
223223 ; 4 locations
224 ; CHECK-NEXT: .short 1
224 ; CHECK-NEXT: .short 1
225225 ;
226226 ; Check that the subregister operand is a 4-byte spill.
227227 ; Location: Indirect, 4-byte, RBP + ...
228 ; CHECK: .byte 3
229 ; CHECK-NEXT: .byte 4
230 ; CHECK-NEXT: .short 6
228 ; CHECK: .byte 3
229 ; CHECK-NEXT: .byte 4
230 ; CHECK-NEXT: .short 6
231231 define void @spillSubReg(i64 %arg) #0 {
232232 bb:
233233 br i1 undef, label %bb1, label %bb2
258258 ; Map a single byte subregister. There is no DWARF register number, so
259259 ; we expect the register to be encoded with the proper size and spill offset. We don't know which
260260 ;
261 ; CHECK-LABEL: .long L{{.*}}-_subRegOffset
262 ; CHECK-NEXT: .short 0
261 ; CHECK-LABEL: .long L{{.*}}-_subRegOffset
262 ; CHECK-NEXT: .short 0
263263 ; 2 locations
264 ; CHECK-NEXT: .short 2
264 ; CHECK-NEXT: .short 2
265265 ;
266266 ; Check that the subregister operands are 1-byte spills.
267267 ; Location 0: Register, 4-byte, AL
268 ; CHECK-NEXT: .byte 1
269 ; CHECK-NEXT: .byte 1
270 ; CHECK-NEXT: .short 0
271 ; CHECK-NEXT: .long 0
268 ; CHECK-NEXT: .byte 1
269 ; CHECK-NEXT: .byte 1
270 ; CHECK-NEXT: .short 0
271 ; CHECK-NEXT: .long 0
272272 ;
273273 ; Location 1: Register, 4-byte, BL
274 ; CHECK-NEXT: .byte 1
275 ; CHECK-NEXT: .byte 1
276 ; CHECK-NEXT: .short 3
277 ; CHECK-NEXT: .long 0
274 ; CHECK-NEXT: .byte 1
275 ; CHECK-NEXT: .byte 1
276 ; CHECK-NEXT: .short 3
277 ; CHECK-NEXT: .long 0
278278 define void @subRegOffset(i16 %arg) {
279279 %v = mul i16 %arg, 5
280280 %a0 = trunc i16 %v to i8
288288
289289 ; Map a constant value.
290290 ;
291 ; CHECK-LABEL: .long L{{.*}}-_liveConstant
292 ; CHECK-NEXT: .short 0
291 ; CHECK-LABEL: .long L{{.*}}-_liveConstant
292 ; CHECK-NEXT: .short 0
293293 ; 1 location
294 ; CHECK-NEXT: .short 1
294 ; CHECK-NEXT: .short 1
295295 ; Loc 0: SmallConstant
296296 ; CHECK-NEXT: .byte 4
297297 ; CHECK-NEXT: .byte 8
315315 ; CHECK-NEXT: .byte 8
316316 ; CHECK-NEXT: .short 6
317317 ; CHECK-NEXT: .long
318 ; CHECK-NEXT: .quad
318
319319 ; Callsite 17
320 ; CHECK-NEXT: .long L{{.*}}-_directFrameIdx
320 ; CHECK-LABEL: .long L{{.*}}-_directFrameIdx
321321 ; CHECK-NEXT: .short 0
322322 ; 2 locations
323323 ; CHECK-NEXT: .short 2