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ARM: Enforce decoding rules for VLDn instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183731 91177308-0d34-0410-b5e6-96231b3b80d8 Amaury de la Vieuville 7 years ago
5 changed file(s) with 149 addition(s) and 117 deletion(s). Raw diff Collapse all Expand all
625625 "vld1", Dt, "$Vd, $Rn", "", []> {
626626 let Rm = 0b1111;
627627 let Inst{4} = Rn{4};
628 let DecoderMethod = "DecodeVLDInstruction";
628 let DecoderMethod = "DecodeVLDST1Instruction";
629629 }
630630 class VLD1Q op7_4, string Dt>
631631 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
633633 "vld1", Dt, "$Vd, $Rn", "", []> {
634634 let Rm = 0b1111;
635635 let Inst{5-4} = Rn{5-4};
636 let DecoderMethod = "DecodeVLDInstruction";
636 let DecoderMethod = "DecodeVLDST1Instruction";
637637 }
638638
639639 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
654654 "$Rn.addr = $wb", []> {
655655 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
656656 let Inst{4} = Rn{4};
657 let DecoderMethod = "DecodeVLDInstruction";
657 let DecoderMethod = "DecodeVLDST1Instruction";
658658 let AsmMatchConverter = "cvtVLDwbFixed";
659659 }
660660 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
662662 "vld1", Dt, "$Vd, $Rn, $Rm",
663663 "$Rn.addr = $wb", []> {
664664 let Inst{4} = Rn{4};
665 let DecoderMethod = "DecodeVLDInstruction";
665 let DecoderMethod = "DecodeVLDST1Instruction";
666666 let AsmMatchConverter = "cvtVLDwbRegister";
667667 }
668668 }
673673 "$Rn.addr = $wb", []> {
674674 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
675675 let Inst{5-4} = Rn{5-4};
676 let DecoderMethod = "DecodeVLDInstruction";
676 let DecoderMethod = "DecodeVLDST1Instruction";
677677 let AsmMatchConverter = "cvtVLDwbFixed";
678678 }
679679 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
681681 "vld1", Dt, "$Vd, $Rn, $Rm",
682682 "$Rn.addr = $wb", []> {
683683 let Inst{5-4} = Rn{5-4};
684 let DecoderMethod = "DecodeVLDInstruction";
684 let DecoderMethod = "DecodeVLDST1Instruction";
685685 let AsmMatchConverter = "cvtVLDwbRegister";
686686 }
687687 }
702702 "$Vd, $Rn", "", []> {
703703 let Rm = 0b1111;
704704 let Inst{4} = Rn{4};
705 let DecoderMethod = "DecodeVLDInstruction";
705 let DecoderMethod = "DecodeVLDST1Instruction";
706706 }
707707 multiclass VLD1D3WB op7_4, string Dt> {
708708 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
711711 "$Rn.addr = $wb", []> {
712712 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
713713 let Inst{4} = Rn{4};
714 let DecoderMethod = "DecodeVLDInstruction";
714 let DecoderMethod = "DecodeVLDST1Instruction";
715715 let AsmMatchConverter = "cvtVLDwbFixed";
716716 }
717717 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
719719 "vld1", Dt, "$Vd, $Rn, $Rm",
720720 "$Rn.addr = $wb", []> {
721721 let Inst{4} = Rn{4};
722 let DecoderMethod = "DecodeVLDInstruction";
722 let DecoderMethod = "DecodeVLDST1Instruction";
723723 let AsmMatchConverter = "cvtVLDwbRegister";
724724 }
725725 }
743743 "$Vd, $Rn", "", []> {
744744 let Rm = 0b1111;
745745 let Inst{5-4} = Rn{5-4};
746 let DecoderMethod = "DecodeVLDInstruction";
746 let DecoderMethod = "DecodeVLDST1Instruction";
747747 }
748748 multiclass VLD1D4WB op7_4, string Dt> {
749749 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
752752 "$Rn.addr = $wb", []> {
753753 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
754754 let Inst{5-4} = Rn{5-4};
755 let DecoderMethod = "DecodeVLDInstruction";
755 let DecoderMethod = "DecodeVLDST1Instruction";
756756 let AsmMatchConverter = "cvtVLDwbFixed";
757757 }
758758 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
760760 "vld1", Dt, "$Vd, $Rn, $Rm",
761761 "$Rn.addr = $wb", []> {
762762 let Inst{5-4} = Rn{5-4};
763 let DecoderMethod = "DecodeVLDInstruction";
763 let DecoderMethod = "DecodeVLDST1Instruction";
764764 let AsmMatchConverter = "cvtVLDwbRegister";
765765 }
766766 }
785785 "vld2", Dt, "$Vd, $Rn", "", []> {
786786 let Rm = 0b1111;
787787 let Inst{5-4} = Rn{5-4};
788 let DecoderMethod = "DecodeVLDInstruction";
788 let DecoderMethod = "DecodeVLDST2Instruction";
789789 }
790790
791791 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
809809 "$Rn.addr = $wb", []> {
810810 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
811811 let Inst{5-4} = Rn{5-4};
812 let DecoderMethod = "DecodeVLDInstruction";
812 let DecoderMethod = "DecodeVLDST2Instruction";
813813 let AsmMatchConverter = "cvtVLDwbFixed";
814814 }
815815 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
817817 "vld2", Dt, "$Vd, $Rn, $Rm",
818818 "$Rn.addr = $wb", []> {
819819 let Inst{5-4} = Rn{5-4};
820 let DecoderMethod = "DecodeVLDInstruction";
820 let DecoderMethod = "DecodeVLDST2Instruction";
821821 let AsmMatchConverter = "cvtVLDwbRegister";
822822 }
823823 }
852852 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
853853 let Rm = 0b1111;
854854 let Inst{4} = Rn{4};
855 let DecoderMethod = "DecodeVLDInstruction";
855 let DecoderMethod = "DecodeVLDST3Instruction";
856856 }
857857
858858 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
871871 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
872872 "$Rn.addr = $wb", []> {
873873 let Inst{4} = Rn{4};
874 let DecoderMethod = "DecodeVLDInstruction";
874 let DecoderMethod = "DecodeVLDST3Instruction";
875875 }
876876
877877 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
911911 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
912912 let Rm = 0b1111;
913913 let Inst{5-4} = Rn{5-4};
914 let DecoderMethod = "DecodeVLDInstruction";
914 let DecoderMethod = "DecodeVLDST4Instruction";
915915 }
916916
917917 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
930930 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
931931 "$Rn.addr = $wb", []> {
932932 let Inst{5-4} = Rn{5-4};
933 let DecoderMethod = "DecodeVLDInstruction";
933 let DecoderMethod = "DecodeVLDST4Instruction";
934934 }
935935
936936 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
15791579 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
15801580 let Rm = 0b1111;
15811581 let Inst{4} = Rn{4};
1582 let DecoderMethod = "DecodeVST1Instruction";
1582 let DecoderMethod = "DecodeVLDST1Instruction";
15831583 }
15841584 class VST1Q op7_4, string Dt>
15851585 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
15861586 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
15871587 let Rm = 0b1111;
15881588 let Inst{5-4} = Rn{5-4};
1589 let DecoderMethod = "DecodeVST1Instruction";
1589 let DecoderMethod = "DecodeVLDST1Instruction";
15901590 }
15911591
15921592 def VST1d8 : VST1D<{0,0,0,?}, "8">;
16071607 "$Rn.addr = $wb", []> {
16081608 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16091609 let Inst{4} = Rn{4};
1610 let DecoderMethod = "DecodeVST1Instruction";
1610 let DecoderMethod = "DecodeVLDST1Instruction";
16111611 let AsmMatchConverter = "cvtVSTwbFixed";
16121612 }
16131613 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
16161616 "vst1", Dt, "$Vd, $Rn, $Rm",
16171617 "$Rn.addr = $wb", []> {
16181618 let Inst{4} = Rn{4};
1619 let DecoderMethod = "DecodeVST1Instruction";
1619 let DecoderMethod = "DecodeVLDST1Instruction";
16201620 let AsmMatchConverter = "cvtVSTwbRegister";
16211621 }
16221622 }
16271627 "$Rn.addr = $wb", []> {
16281628 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16291629 let Inst{5-4} = Rn{5-4};
1630 let DecoderMethod = "DecodeVST1Instruction";
1630 let DecoderMethod = "DecodeVLDST1Instruction";
16311631 let AsmMatchConverter = "cvtVSTwbFixed";
16321632 }
16331633 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
16361636 "vst1", Dt, "$Vd, $Rn, $Rm",
16371637 "$Rn.addr = $wb", []> {
16381638 let Inst{5-4} = Rn{5-4};
1639 let DecoderMethod = "DecodeVST1Instruction";
1639 let DecoderMethod = "DecodeVLDST1Instruction";
16401640 let AsmMatchConverter = "cvtVSTwbRegister";
16411641 }
16421642 }
16581658 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
16591659 let Rm = 0b1111;
16601660 let Inst{4} = Rn{4};
1661 let DecoderMethod = "DecodeVST1Instruction";
1661 let DecoderMethod = "DecodeVLDST1Instruction";
16621662 }
16631663 multiclass VST1D3WB op7_4, string Dt> {
16641664 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
16671667 "$Rn.addr = $wb", []> {
16681668 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
16691669 let Inst{5-4} = Rn{5-4};
1670 let DecoderMethod = "DecodeVST1Instruction";
1670 let DecoderMethod = "DecodeVLDST1Instruction";
16711671 let AsmMatchConverter = "cvtVSTwbFixed";
16721672 }
16731673 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
16761676 "vst1", Dt, "$Vd, $Rn, $Rm",
16771677 "$Rn.addr = $wb", []> {
16781678 let Inst{5-4} = Rn{5-4};
1679 let DecoderMethod = "DecodeVST1Instruction";
1679 let DecoderMethod = "DecodeVLDST1Instruction";
16801680 let AsmMatchConverter = "cvtVSTwbRegister";
16811681 }
16821682 }
17031703 []> {
17041704 let Rm = 0b1111;
17051705 let Inst{5-4} = Rn{5-4};
1706 let DecoderMethod = "DecodeVST1Instruction";
1706 let DecoderMethod = "DecodeVLDST1Instruction";
17071707 }
17081708 multiclass VST1D4WB op7_4, string Dt> {
17091709 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
17121712 "$Rn.addr = $wb", []> {
17131713 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
17141714 let Inst{5-4} = Rn{5-4};
1715 let DecoderMethod = "DecodeVST1Instruction";
1715 let DecoderMethod = "DecodeVLDST1Instruction";
17161716 let AsmMatchConverter = "cvtVSTwbFixed";
17171717 }
17181718 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
17211721 "vst1", Dt, "$Vd, $Rn, $Rm",
17221722 "$Rn.addr = $wb", []> {
17231723 let Inst{5-4} = Rn{5-4};
1724 let DecoderMethod = "DecodeVST1Instruction";
1724 let DecoderMethod = "DecodeVLDST1Instruction";
17251725 let AsmMatchConverter = "cvtVSTwbRegister";
17261726 }
17271727 }
17471747 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
17481748 let Rm = 0b1111;
17491749 let Inst{5-4} = Rn{5-4};
1750 let DecoderMethod = "DecodeVST2Instruction";
1750 let DecoderMethod = "DecodeVLDST2Instruction";
17511751 }
17521752
17531753 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
17711771 "$Rn.addr = $wb", []> {
17721772 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
17731773 let Inst{5-4} = Rn{5-4};
1774 let DecoderMethod = "DecodeVST2Instruction";
1774 let DecoderMethod = "DecodeVLDST2Instruction";
17751775 let AsmMatchConverter = "cvtVSTwbFixed";
17761776 }
17771777 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
17791779 "vst2", Dt, "$Vd, $Rn, $Rm",
17801780 "$Rn.addr = $wb", []> {
17811781 let Inst{5-4} = Rn{5-4};
1782 let DecoderMethod = "DecodeVST2Instruction";
1782 let DecoderMethod = "DecodeVLDST2Instruction";
17831783 let AsmMatchConverter = "cvtVSTwbRegister";
17841784 }
17851785 }
17901790 "$Rn.addr = $wb", []> {
17911791 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
17921792 let Inst{5-4} = Rn{5-4};
1793 let DecoderMethod = "DecodeVST2Instruction";
1793 let DecoderMethod = "DecodeVLDST2Instruction";
17941794 let AsmMatchConverter = "cvtVSTwbFixed";
17951795 }
17961796 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
17991799 "vst2", Dt, "$Vd, $Rn, $Rm",
18001800 "$Rn.addr = $wb", []> {
18011801 let Inst{5-4} = Rn{5-4};
1802 let DecoderMethod = "DecodeVST2Instruction";
1802 let DecoderMethod = "DecodeVLDST2Instruction";
18031803 let AsmMatchConverter = "cvtVSTwbRegister";
18041804 }
18051805 }
18341834 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
18351835 let Rm = 0b1111;
18361836 let Inst{4} = Rn{4};
1837 let DecoderMethod = "DecodeVST3Instruction";
1837 let DecoderMethod = "DecodeVLDST3Instruction";
18381838 }
18391839
18401840 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
18531853 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
18541854 "$Rn.addr = $wb", []> {
18551855 let Inst{4} = Rn{4};
1856 let DecoderMethod = "DecodeVST3Instruction";
1856 let DecoderMethod = "DecodeVLDST3Instruction";
18571857 }
18581858
18591859 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
18931893 "", []> {
18941894 let Rm = 0b1111;
18951895 let Inst{5-4} = Rn{5-4};
1896 let DecoderMethod = "DecodeVST4Instruction";
1896 let DecoderMethod = "DecodeVLDST4Instruction";
18971897 }
18981898
18991899 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
19121912 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
19131913 "$Rn.addr = $wb", []> {
19141914 let Inst{5-4} = Rn{5-4};
1915 let DecoderMethod = "DecodeVST4Instruction";
1915 let DecoderMethod = "DecodeVLDST4Instruction";
19161916 }
19171917
19181918 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
240240 uint64_t Address, const void *Decoder);
241241 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
242242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
243251 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val,
252252 uint64_t Address, const void *Decoder);
253253 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
254254 uint64_t Address, const void *Decoder);
24292429 return S;
24302430 }
24312431
2432 static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn,
2433 uint64_t Addr, const void* Decoder) {
2432 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2433 uint64_t Address, const void *Decoder) {
24342434 unsigned type = fieldFromInstruction(Insn, 8, 4);
24352435 unsigned align = fieldFromInstruction(Insn, 4, 2);
2436 if(type == 7 && (align & 2)) return MCDisassembler::Fail;
2437 if(type == 10 && align == 3) return MCDisassembler::Fail;
2438 if(type == 6 && (align & 2)) return MCDisassembler::Fail;
2439
2440 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2441 }
2442
2443 static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn,
2444 uint64_t Addr, const void* Decoder) {
2436 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2437 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2438 if (type == 10 && align == 3) return MCDisassembler::Fail;
2439
2440 unsigned load = fieldFromInstruction(Insn, 21, 1);
2441 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2442 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2443 }
2444
2445 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2446 uint64_t Address, const void *Decoder) {
24452447 unsigned size = fieldFromInstruction(Insn, 6, 2);
2446 if(size == 3) return MCDisassembler::Fail;
2448 if (size == 3) return MCDisassembler::Fail;
24472449
24482450 unsigned type = fieldFromInstruction(Insn, 8, 4);
24492451 unsigned align = fieldFromInstruction(Insn, 4, 2);
2450 if(type == 8 && align == 3) return MCDisassembler::Fail;
2451 if(type == 9 && align == 3) return MCDisassembler::Fail;
2452
2453 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2454 }
2455
2456 static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn,
2457 uint64_t Addr, const void* Decoder) {
2452 if (type == 8 && align == 3) return MCDisassembler::Fail;
2453 if (type == 9 && align == 3) return MCDisassembler::Fail;
2454
2455 unsigned load = fieldFromInstruction(Insn, 21, 1);
2456 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2457 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2458 }
2459
2460 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2461 uint64_t Address, const void *Decoder) {
24582462 unsigned size = fieldFromInstruction(Insn, 6, 2);
2459 if(size == 3) return MCDisassembler::Fail;
2463 if (size == 3) return MCDisassembler::Fail;
24602464
24612465 unsigned align = fieldFromInstruction(Insn, 4, 2);
2462 if(align & 2) return MCDisassembler::Fail;
2463
2464 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2465 }
2466
2467 static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn,
2468 uint64_t Addr, const void* Decoder) {
2466 if (align & 2) return MCDisassembler::Fail;
2467
2468 unsigned load = fieldFromInstruction(Insn, 21, 1);
2469 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2470 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2471 }
2472
2473 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2474 uint64_t Address, const void *Decoder) {
24692475 unsigned size = fieldFromInstruction(Insn, 6, 2);
2470 if(size == 3) return MCDisassembler::Fail;
2471
2472 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2476 if (size == 3) return MCDisassembler::Fail;
2477
2478 unsigned load = fieldFromInstruction(Insn, 21, 1);
2479 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2480 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
24732481 }
24742482
24752483 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
0 # VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
1 # RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
2
3 # VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
4 # RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
5
6 # VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
7 # RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
8
9 # VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
10 # RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
11
12 # VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
13 # RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
14
15 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
16 # RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
17
18 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
19 # RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
20
21 # VST3 multi-element, size = 0b11 -> undefined
22 # RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
23
24 # VST3 multi-element, align = 0b10 -> undefined
25 # RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
26
27 # VST3 multi-element, align = 0b11 -> undefined
28 # RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
29
30 # VST4 multi-element, size = 0b11 -> undefined
31 # RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
32
33 # VLD1 multi-element, type=0b1010 align=0b11
34 # RUN: echo "0x24 0xf9 0xbf 0x8a" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
35
36 # VLD1 multi-element type=0b0111 align=0b1x
37 # RUN: echo "0x24 0xf9 0xbf 0x87" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
38
39 # VLD1 multi-element type=0b0010 align=0b1x
40 # RUN: echo "0x24 0xf9 0xbf 0x86" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
41
42 # VLD2 multi-element size=0b11
43 # RUN: echo "0x60 0xf9 0xcf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
44
45 # VLD2 multi-element type=0b1111 align=0b11
46 # RUN: echo "0x60 0xf9 0xbf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
47
48 # VLD2 multi-element type=0b1001 align=0b11
49 # RUN: echo "0x60 0xf9 0xbf 0x09" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
50
51 # VLD3 multi-element size=0b11
52 # RUN: echo "0x60 0xf9 0x7f 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
53
54 # VLD3 multi-element align=0b1x
55 # RUN: echo "0x60 0xf9 0xcf 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
56
57 # VLD4 multi-element size=0b11
58 # RUN: echo "0x60 0xf9 0xcd 0x11" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
59
60 # CHECK: invalid instruction encoding
61
+0
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test/MC/Disassembler/ARM/invalid-VST-arm.txt less more
None # VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
1 # RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
2
3 # VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
4 # RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
5
6 # VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
7 # RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
8
9 # VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
10 # RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
11
12 # VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
13 # RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
14
15 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
16 # RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
17
18 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
19 # RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
20
21 # VST3 multi-element, size = 0b11 -> undefined
22 # RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
23
24 # VST3 multi-element, align = 0b10 -> undefined
25 # RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
26
27 # VST3 multi-element, align = 0b11 -> undefined
28 # RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
29
30 # VST4 multi-element, size = 0b11 -> undefined
31 # RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -show-encoding -disassemble 2>&1 | FileCheck %s
32
33 # CHECK: invalid instruction encoding
34
16281628 0xc0 0xf9 0x4f 0x1b
16291629 # CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
16301630
1631 0x63 0xf9 0x37 0xc9
1632 # CHECK: vld2.8 {d28, d30}, [r3:256], r7
1633
16341631 # rdar://10798451
16351632 0xe7 0xf9 0x32 0x1d
16361633 # CHECK vld2.8 {d17[], d19[]}, [r7:16], r2