llvm.org GIT mirror llvm / aa744e2
Table-generated register pressure fixes. Handle mixing allocatable and unallocatable register gracefully. Simplify the pruning of register unit sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154474 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 8 years ago
1 changed file(s) with 48 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
944944
945945 // For simplicitly make the SetID the same as EnumValue.
946946 IntEqClasses UberSetIDs(Registers.size()+1);
947 std::set AllocatableRegs;
947948 for (unsigned i = 0, e = RegBank.getRegClasses().size(); i != e; ++i) {
949
948950 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i];
951 if (!RegClass->Allocatable)
952 continue;
953
949954 const CodeGenRegister::Set &Regs = RegClass->getMembers();
950 if (Regs.empty()) continue;
955 if (Regs.empty())
956 continue;
951957
952958 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
953959 assert(USetID && "register number 0 is invalid");
954960
955 // combine non-allocatable classes
956 if (!RegClass->Allocatable) {
957 UberSetIDs.join(0, USetID);
958 USetID = 0;
959 }
961 AllocatableRegs.insert((*Regs.begin())->EnumValue);
960962 for (CodeGenRegister::Set::const_iterator I = llvm::next(Regs.begin()),
961 E = Regs.end(); I != E; ++I)
963 E = Regs.end(); I != E; ++I) {
964 AllocatableRegs.insert((*I)->EnumValue);
962965 UberSetIDs.join(USetID, (*I)->EnumValue);
966 }
967 }
968 // Combine non-allocatable regs.
969 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
970 unsigned RegNum = Registers[i]->EnumValue;
971 if (AllocatableRegs.count(RegNum))
972 continue;
973
974 UberSetIDs.join(0, RegNum);
963975 }
964976 UberSetIDs.compress();
965977
11541166 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets");
11551167
11561168 // Form an equivalence class of UnitSets with no significant difference.
1157 IntEqClasses RepUnitSetIDs(RegUnitSets.size());
1169 // Populate PrunedUnitSets with each equivalence class's superset.
1170 std::vector PrunedUnitSets;
11581171 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
11591172 SubIdx != EndIdx; ++SubIdx) {
11601173 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1161 for (unsigned SuperIdx = 0; SuperIdx != EndIdx; ++SuperIdx) {
1174 unsigned SuperIdx = 0;
1175 for (; SuperIdx != EndIdx; ++SuperIdx) {
11621176 if (SuperIdx == SubIdx)
11631177 continue;
1164
1165 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1166 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1167 && (SubSet.Units.size() + 3 > SuperSet.Units.size())) {
1168 RepUnitSetIDs.join(SubIdx, SuperIdx);
1178 const RegUnitSet *SuperSet = 0;
1179 if (SuperIdx > SubIdx)
1180 SuperSet = &RegUnitSets[SuperIdx];
1181 else {
1182 // Compare with already-pruned sets.
1183 if (SuperIdx >= PrunedUnitSets.size())
1184 continue;
1185 SuperSet = &PrunedUnitSets[SuperIdx];
11691186 }
1170 }
1171 }
1172 RepUnitSetIDs.compress();
1173
1174 // Populate PrunedUnitSets with each equivalence class's superset.
1175 std::vector PrunedUnitSets(RepUnitSetIDs.getNumClasses());
1176 for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
1177 RegUnitSet &SuperSet = PrunedUnitSets[RepUnitSetIDs[i]];
1178 if (SuperSet.Units.size() < RegUnitSets[i].Units.size())
1179 SuperSet = RegUnitSets[i];
1187 if (isRegUnitSubSet(SubSet.Units, SuperSet->Units)
1188 && (SubSet.Units.size() + 3 > SuperSet->Units.size())) {
1189 break;
1190 }
1191 }
1192 if (SuperIdx != EndIdx)
1193 continue;
1194 PrunedUnitSets.resize(PrunedUnitSets.size()+1);
1195 PrunedUnitSets.back().Name = RegUnitSets[SubIdx].Name;
1196 PrunedUnitSets.back().Units.swap(RegUnitSets[SubIdx].Units);
11801197 }
11811198 RegUnitSets.swap(PrunedUnitSets);
11821199 }
11941211 const ArrayRef &RegClasses = getRegClasses();
11951212 unsigned NumRegClasses = RegClasses.size();
11961213 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1214 if (!RegClasses[RCIdx]->Allocatable)
1215 continue;
11971216
11981217 // Speculatively grow the RegUnitSets to hold the new set.
11991218 RegUnitSets.resize(RegUnitSets.size() + 1);
12521271 }
12531272 }
12541273
1255 // Iteratively prune unit sets again after inferring supersets.
1274 // Iteratively prune unit sets after inferring supersets.
12561275 pruneUnitSets();
12571276
12581277 // For each register class, list the UnitSets that are supersets.
12591278 RegClassUnitSets.resize(NumRegClasses);
12601279 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) {
1280 if (!RegClasses[RCIdx]->Allocatable)
1281 continue;
1282
12611283 // Recompute the sorted list of units in this class.
12621284 std::vector RegUnits;
12631285 buildRegUnitSet(RegClasses[RCIdx]->getMembers(), RegUnits);
12721294 if (isRegUnitSubSet(RegUnits, RegUnitSets[USIdx].Units))
12731295 RegClassUnitSets[RCIdx].push_back(USIdx);
12741296 }
1297 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
12751298 }
12761299 }
12771300