llvm.org GIT mirror llvm / aa4b015
Avoid allocating the same physreg to multiple virtregs in one instruction. While that approach works wonders for register pressure, it tends to break everything. This should unbreak the arm-linux builder and fix a number of miscompilations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103946 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
2 changed file(s) with 106 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
470470
471471 unsigned BestReg = 0, BestCost = spillImpossible;
472472 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
473 if (UsedInInstr.test(*I)) continue;
473474 unsigned Cost = calcSpillCost(*I);
474475 // Cost is 0 when all aliases are already disabled.
475476 if (Cost == 0)
0 ; RUN: llc < %s -regalloc=fast -verify-machineinstrs
1 target triple = "arm-pc-linux-gnu"
2
3 ; This test case would accidentally use the same physreg for two virtregs
4 ; because allocVirtReg forgot to check if registers were already used in the
5 ; instruction.
6 ; This caused the RegScavenger to complain, but -verify-machineinstrs also
7 ; catches it.
8
9 %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
10
11 @search = external global %struct.CHESS_POSITION ; <%struct.CHESS_POSITION*> [#uses=1]
12 @bishop_mobility_rr45 = external global [64 x [256 x i32]] ; <[64 x [256 x i32]]*> [#uses=1]
13
14 declare fastcc i32 @FirstOne()
15
16 define fastcc void @Evaluate() {
17 entry:
18 br i1 false, label %cond_false186, label %cond_true
19
20 cond_true: ; preds = %entry
21 ret void
22
23 cond_false186: ; preds = %entry
24 br i1 false, label %cond_true293, label %bb203
25
26 bb203: ; preds = %cond_false186
27 ret void
28
29 cond_true293: ; preds = %cond_false186
30 br i1 false, label %cond_true298, label %cond_next317
31
32 cond_true298: ; preds = %cond_true293
33 br i1 false, label %cond_next518, label %cond_true397.preheader
34
35 cond_next317: ; preds = %cond_true293
36 ret void
37
38 cond_true397.preheader: ; preds = %cond_true298
39 ret void
40
41 cond_next518: ; preds = %cond_true298
42 br i1 false, label %bb1069, label %cond_true522
43
44 cond_true522: ; preds = %cond_next518
45 ret void
46
47 bb1069: ; preds = %cond_next518
48 br i1 false, label %cond_next1131, label %bb1096
49
50 bb1096: ; preds = %bb1069
51 ret void
52
53 cond_next1131: ; preds = %bb1069
54 br i1 false, label %cond_next1207, label %cond_true1150
55
56 cond_true1150: ; preds = %cond_next1131
57 ret void
58
59 cond_next1207: ; preds = %cond_next1131
60 br i1 false, label %cond_next1219, label %cond_true1211
61
62 cond_true1211: ; preds = %cond_next1207
63 ret void
64
65 cond_next1219: ; preds = %cond_next1207
66 br i1 false, label %cond_true1223, label %cond_next1283
67
68 cond_true1223: ; preds = %cond_next1219
69 br i1 false, label %cond_true1254, label %cond_true1264
70
71 cond_true1254: ; preds = %cond_true1223
72 br i1 false, label %bb1567, label %cond_true1369.preheader
73
74 cond_true1264: ; preds = %cond_true1223
75 ret void
76
77 cond_next1283: ; preds = %cond_next1219
78 ret void
79
80 cond_true1369.preheader: ; preds = %cond_true1254
81 ret void
82
83 bb1567: ; preds = %cond_true1254
84 %tmp1591 = load i64* getelementptr inbounds (%struct.CHESS_POSITION* @search, i32 0, i32 4) ; [#uses=1]
85 %tmp1572 = tail call fastcc i32 @FirstOne() ; [#uses=1]
86 %tmp1594 = load i32* undef ; [#uses=1]
87 %tmp1594.upgrd.5 = trunc i32 %tmp1594 to i8 ; [#uses=1]
88 %shift.upgrd.6 = zext i8 %tmp1594.upgrd.5 to i64 ; [#uses=1]
89 %tmp1595 = lshr i64 %tmp1591, %shift.upgrd.6 ; [#uses=1]
90 %tmp1595.upgrd.7 = trunc i64 %tmp1595 to i32 ; [#uses=1]
91 %tmp1596 = and i32 %tmp1595.upgrd.7, 255 ; [#uses=1]
92 %gep.upgrd.8 = zext i32 %tmp1596 to i64 ; [#uses=1]
93 %tmp1598 = getelementptr [64 x [256 x i32]]* @bishop_mobility_rr45, i32 0, i32 %tmp1572, i64 %gep.upgrd.8 ; [#uses=1]
94 %tmp1599 = load i32* %tmp1598 ; [#uses=1]
95 %tmp1602 = sub i32 0, %tmp1599 ; [#uses=1]
96 br i1 undef, label %cond_next1637, label %cond_true1607
97
98 cond_true1607: ; preds = %bb1567
99 ret void
100
101 cond_next1637: ; preds = %bb1567
102 %tmp1662 = sub i32 %tmp1602, 0 ; [#uses=0]
103 ret void
104 }