llvm.org GIT mirror llvm / a9d6f4a
[X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior. This also fixes a bug where negative immediates below -128 were not being reported as errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249989 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
5 changed file(s) with 15 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
717717 bool ParseDirectiveWord(unsigned Size, SMLoc L);
718718 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
719719
720 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
721720 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
722721
723722 /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
24002399 return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
24012400 }
24022401
2403 bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
2404 switch (Inst.getOpcode()) {
2405 default: return true;
2406 case X86::INT:
2407 X86Operand &Op = static_cast(*Ops[1]);
2408 assert(Op.isImm() && "expected immediate");
2409 int64_t Res;
2410 if (!Op.getImm()->evaluateAsAbsolute(Res) || Res > 255) {
2411 Error(Op.getStartLoc(), "interrupt vector must be in range [0-255]");
2412 return false;
2413 }
2414 return true;
2415 }
2416 llvm_unreachable("handle the instruction appropriately");
2417 }
2418
24192402 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
24202403 switch (Inst.getOpcode()) {
24212404 default: return false;
25782561 isParsingIntelSyntax())) {
25792562 default: llvm_unreachable("Unexpected match result!");
25802563 case Match_Success:
2581 if (!validateInstruction(Inst, Operands))
2582 return true;
2583
25842564 // Some instructions need post-processing to, for example, tweak which
25852565 // encoding is selected. Loop on it while changes happen so the
25862566 // individual transformations can chain off each other.
28242804 unsigned NumSuccessfulMatches =
28252805 std::count(std::begin(Match), std::end(Match), Match_Success);
28262806 if (NumSuccessfulMatches == 1) {
2827 if (!validateInstruction(Inst, Operands))
2828 return true;
2829
28302807 // Some instructions need post-processing to, for example, tweak which
28312808 // encoding is selected. Loop on it while changes happen so the individual
28322809 // transformations can chain off each other.
4343
4444 let SchedRW = [WriteSystem] in {
4545
46 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
46 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
4747 [(int_x86_int imm:$trap)], IIC_INT>;
4848
4949
1010 ret void
1111 }
1212
13 ; CHECK: int $-128
13 ; CHECK: int $128
1414 ; CHECK: ret
1515 define void @primitive_int128 () {
1616 bb.entry:
11
22 .text
33 int $65535
4 # CHECK: error: interrupt vector must be in range [0-255]
4 # CHECK: error: invalid operand for instruction
55 # CHECK: int $65535
66 # CHECK: ^
7
8 int $-129
9 # CHECK: error: invalid operand for instruction
10 # CHECK: int $-129
11 # CHECK: ^
22
33 .text
44 int 65535
5 # CHECK: error: interrupt vector must be in range [0-255]
5 # CHECK: error: invalid operand for instruction
66 # CHECK: int 65535
77 # CHECK: ^
88
9 .text
10 int -129
11 # CHECK: error: invalid operand for instruction
12 # CHECK: int -129
13 # CHECK: ^
14