llvm.org GIT mirror llvm / a9a94ce
TableGen: fix operand counting for aliases TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208969 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 5 years ago
21 changed file(s) with 125 addition(s) and 244 deletion(s). Raw diff Collapse all Expand all
16661666 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm)>;
16671667 def : InstAlias(NAME#"Xri")
16681668 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm)>;
1669 def : InstAlias, $sh", (!cast(NAME#"Wrx")
1669 def : InstAlias$sh", (!cast(NAME#"Wrx")
16701670 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh)>;
1671 def : InstAlias, $sh", (!cast(NAME#"Xrx")
1671 def : InstAlias$sh", (!cast(NAME#"Xrx")
16721672 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh)>;
1673 def : InstAlias, $sh", (!cast(NAME#"Xrx64")
1673 def : InstAlias$sh", (!cast(NAME#"Xrx64")
16741674 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh)>;
1675 def : InstAlias, $sh", (!cast(NAME#"Wrs")
1675 def : InstAlias$sh", (!cast(NAME#"Wrs")
16761676 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh)>;
1677 def : InstAlias, $sh", (!cast(NAME#"Xrs")
1677 def : InstAlias$sh", (!cast(NAME#"Xrs")
16781678 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh)>;
16791679
16801680 // Compare shorthands
217217 MI->getOperand(2).isExpr()) {
218218 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
219219 << *MI->getOperand(2).getExpr();
220 return;
221 }
222
223 // FIXME: TableGen should be able to do all of these now.
224
225 // ANDS WZR, Wn, Wm{, lshift #imm} ==> TST Wn{, lshift #imm}
226 // ANDS XZR, Xn, Xm{, lshift #imm} ==> TST Xn{, lshift #imm}
227 if ((Opcode == ARM64::ANDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
228 (Opcode == ARM64::ANDSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
229 O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
230 printShiftedRegister(MI, 2, O);
231 return;
232 }
233
234 // ORN Wn, WZR, Wm{, lshift #imm} ==> MVN Wn, Wm{, lshift #imm}
235 // ORN Xn, XZR, Xm{, lshift #imm} ==> MVN Xn, Xm{, lshift #imm}
236 if ((Opcode == ARM64::ORNWrs && MI->getOperand(1).getReg() == ARM64::WZR) ||
237 (Opcode == ARM64::ORNXrs && MI->getOperand(1).getReg() == ARM64::XZR)) {
238 O << "\tmvn\t" << getRegisterName(MI->getOperand(0).getReg()) << ", ";
239 printShiftedRegister(MI, 2, O);
240 return;
241 }
242 // SUBS WZR, Wn, Wm{, lshift #imm} ==> CMP Wn, Wm{, lshift #imm}
243 // SUBS XZR, Xn, Xm{, lshift #imm} ==> CMP Xn, Xm{, lshift #imm}
244 if ((Opcode == ARM64::SUBSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
245 (Opcode == ARM64::SUBSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
246 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
247 printShiftedRegister(MI, 2, O);
248 return;
249 }
250 // SUBS XZR, Xn, Wm, uxtb #imm ==> CMP Xn, uxtb #imm
251 // SUBS WZR, Wn, Xm, uxtb #imm ==> CMP Wn, uxtb #imm
252 if ((Opcode == ARM64::SUBSXrx && MI->getOperand(0).getReg() == ARM64::XZR) ||
253 (Opcode == ARM64::SUBSWrx && MI->getOperand(0).getReg() == ARM64::WZR)) {
254 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
255 printExtendedRegister(MI, 2, O);
256 return;
257 }
258 // SUBS XZR, Xn, Xm, uxtx #imm ==> CMP Xn, uxtb #imm
259 if (Opcode == ARM64::SUBSXrx64 && MI->getOperand(0).getReg() == ARM64::XZR) {
260 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "
261 << getRegisterName(MI->getOperand(2).getReg());
262 printExtend(MI, 3, O);
263 return;
264 }
265
266 // ADDS WZR, Wn, Wm{, lshift #imm} ==> CMN Wn, Wm{, lshift #imm}
267 // ADDS XZR, Xn, Xm{, lshift #imm} ==> CMN Xn, Xm{, lshift #imm}
268 if ((Opcode == ARM64::ADDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
269 (Opcode == ARM64::ADDSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
270 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
271 printShiftedRegister(MI, 2, O);
272 return;
273 }
274 // ADDS XZR, Xn, Wm, uxtb #imm ==> CMN Xn, uxtb #imm
275 if (Opcode == ARM64::ADDSXrx && MI->getOperand(0).getReg() == ARM64::XZR) {
276 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
277 printExtendedRegister(MI, 2, O);
278 return;
279 }
280 // ADDS XZR, Xn, Xm, uxtx #imm ==> CMN Xn, uxtb #imm
281 if (Opcode == ARM64::ADDSXrx64 && MI->getOperand(0).getReg() == ARM64::XZR) {
282 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "
283 << getRegisterName(MI->getOperand(2).getReg());
284 printExtend(MI, 3, O);
285220 return;
286221 }
287222
1414 #include "Sparc.h"
1515 #include "llvm/MC/MCExpr.h"
1616 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCRegisterInfo.h"
1718 #include "llvm/MC/MCSymbol.h"
1819 #include "llvm/Support/raw_ostream.h"
1920 using namespace llvm;
None ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
1 ; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
0 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
1 ; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s
22
33 @var32 = global i32 0
44 @var64 = global i64 0
3535 %shift4a = shl i32 %lhs4a, 15
3636 %val4a = sub i32 0, %shift4a
3737 store volatile i32 %val4a, i32* @var32
38 ; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, lsl #15
39 ; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsl #15
38 ; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, lsl #15
4039
4140 %rhs5 = load volatile i64* @var64
4241 %shift5 = shl i64 %rhs5, 18
6766 %shift8a = shl i64 %lhs8a, 60
6867 %val8a = sub i64 0, %shift8a
6968 store volatile i64 %val8a, i64* @var64
70 ; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, lsl #60
71 ; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsl #60
69 ; CHECK: neg {{x[0-9]+}}, {{x[0-9]+}}, lsl #60
7270
7371 ret void
7472 ; CHECK: ret
10199 %shift4a = lshr i32 %lhs32, 15
102100 %val4a = sub i32 0, %shift4a
103101 store volatile i32 %val4a, i32* @var32
104 ; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, lsr #15
105 ; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsr #15
102 ; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, lsr #15
106103
107104 %shift5 = lshr i64 %rhs64, 18
108105 %val5 = add i64 %lhs64, %shift5
128125 %shift8a = lshr i64 %lhs64, 45
129126 %val8a = sub i64 0, %shift8a
130127 store volatile i64 %val8a, i64* @var64
131 ; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, lsr #45
132 ; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsr #45
128 ; CHECK: neg {{x[0-9]+}}, {{x[0-9]+}}, lsr #45
133129
134130 ret void
135131 ; CHECK: ret
162158 %shift4a = ashr i32 %lhs32, 15
163159 %val4a = sub i32 0, %shift4a
164160 store volatile i32 %val4a, i32* @var32
165 ; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, asr #15
166 ; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, asr #15
161 ; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, asr #15
167162
168163 %shift5 = ashr i64 %rhs64, 18
169164 %val5 = add i64 %lhs64, %shift5
189184 %shift8a = ashr i64 %lhs64, 45
190185 %val8a = sub i64 0, %shift8a
191186 store volatile i64 %val8a, i64* @var64
192 ; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, asr #45
193 ; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, asr #45
187 ; CHECK: neg {{x[0-9]+}}, {{x[0-9]+}}, asr #45
194188
195189 ret void
196190 ; CHECK: ret
251245 br i1 %tst1, label %t2, label %end
252246 ; Important that this isn't lowered to a cmn instruction because if %rhs32 ==
253247 ; 0 then the results will differ.
254 ; CHECK-AARCH64: neg [[RHS:w[0-9]+]], {{w[0-9]+}}, lsl #13
255 ; CHECK-ARM64: sub [[RHS:w[0-9]+]], wzr, {{w[0-9]+}}, lsl #13
248 ; CHECK: neg [[RHS:w[0-9]+]], {{w[0-9]+}}, lsl #13
256249 ; CHECK: cmp {{w[0-9]+}}, [[RHS]]
257250
258251 t2:
275268 %tst4 = icmp slt i64 %lhs64, %val4
276269 br i1 %tst4, label %t5, label %end
277270 ; Again, it's important that cmn isn't used here in case %rhs64 == 0.
278 ; CHECK-AARCH64: neg [[RHS:x[0-9]+]], {{x[0-9]+}}, lsl #43
279 ; CHECK-ARM64: sub [[RHS:x[0-9]+]], xzr, {{x[0-9]+}}, lsl #43
271 ; CHECK: neg [[RHS:x[0-9]+]], {{x[0-9]+}}, lsl #43
280272 ; CHECK: cmp {{x[0-9]+}}, [[RHS]]
281273
282274 t5:
155155 entry:
156156 ; CHECK-LABEL: t17:
157157 ; CHECK: sxth [[REG:x[0-9]+]], w0
158 ; CHECK: sub x0, xzr, [[REG]], lsl #32
158 ; CHECK: neg x0, [[REG]], lsl #32
159159 ; CHECK: ret
160160 %tmp16 = sext i16 %a to i64
161161 %tmp17 = mul i64 %tmp16, -4294967296
5959 define i8* @retaddr() nounwind readnone {
6060 entry:
6161 ;V8-LABEL: retaddr:
62 ;V8: or %g0, %o7, {{.+}}
62 ;V8: mov %o7, {{.+}}
6363
6464 ;V9-LABEL: retaddr:
65 ;V9: or %g0, %o7, {{.+}}
65 ;V9: mov %o7, {{.+}}
6666
6767 ;SPARC64-LABEL: retaddr
68 ;SPARC64: or %g0, %o7, {{.+}}
68 ;SPARC64: mov %o7, {{.+}}
6969
7070 %0 = tail call i8* @llvm.returnaddress(i32 0)
7171 ret i8* %0
5959 ;CHECK: !NO_APP
6060 ;CHECK-NEXT: cmp
6161 ;CHECK-NEXT: bg
62 ;CHECK-NEXT: or
62 ;CHECK-NEXT: mov
6363 tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
6464 %0 = icmp slt i32 %a, 0
6565 br i1 %0, label %bb, label %bb1
4343 ; CHECK: sra %i0, 0, [[R:%[gilo][0-7]]]
4444 ; CHECK: stx [[R]], [%sp+2223]
4545 ; Use %o0-%o5 for outgoing arguments
46 ; CHECK: or %g0, 5, %o5
46 ; CHECK: mov 5, %o5
4747 ; CHECK: call intarg
4848 ; CHECK-NOT: add %sp
4949 ; CHECK: restore
207207
208208 ; CHECK: call_inreg_if
209209 ; CHECK: fmovs %f3, %f0
210 ; CHECK: or %g0, %i2, %o0
210 ; CHECK: mov %i2, %o0
211211 ; CHECK: call inreg_if
212212 define void @call_inreg_if(i32* %p, float %f3, i32 %i2) {
213213 %x = call i32 @inreg_if(float %f3, i32 %i2)
11 ; RUN: llc < %s -march=sparcv9 -mattr=+popc | FileCheck %s -check-prefix=OPT
22
33 ; CHECK-LABEL: ret2:
4 ; CHECK: or %g0, %i1, %i0
4 ; CHECK: mov %i1, %i0
55
66 ; OPT-LABEL: ret2:
77 ; OPT: retl
8 ; OPT: or %g0, %o1, %o0
8 ; OPT: mov %o1, %o0
99 define i64 @ret2(i64 %a, i64 %b) {
1010 ret i64 %b
1111 }
3838 ; restore %g0, %g0, %o0
3939 ;
4040 ; CHECK: ret_imm0
41 ; CHECK: or %g0, 0, %i0
41 ; CHECK: mov 0, %i0
4242
4343 ; OPT: ret_imm0
4444 ; OPT: retl
45 ; OPT: or %g0, 0, %o0
45 ; OPT: mov 0, %o0
4646 define i64 @ret_imm0() {
4747 ret i64 0
4848 }
4949
5050 ; CHECK: ret_simm13
51 ; CHECK: or %g0, -4096, %i0
51 ; CHECK: mov -4096, %i0
5252
5353 ; OPT: ret_simm13
5454 ; OPT: retl
55 ; OPT: or %g0, -4096, %o0
55 ; OPT: mov -4096, %o0
5656 define i64 @ret_simm13() {
5757 ret i64 -4096
5858 }
111111
112112 ; CHECK-LABEL: setcc_resultty
113113 ; CHECK-DAG: srax %i0, 63, %o0
114 ; CHECK-DAG: or %g0, %i0, %o1
115 ; CHECK-DAG: or %g0, 0, %o2
116 ; CHECK-DAG: or %g0, 32, %o3
114 ; CHECK-DAG: mov %i0, %o1
115 ; CHECK-DAG: mov 0, %o2
116 ; CHECK-DAG: mov 32, %o3
117117 ; CHECK-DAG: call __multi3
118118 ; CHECK: cmp
119119 ; CHECK: movne %xcc, 1, [[R:%[gilo][0-7]]]
3232 }
3333
3434 ; CHECK-LABEL: test_cmpxchg_i32
35 ; CHECK: or %g0, 123, [[R:%[gilo][0-7]]]
35 ; CHECK: mov 123, [[R:%[gilo][0-7]]]
3636 ; CHECK: cas [%o1], %o0, [[R]]
3737
3838 define i32 @test_cmpxchg_i32(i32 %a, i32* %ptr) {
4242 }
4343
4444 ; CHECK-LABEL: test_cmpxchg_i64
45 ; CHECK: or %g0, 123, [[R:%[gilo][0-7]]]
45 ; CHECK: mov 123, [[R:%[gilo][0-7]]]
4646 ; CHECK: casx [%o1], %o0, [[R]]
4747
4848 define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
5252 }
5353
5454 ; CHECK-LABEL: test_swap_i32
55 ; CHECK: or %g0, 42, [[R:%[gilo][0-7]]]
55 ; CHECK: mov 42, [[R:%[gilo][0-7]]]
5656 ; CHECK: swap [%o1], [[R]]
5757
5858 define i32 @test_swap_i32(i32 %a, i32* %ptr) {
1010
1111 ; CHECK-LABEL: return_int_const:
1212 ; CHECK: retl
13 ; CHECK-NEXT: or %g0, 1729, %o0
13 ; CHECK-NEXT: mov 1729, %o0
1414 define i32 @return_int_const() {
1515 entry:
1616 ret i32 1729
5757
5858 ; CHECK-LABEL: leaf_proc_with_local_array:
5959 ; CHECK: add %sp, -104, %sp
60 ; CHECK: or %g0, 1, [[R1:%[go][0-7]]]
60 ; CHECK: mov 1, [[R1:%[go][0-7]]]
6161 ; CHECK: st [[R1]], [%sp+96]
62 ; CHECK: or %g0, 2, [[R2:%[go][0-7]]]
62 ; CHECK: mov 2, [[R2:%[go][0-7]]]
6363 ; CHECK: st [[R2]], [%sp+100]
6464 ; CHECK: ld {{.+}}, %o0
6565 ; CHECK: retl
11
22 ; CHECK-LABEL: test
33 ; CHECK: srl %i1, 0, %o2
4 ; CHECK-NEXT: or %g0, %i2, %o0
4 ; CHECK-NEXT: mov %i2, %o0
55 ; CHECK-NEXT: call __ashlti3
6 ; CHECK-NEXT: or %g0, %i3, %o1
7 ; CHECK-NEXT: or %g0, %o0, %i0
6 ; CHECK-NEXT: mov %i3, %o1
7 ; CHECK-NEXT: mov %o0, %i0
88
99 define i128 @test(i128 %a, i128 %b) {
1010 entry:
2626 // CHECK: add x2, x4, w5, uxtb // encoding: [0x82,0x00,0x25,0x8b]
2727 // CHECK: add x20, sp, w19, uxth // encoding: [0xf4,0x23,0x33,0x8b]
2828 // CHECK: add x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0x8b]
29 // CHECK: add x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0x8b]
29 // CHECK-AARCH64: add x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0x8b]
30 // CHECK-ARM64: add x20, x3, x13 // encoding: [0x74,0x60,0x2d,0x8b]
3031 // CHECK: add x17, x25, w20, sxtb // encoding: [0x31,0x83,0x34,0x8b]
3132 // CHECK: add x18, x13, w19, sxth // encoding: [0xb2,0xa1,0x33,0x8b]
3233 // CHECK: add sp, x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x8b]
4344 add w2, w3, w5, sxtx
4445 // CHECK: add w2, w5, w7, uxtb // encoding: [0xa2,0x00,0x27,0x0b]
4546 // CHECK: add w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x0b]
46 // CHECK: add w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x0b]
47 // CHECK-AARCH64: add w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x0b]
48 // CHECK-ARM64: add w30, w29, wzr // encoding: [0xbe,0x43,0x3f,0x0b]
4749 // CHECK: add w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x0b]
4850 // CHECK: add w2, w5, w1, sxtb // encoding: [0xa2,0x80,0x21,0x0b]
4951 // CHECK: add w26, w17, w19, sxth // encoding: [0x3a,0xa2,0x33,0x0b]
7274 // CHECK: sub x2, x4, w5, uxtb #2 // encoding: [0x82,0x08,0x25,0xcb]
7375 // CHECK: sub x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xcb]
7476 // CHECK: sub x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xcb]
75 // CHECK: sub x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xcb]
77 // CHECK-AARCH64: sub x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xcb]
78 // CHECK-ARM64: sub x20, x3, x13 // encoding: [0x74,0x60,0x2d,0xcb]
7679 // CHECK: sub x17, x25, w20, sxtb // encoding: [0x31,0x83,0x34,0xcb]
7780 // CHECK: sub x18, x13, w19, sxth // encoding: [0xb2,0xa1,0x33,0xcb]
7881 // CHECK: sub sp, x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xcb]
8891 sub w2, w3, w5, sxtx
8992 // CHECK: sub w2, w5, w7, uxtb // encoding: [0xa2,0x00,0x27,0x4b]
9093 // CHECK: sub w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x4b]
91 // CHECK: sub w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x4b]
94 // CHECK-AARCH64: sub w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x4b]
95 // CHECK-ARM64: sub w30, w29, wzr // encoding: [0xbe,0x43,0x3f,0x4b]
9296 // CHECK: sub w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x4b]
9397 // CHECK: sub w2, w5, w1, sxtb // encoding: [0xa2,0x80,0x21,0x4b]
9498 // CHECK: sub w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x4b]
107111 // CHECK: adds x2, x4, w5, uxtb #2 // encoding: [0x82,0x08,0x25,0xab]
108112 // CHECK: adds x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xab]
109113 // CHECK: adds x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xab]
110 // CHECK: adds x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xab]
114 // CHECK-AARCH64: adds x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xab]
115 // CHECK-ARM64: adds x20, x3, x13 // encoding: [0x74,0x60,0x2d,0xab]
111116 // CHECK: {{adds xzr,|cmn}} x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xab]
112117 // CHECK: adds x18, sp, w19, sxth // encoding: [0xf2,0xa3,0x33,0xab]
113118 // CHECK: {{adds xzr,|cmn}} x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xab]
123128 adds w2, w3, w5, sxtx
124129 // CHECK: adds w2, w5, w7, uxtb // encoding: [0xa2,0x00,0x27,0x2b]
125130 // CHECK: adds w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x2b]
126 // CHECK: adds w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x2b]
131 // CHECK-AARCH64: adds w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x2b]
132 // CHECK-ARM64: adds w30, w29, wzr // encoding: [0xbe,0x43,0x3f,0x2b]
127133 // CHECK: adds w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x2b]
128134 // CHECK: adds w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x2b]
129135 // CHECK: adds w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x2b]
130 // CHECK: adds wzr, w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b]
136 // CHECK-AARCH64: adds wzr, w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b]
137 // CHECK-ARM64: cmn w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b]
131138 // CHECK: adds w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x2b]
132139
133140 // subs
142149 // CHECK: subs x2, x4, w5, uxtb #2 // encoding: [0x82,0x08,0x25,0xeb]
143150 // CHECK: subs x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xeb]
144151 // CHECK: subs x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xeb]
145 // CHECK: subs x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xeb]
152 // CHECK-AARCH64: subs x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xeb]
153 // CHECK-ARM64: subs x20, x3, x13 // encoding: [0x74,0x60,0x2d,0xeb]
146154 // CHECK: {{subs xzr,|cmp}} x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xeb]
147155 // CHECK: subs x18, sp, w19, sxth // encoding: [0xf2,0xa3,0x33,0xeb]
148156 // CHECK: {{subs xzr,|cmp}} x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xeb]
158166 subs w2, w3, w5, sxtx
159167 // CHECK: subs w2, w5, w7, uxtb // encoding: [0xa2,0x00,0x27,0x6b]
160168 // CHECK: subs w21, w15, w17, uxth // encoding: [0xf5,0x21,0x31,0x6b]
161 // CHECK: subs w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x6b]
169 // CHECK-AARCH64: subs w30, w29, wzr, uxtw // encoding: [0xbe,0x43,0x3f,0x6b]
170 // CHECK-ARM64: subs w30, w29, wzr // encoding: [0xbe,0x43,0x3f,0x6b]
162171 // CHECK: subs w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x6b]
163172 // CHECK: subs w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x6b]
164173 // CHECK: subs w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x6b]
255264 // CHECK: sub sp, x3, x7, lsl #4 // encoding: [0x7f,0x70,0x27,0xcb]
256265 // CHECK: add w2, wsp, w3, lsl #1 // encoding: [0xe2,0x47,0x23,0x0b]
257266 // CHECK: cmp wsp, w9 // encoding: [0xff,0x43,0x29,0x6b]
258 // CHECK: adds wzr, wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b]
267 // CHECK-AARCH64: adds wzr, wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b]
268 // CHECK-ARM64: cmn wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b]
259269 // CHECK: subs x3, sp, x9, lsl #2 // encoding: [0xe3,0x6b,0x29,0xeb]
260270
261271 //------------------------------------------------------------------------------
734744 // CHECK-AARCH64: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
735745
736746 // CHECK-ARM64: neg w28, w27 // encoding: [0xfc,0x03,0x1b,0x4b]
737 // CHECK-ARM64: sub w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
738 // CHECK-ARM64: sub w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
747 // CHECK-ARM64: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
748 // CHECK-ARM64: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
739749
740750 neg w22, w21, lsr #0
741751 neg w20, w19, lsr #1
742752 neg w18, w17, lsr #31
743 // CHECK-AARCH64: neg w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
744 // CHECK-AARCH64: neg w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
745 // CHECK-AARCH64: neg w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
746
747 // CHECK-ARM64: sub w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
748 // CHECK-ARM64: sub w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
749 // CHECK-ARM64: sub w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
753 // CHECK: neg w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
754 // CHECK: neg w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
755 // CHECK: neg w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
750756
751757 neg w16, w15, asr #0
752758 neg w14, w13, asr #12
753759 neg w12, w11, asr #31
754 // CHECK-AARCH64: neg w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
755 // CHECK-AARCH64: neg w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
756 // CHECK-AARCH64: neg w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
757
758 // CHECK-ARM64: sub w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
759 // CHECK-ARM64: sub w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
760 // CHECK-ARM64: sub w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
760 // CHECK: neg w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
761 // CHECK: neg w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
762 // CHECK: neg w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
761763
762764 neg x29, x30
763765 neg x30, xzr
777779 // CHECK-AARCH64: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
778780
779781 // CHECK-ARM64: neg x28, x27 // encoding: [0xfc,0x03,0x1b,0xcb]
780 // CHECK-ARM64: sub x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
781 // CHECK-ARM64: sub x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
782 // CHECK-ARM64: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
783 // CHECK-ARM64: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
782784
783785 neg x22, x21, lsr #0
784786 neg x20, x19, lsr #1
785787 neg x18, x17, lsr #31
786 // CHECK-AARCH64: neg x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
787 // CHECK-AARCH64: neg x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
788 // CHECK-AARCH64: neg x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
789
790 // CHECK-ARM64: sub x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
791 // CHECK-ARM64: sub x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
792 // CHECK-ARM64: sub x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
788 // CHECK: neg x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
789 // CHECK: neg x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
790 // CHECK: neg x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
793791
794792 neg x16, x15, asr #0
795793 neg x14, x13, asr #12
796794 neg x12, x11, asr #31
797 // CHECK-AARCH64: neg x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
798 // CHECK-AARCH64: neg x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
799 // CHECK-AARCH64: neg x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
800
801 // CHECK-ARM64: sub x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
802 // CHECK-ARM64: sub x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
803 // CHECK-ARM64: sub x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
795 // CHECK: neg x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
796 // CHECK: neg x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
797 // CHECK: neg x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
804798
805799 negs w29, w30
806800 negs w30, wzr
820814 // CHECK-AARCH64: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
821815
822816 // CHECK-ARM64: negs w28, w27 // encoding: [0xfc,0x03,0x1b,0x6b]
823 // CHECK-ARM64: subs w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
824 // CHECK-ARM64: subs w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
817 // CHECK-ARM64: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
818 // CHECK-ARM64: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
825819
826820 negs w22, w21, lsr #0
827821 negs w20, w19, lsr #1
828822 negs w18, w17, lsr #31
829 // CHECK-AARCH64: negs w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
830 // CHECK-AARCH64: negs w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
831 // CHECK-AARCH64: negs w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
832
833 // CHECK-ARM64: subs w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
834 // CHECK-ARM64: subs w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
835 // CHECK-ARM64: subs w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
823 // CHECK: negs w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
824 // CHECK: negs w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
825 // CHECK: negs w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
836826
837827 negs w16, w15, asr #0
838828 negs w14, w13, asr #12
839829 negs w12, w11, asr #31
840 // CHECK-AARCH64: negs w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
841 // CHECK-AARCH64: negs w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
842 // CHECK-AARCH64: negs w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
843
844 // CHECK-ARM64: subs w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
845 // CHECK-ARM64: subs w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
846 // CHECK-ARM64: subs w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
830 // CHECK: negs w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
831 // CHECK: negs w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
832 // CHECK: negs w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
847833
848834 negs x29, x30
849835 negs x30, xzr
863849 // CHECK-AARCH64: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
864850
865851 // CHECK-ARM64: negs x28, x27 // encoding: [0xfc,0x03,0x1b,0xeb]
866 // CHECK-ARM64: subs x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
867 // CHECK-ARM64: subs x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
852 // CHECK-ARM64: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
853 // CHECK-ARM64: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
868854
869855 negs x22, x21, lsr #0
870856 negs x20, x19, lsr #1
871857 negs x18, x17, lsr #31
872 // CHECK-AARCH64: negs x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
873 // CHECK-AARCH64: negs x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
874 // CHECK-AARCH64: negs x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
875
876 // CHECK-ARM64: subs x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
877 // CHECK-ARM64: subs x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
878 // CHECK-ARM64: subs x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
858 // CHECK: negs x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
859 // CHECK: negs x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
860 // CHECK: negs x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
879861
880862 negs x16, x15, asr #0
881863 negs x14, x13, asr #12
882864 negs x12, x11, asr #31
883 // CHECK-AARCH64: negs x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
884 // CHECK-AARCH64: negs x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
885 // CHECK-AARCH64: negs x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
886
887 // CHECK-ARM64: subs x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
888 // CHECK-ARM64: subs x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
889 // CHECK-ARM64: subs x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
865 // CHECK: negs x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
866 // CHECK: negs x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
867 // CHECK: negs x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
890868
891869 //------------------------------------------------------------------------------
892870 // Add-sub (shifted register)
112112 neg w0, w1
113113 ; CHECK: neg w0, w1
114114 neg w0, w1, lsl #1
115 ; CHECK: sub w0, wzr, w1, lsl #1
115 ; CHECK: neg w0, w1, lsl #1
116116 neg x0, x1
117117 ; CHECK: neg x0, x1
118118 neg x0, x1, asr #1
119 ; CHECK: sub x0, xzr, x1, asr #1
119 ; CHECK: neg x0, x1, asr #1
120120 negs w0, w1
121121 ; CHECK: negs w0, w1
122122 negs w0, w1, lsl #1
123 ; CHECK: subs w0, wzr, w1, lsl #1
123 ; CHECK: negs w0, w1, lsl #1
124124 negs x0, x1
125125 ; CHECK: negs x0, x1
126126 negs x0, x1, asr #1
127 ; CHECK: subs x0, xzr, x1, asr #1
127 ; CHECK: negs x0, x1, asr #1
128128
129129 ;-----------------------------------------------------------------------------
130130 ; MOV aliases
177177
178178 ; CHECK: add w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x0b]
179179 ; CHECK: add w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x0b]
180 ; CHECK: add w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x0b]
180 ; CHECK: add w1, w2, w3 ; encoding: [0x41,0x40,0x23,0x0b]
181181 ; CHECK: add w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x0b]
182182 ; CHECK: add w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x0b]
183183 ; CHECK: add w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x0b]
221221
222222 ; CHECK: sub w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x4b]
223223 ; CHECK: sub w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x4b]
224 ; CHECK: sub w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x4b]
224 ; CHECK: sub w1, w2, w3 ; encoding: [0x41,0x40,0x23,0x4b]
225225 ; CHECK: sub w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x4b]
226226 ; CHECK: sub w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x4b]
227227 ; CHECK: sub w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x4b]
265265
266266 ; CHECK: adds w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x2b]
267267 ; CHECK: adds w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x2b]
268 ; CHECK: adds w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x2b]
268 ; CHECK: adds w1, w2, w3 ; encoding: [0x41,0x40,0x23,0x2b]
269269 ; CHECK: adds w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x2b]
270270 ; CHECK: adds w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x2b]
271271 ; CHECK: adds w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x2b]
296296
297297 ; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b]
298298 ; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b]
299 ; CHECK: adds wzr, wsp, w3, lsl #4 ; encoding: [0xff,0x53,0x23,0x2b]
299 ; CHECK: cmn wsp, w3, lsl #4 ; encoding: [0xff,0x53,0x23,0x2b]
300300
301301 subs w1, w2, w3, uxtb
302302 subs w1, w2, w3, uxth
309309
310310 ; CHECK: subs w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x6b]
311311 ; CHECK: subs w1, w2, w3, uxth ; encoding: [0x41,0x20,0x23,0x6b]
312 ; CHECK: subs w1, w2, w3, uxtw ; encoding: [0x41,0x40,0x23,0x6b]
312 ; CHECK: subs w1, w2, w3 ; encoding: [0x41,0x40,0x23,0x6b]
313313 ; CHECK: subs w1, w2, w3, uxtx ; encoding: [0x41,0x60,0x23,0x6b]
314314 ; CHECK: subs w1, w2, w3, sxtb ; encoding: [0x41,0x80,0x23,0x6b]
315315 ; CHECK: subs w1, w2, w3, sxth ; encoding: [0x41,0xa0,0x23,0x6b]
171171
172172 # CHECK: add w1, w2, w3, uxtb
173173 # CHECK: add w1, w2, w3, uxth
174 # CHECK: add w1, w2, w3, uxtw
174 # CHECK: add w1, w2, w3
175175 # CHECK: add w1, w2, w3, uxtx
176176 # CHECK: add w1, w2, w3, sxtb
177177 # CHECK: add w1, w2, w3, sxth
213213
214214 # CHECK: sub w1, w2, w3, uxtb
215215 # CHECK: sub w1, w2, w3, uxth
216 # CHECK: sub w1, w2, w3, uxtw
216 # CHECK: sub w1, w2, w3
217217 # CHECK: sub w1, w2, w3, uxtx
218218 # CHECK: sub w1, w2, w3, sxtb
219219 # CHECK: sub w1, w2, w3, sxth
255255
256256 # CHECK: adds w1, w2, w3, uxtb
257257 # CHECK: adds w1, w2, w3, uxth
258 # CHECK: adds w1, w2, w3, uxtw
258 # CHECK: adds w1, w2, w3
259259 # CHECK: adds w1, w2, w3, uxtx
260260 # CHECK: adds w1, w2, w3, sxtb
261261 # CHECK: adds w1, w2, w3, sxth
293293
294294 # CHECK: subs w1, w2, w3, uxtb
295295 # CHECK: subs w1, w2, w3, uxth
296 # CHECK: subs w1, w2, w3, uxtw
296 # CHECK: subs w1, w2, w3
297297 # CHECK: subs w1, w2, w3, uxtx
298298 # CHECK: subs w1, w2, w3, sxtb
299299 # CHECK: subs w1, w2, w3, sxth
119119 # CHECK: fdivq %f0, %f4, %f8
120120 0x91 0xa0 0x09 0xe4
121121
122 # CHECK: fcmps %fcc0, %f0, %f4
122 # CHECK: fcmps %f0, %f4
123123 0x81 0xa8 0x0a 0x24
124124
125 # CHECK: fcmpd %fcc0, %f0, %f4
125 # CHECK: fcmpd %f0, %f4
126126 0x81 0xa8 0x0a 0x44
127127
128 # CHECK: fcmpq %fcc0, %f0, %f4
128 # CHECK: fcmpq %f0, %f4
129129 0x81 0xa8 0x0a 0x64
130130
131131 # CHECK: fxtos %f0, %f4
6969 ! CHECK: subxcc %g1, %g2, %g3 ! encoding: [0x86,0xe0,0x40,0x02]
7070 subxcc %g1, %g2, %g3
7171
72 ! CHECK: or %g0, %g1, %g3 ! encoding: [0x86,0x10,0x00,0x01]
72 ! CHECK: mov %g1, %g3 ! encoding: [0x86,0x10,0x00,0x01]
7373 mov %g1, %g3
7474
75 ! CHECK: or %g0, 255, %g3 ! encoding: [0x86,0x10,0x20,0xff]
75 ! CHECK: mov 255, %g3 ! encoding: [0x86,0x10,0x20,0xff]
7676 mov 0xff, %g3
7777
7878 ! CHECK: restore ! encoding: [0x81,0xe8,0x00,0x00]
9595 fdivd %f0, %f4, %f8
9696 fdivq %f0, %f4, %f8
9797
98 ! CHECK: fcmps %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x24]
99 ! CHECK: fcmpd %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x44]
100 ! CHECK: fcmpq %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x64]
98 ! CHECK: fcmps %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x24]
99 ! CHECK: fcmpd %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x44]
100 ! CHECK: fcmpq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x64]
101101 fcmps %f0, %f4
102102 fcmpd %f0, %f4
103103 fcmpq %f0, %f4
104104
105 ! CHECK: fcmpes %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]
106 ! CHECK: fcmped %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]
107 ! CHECK: fcmpeq %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]
105 ! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4]
106 ! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4]
107 ! CHECK: fcmpeq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4]
108108 fcmpes %f0, %f4
109109 fcmped %f0, %f4
110110 fcmpeq %f0, %f4
741741
742742 } // end anonymous namespace
743743
744 static unsigned CountNumOperands(StringRef AsmString) {
745 unsigned NumOps = 0;
746 std::pair ASM = AsmString.split(' ');
747
748 while (!ASM.second.empty()) {
749 ++NumOps;
750 ASM = ASM.second.split(' ');
751 }
752
753 return NumOps;
754 }
755
756 static unsigned CountResultNumOperands(StringRef AsmString) {
757 unsigned NumOps = 0;
758 std::pair ASM = AsmString.split('\t');
759
760 if (!ASM.second.empty()) {
761 size_t I = ASM.second.find('{');
762 StringRef Str = ASM.second;
763 if (I != StringRef::npos)
764 Str = ASM.second.substr(I, ASM.second.find('|', I));
765
766 ASM = Str.split(' ');
767
768 do {
769 ++NumOps;
770 ASM = ASM.second.split(' ');
771 } while (!ASM.second.empty());
772 }
773
774 return NumOps;
744 static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
745 std::string FlatAsmString =
746 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant);
747 AsmString = FlatAsmString;
748
749 return AsmString.count(' ') + AsmString.count('\t');
775750 }
776751
777752 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
817792 const CodeGenInstAlias *CGA = *II;
818793 unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
819794 unsigned NumResultOps =
820 CountResultNumOperands(CGA->ResultInst->AsmString);
795 CountNumOperands(CGA->ResultInst->AsmString, Variant);
821796
822797 // Don't emit the alias if it has more operands than what it's aliasing.
823 if (NumResultOps < CountNumOperands(CGA->AsmString))
798 if (NumResultOps < CountNumOperands(CGA->AsmString, Variant))
824799 continue;
825800
826801 IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),