llvm.org GIT mirror llvm / a9a568a
Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support for AsmPrinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155982 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
5 changed file(s) with 104 addition(s) and 36 deletion(s). Raw diff Collapse all Expand all
9595 case X86::PSHUFHWmi:
9696 case X86::VPSHUFHWmi:
9797 DestName = getRegName(MI->getOperand(0).getReg());
98 DecodePSHUFHWMask(MI->getOperand(MI->getNumOperands()-1).getImm(),
98 DecodePSHUFHWMask(MVT::v8i16,
99 MI->getOperand(MI->getNumOperands()-1).getImm(),
100 ShuffleMask);
101 break;
102 case X86::VPSHUFHWYri:
103 Src1Name = getRegName(MI->getOperand(1).getReg());
104 // FALL THROUGH.
105 case X86::VPSHUFHWYmi:
106 DestName = getRegName(MI->getOperand(0).getReg());
107 DecodePSHUFHWMask(MVT::v16i16,
108 MI->getOperand(MI->getNumOperands()-1).getImm(),
99109 ShuffleMask);
100110 break;
101111 case X86::PSHUFLWri:
105115 case X86::PSHUFLWmi:
106116 case X86::VPSHUFLWmi:
107117 DestName = getRegName(MI->getOperand(0).getReg());
108 DecodePSHUFLWMask(MI->getOperand(MI->getNumOperands()-1).getImm(),
118 DecodePSHUFLWMask(MVT::v8i16,
119 MI->getOperand(MI->getNumOperands()-1).getImm(),
120 ShuffleMask);
121 break;
122 case X86::VPSHUFLWYri:
123 Src1Name = getRegName(MI->getOperand(1).getReg());
124 // FALL THROUGH.
125 case X86::VPSHUFLWYmi:
126 DestName = getRegName(MI->getOperand(0).getReg());
127 DecodePSHUFLWMask(MVT::v16i16,
128 MI->getOperand(MI->getNumOperands()-1).getImm(),
109129 ShuffleMask);
110130 break;
111131
6969 unsigned NumLanes = VT.getSizeInBits() / 128;
7070 unsigned NumLaneElts = NumElts / NumLanes;
7171
72 int NewImm = Imm;
72 unsigned NewImm = Imm;
7373 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
7474 for (unsigned i = 0; i != NumLaneElts; ++i) {
7575 ShuffleMask.push_back(NewImm % NumLaneElts + l);
7979 }
8080 }
8181
82 void DecodePSHUFHWMask(unsigned Imm, SmallVectorImpl &ShuffleMask) {
83 ShuffleMask.push_back(0);
84 ShuffleMask.push_back(1);
85 ShuffleMask.push_back(2);
86 ShuffleMask.push_back(3);
87 for (unsigned i = 0; i != 4; ++i) {
88 ShuffleMask.push_back(4+(Imm & 3));
89 Imm >>= 2;
82 void DecodePSHUFHWMask(EVT VT, unsigned Imm,
83 SmallVectorImpl &ShuffleMask) {
84 unsigned NumLanes = VT.getSizeInBits() / 128;
85 unsigned NumElts = 8 * NumLanes;
86
87 for (unsigned l = 0; l != NumElts; l += 8) {
88 unsigned NewImm = Imm;
89 for (unsigned i = 0, e = 4; i != e; ++i) {
90 ShuffleMask.push_back(l + i);
91 }
92 for (unsigned i = 4, e = 8; i != e; ++i) {
93 ShuffleMask.push_back(l + 4 + (NewImm & 3));
94 NewImm >>= 2;
95 }
9096 }
9197 }
9298
93 void DecodePSHUFLWMask(unsigned Imm, SmallVectorImpl &ShuffleMask) {
94 for (unsigned i = 0; i != 4; ++i) {
95 ShuffleMask.push_back((Imm & 3));
96 Imm >>= 2;
99 void DecodePSHUFLWMask(EVT VT, unsigned Imm,
100 SmallVectorImpl &ShuffleMask) {
101 unsigned NumLanes = VT.getSizeInBits() / 128;
102 unsigned NumElts = 8 * NumLanes;
103
104 for (unsigned l = 0; l != NumElts; l += 8) {
105 unsigned NewImm = Imm;
106 for (unsigned i = 0, e = 4; i != e; ++i) {
107 ShuffleMask.push_back(l + (NewImm & 3));
108 NewImm >>= 2;
109 }
110 for (unsigned i = 4, e = 8; i != e; ++i) {
111 ShuffleMask.push_back(l + i);
112 }
97113 }
98 ShuffleMask.push_back(4);
99 ShuffleMask.push_back(5);
100 ShuffleMask.push_back(6);
101 ShuffleMask.push_back(7);
102114 }
103115
104116 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
110122 unsigned NumLanes = VT.getSizeInBits() / 128;
111123 unsigned NumLaneElts = NumElts / NumLanes;
112124
113 int NewImm = Imm;
125 unsigned NewImm = Imm;
114126 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
115127 // Part that reads from dest.
116128 for (unsigned i = 0; i != NumLaneElts/2; ++i) {
175187 unsigned FstHalfBegin = (Imm & 0x3) * HalfSize;
176188 unsigned SndHalfBegin = ((Imm >> 4) & 0x3) * HalfSize;
177189
178 for (int i = FstHalfBegin, e = FstHalfBegin+HalfSize; i != e; ++i)
190 for (unsigned i = FstHalfBegin, e = FstHalfBegin+HalfSize; i != e; ++i)
179191 ShuffleMask.push_back(i);
180 for (int i = SndHalfBegin, e = SndHalfBegin+HalfSize; i != e; ++i)
192 for (unsigned i = SndHalfBegin, e = SndHalfBegin+HalfSize; i != e; ++i)
181193 ShuffleMask.push_back(i);
182194 }
183195
3636
3737 void DecodePSHUFMask(EVT VT, unsigned Imm, SmallVectorImpl &ShuffleMask);
3838
39 void DecodePSHUFHWMask(unsigned Imm, SmallVectorImpl &ShuffleMask);
39 void DecodePSHUFHWMask(EVT VT, unsigned Imm, SmallVectorImpl &ShuffleMask);
4040
41 void DecodePSHUFLWMask(unsigned Imm, SmallVectorImpl &ShuffleMask);
41 void DecodePSHUFLWMask(EVT, unsigned Imm, SmallVectorImpl &ShuffleMask);
4242
4343 /// DecodeSHUFPMask - This decodes the shuffle masks for shufp*. VT indicates
4444 /// the type of the vector allowing it to handle different datatypes and vector
31953195
31963196 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
31973197 /// is suitable for input to PSHUFHW.
3198 static bool isPSHUFHWMask(ArrayRef Mask, EVT VT) {
3199 if (VT != MVT::v8i16)
3198 static bool isPSHUFHWMask(ArrayRef Mask, EVT VT, bool HasAVX2) {
3199 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
32003200 return false;
32013201
32023202 // Lower quadword copied in order or undef.
32053205
32063206 // Upper quadword shuffled.
32073207 for (unsigned i = 4; i != 8; ++i)
3208 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3208 if (!isUndefOrInRange(Mask[i], 4, 8))
32093209 return false;
3210
3211 if (VT == MVT::v16i16) {
3212 // Lower quadword copied in order or undef.
3213 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3214 return false;
3215
3216 // Upper quadword shuffled.
3217 for (unsigned i = 12; i != 16; ++i)
3218 if (!isUndefOrInRange(Mask[i], 12, 16))
3219 return false;
3220 }
32103221
32113222 return true;
32123223 }
32133224
32143225 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
32153226 /// is suitable for input to PSHUFLW.
3216 static bool isPSHUFLWMask(ArrayRef Mask, EVT VT) {
3217 if (VT != MVT::v8i16)
3227 static bool isPSHUFLWMask(ArrayRef Mask, EVT VT, bool HasAVX2) {
3228 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
32183229 return false;
32193230
32203231 // Upper quadword copied in order.
32233234
32243235 // Lower quadword shuffled.
32253236 for (unsigned i = 0; i != 4; ++i)
3226 if (Mask[i] >= 4)
3237 if (!isUndefOrInRange(Mask[i], 0, 4))
32273238 return false;
3239
3240 if (VT == MVT::v16i16) {
3241 // Upper quadword copied in order.
3242 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3243 return false;
3244
3245 // Lower quadword shuffled.
3246 for (unsigned i = 8; i != 12; ++i)
3247 if (!isUndefOrInRange(Mask[i], 8, 12))
3248 return false;
3249 }
32283250
32293251 return true;
32303252 }
44044426 break;
44054427 case X86ISD::PSHUFHW:
44064428 ImmN = N->getOperand(N->getNumOperands()-1);
4407 DecodePSHUFHWMask(cast(ImmN)->getZExtValue(), Mask);
4429 DecodePSHUFHWMask(VT, cast(ImmN)->getZExtValue(), Mask);
44084430 IsUnary = true;
44094431 break;
44104432 case X86ISD::PSHUFLW:
44114433 ImmN = N->getOperand(N->getNumOperands()-1);
4412 DecodePSHUFLWMask(cast(ImmN)->getZExtValue(), Mask);
4434 DecodePSHUFLWMask(VT, cast(ImmN)->getZExtValue(), Mask);
44134435 IsUnary = true;
44144436 break;
44154437 case X86ISD::MOVSS:
65806602 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
65816603 }
65826604
6583 if (isPSHUFHWMask(M, VT))
6605 if (isPSHUFHWMask(M, VT, HasAVX2))
65846606 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
65856607 getShufflePSHUFHWImmediate(SVOp),
65866608 DAG);
65876609
6588 if (isPSHUFLWMask(M, VT))
6610 if (isPSHUFLWMask(M, VT, HasAVX2))
65896611 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
65906612 getShufflePSHUFLWImmediate(SVOp),
65916613 DAG);
1137511397 isMOVLMask(M, VT) ||
1137611398 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
1137711399 isPSHUFDMask(M, VT) ||
11378 isPSHUFHWMask(M, VT) ||
11379 isPSHUFLWMask(M, VT) ||
11400 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11401 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
1138011402 isPALIGNRMask(M, VT, Subtarget) ||
1138111403 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
1138211404 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
1111 %t = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32>
1212 ret <16 x i16> %t
1313 }
14
15 ; CHECK: vpshufhw $27, %ymm
16 define <16 x i16> @vpshufhw(<16 x i16> %src1) nounwind uwtable readnone ssp {
17 entry:
18 %shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src1, <16 x i32>
19 ret <16 x i16> %shuffle.i
20 }
21
22 ; CHECK: vpshuflw $27, %ymm
23 define <16 x i16> @vpshuflw(<16 x i16> %src1) nounwind uwtable readnone ssp {
24 entry:
25 %shuffle.i = shufflevector <16 x i16> %src1, <16 x i16> %src1, <16 x i32>
26 ret <16 x i16> %shuffle.i
27 }