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AMDGPU/GlobalISel: Implement select() for 32-bit G_FPTOUI Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45883 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332082 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
4 changed file(s) with 54 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
1616 def gi_vsrc0 :
1717 GIComplexOperandMatcher,
1818 GIComplexPatternEquiv;
19
20 def gi_vop3mods0 :
21 GIComplexOperandMatcher,
22 GIComplexPatternEquiv;
1923
2024 class GISelSop2Pat <
2125 SDPatternOperator node,
454454 switch (I.getOpcode()) {
455455 default:
456456 break;
457 case TargetOpcode::G_FPTOUI:
457458 case TargetOpcode::G_OR:
458459 return selectImpl(I, CoverageInfo);
459460 case TargetOpcode::G_ADD:
481482 [=](MachineInstrBuilder &MIB) { MIB.add(Root); }
482483 }};
483484 }
485
486 InstructionSelector::ComplexRendererFns
487 AMDGPUInstructionSelector::selectVOP3Mods0(MachineOperand &Root) const {
488 return {{
489 [=](MachineInstrBuilder &MIB) { MIB.add(Root); },
490 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // src0_mods
491 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, // clamp
492 [=](MachineInstrBuilder &MIB) { MIB.addImm(0); } // omod
493 }};
494 }
7272 InstructionSelector::ComplexRendererFns
7373 selectVSRC0(MachineOperand &Root) const;
7474
75 InstructionSelector::ComplexRendererFns
76 selectVOP3Mods0(MachineOperand &Root) const;
77
7578 const SIInstrInfo &TII;
7679 const SIRegisterInfo &TRI;
7780 const AMDGPURegisterBankInfo &RBI;
0 # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1
2 --- |
3 define amdgpu_kernel void @fptoui(i32 addrspace(1)* %global0) {ret void}
4 ...
5 ---
6
7 name: fptoui
8 legalized: true
9 regBankSelected: true
10
11 # GCN-LABEL: name: fptoui
12 body: |
13 bb.0:
14 liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
15
16 ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
17 %0:sgpr(s32) = COPY $sgpr0
18
19 ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
20 %1:vgpr(s32) = COPY $vgpr0
21
22 %2:vgpr(s64) = COPY $vgpr3_vgpr4
23
24 ; fptoui s
25 ; GCN: V_CVT_U32_F32_e64 0, [[SGPR]], 0, 0
26 %3:vgpr(s32) = G_FPTOUI %0
27
28 ; fptoui v
29 ; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
30 %4:vgpr(s32) = G_FPTOUI %1
31
32 G_STORE %3, %2 :: (store 4 into %ir.global0)
33 G_STORE %4, %2 :: (store 4 into %ir.global0)
34 ...
35 ---