llvm.org GIT mirror llvm / a905325
[AArch64] Rename 'no-quad-ldst-pairs' to 'slow-paired-128' In order to follow the pattern of the existing 'slow-misaligned-128store' option, rename the option 'no-quad-ldst-pairs' to 'slow-paired-128'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293332 91177308-0d34-0410-b5e6-96231b3b80d8 Evandro Menezes 2 years ago
4 changed file(s) with 8 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
8484 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
8585 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
8686
87 def FeatureAvoidQuadLdStPairs : SubtargetFeature<"no-quad-ldst-pairs",
88 "AvoidQuadLdStPairs", "true",
89 "Do not form quad load/store pair operations">;
87 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
88 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
9089
9190 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
9291 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
221220
222221 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
223222 "Samsung Exynos-M1 processors",
224 [FeatureAvoidQuadLdStPairs,
223 [FeatureSlowPaired128,
225224 FeatureCRC,
226225 FeatureCrypto,
227226 FeatureCustomCheapAsMoveHandling,
235234
236235 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
237236 "Samsung Exynos-M2/M3 processors",
238 [FeatureAvoidQuadLdStPairs,
237 [FeatureSlowPaired128,
239238 FeatureCRC,
240239 FeatureCrypto,
241240 FeatureCustomCheapAsMoveHandling,
16511651 return false;
16521652
16531653 // On some CPUs quad load/store pairs are slower than two single load/stores.
1654 if (Subtarget.avoidQuadLdStPairs()) {
1654 if (Subtarget.isPaired128Slow()) {
16551655 switch (MI.getOpcode()) {
16561656 default:
16571657 break;
7878 bool CustomAsCheapAsMove = false;
7979 bool UsePostRAScheduler = false;
8080 bool Misaligned128StoreIsSlow = false;
81 bool AvoidQuadLdStPairs = false;
81 bool Paired128IsSlow = false;
8282 bool UseAlternateSExtLoadCVTF32Pattern = false;
8383 bool HasArithmeticBccFusion = false;
8484 bool HasArithmeticCbzFusion = false;
188188 }
189189 bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
190190 bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
191 bool avoidQuadLdStPairs() const { return AvoidQuadLdStPairs; }
191 bool isPaired128Slow() const { return Paired128IsSlow; }
192192 bool useAlternateSExtLoadCVTF32Pattern() const {
193193 return UseAlternateSExtLoadCVTF32Pattern;
194194 }
None ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+no-quad-ldst-pairs -verify-machineinstrs -asm-verbose=false | FileCheck %s
0 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+slow-paired-128 -verify-machineinstrs -asm-verbose=false | FileCheck %s
11 ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s
22
33 ; CHECK-LABEL: test_nopair_st